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News 2015
MPW Services Center for IC / MEMS Prototyping
http://cmp.imag.fr
Grenoble ‐ France
New price list, new quotation methods, news offers
The design center initiative Secured runs for 2015 and more in 2016
MyCMP on its way for 2015
New quotation methods for 2015
• We have analysed circuits and projects to check
the min, average and max scribe required for
inclusion in the floorplan of MPW.
• From February 2015, the scribe at CMP is reduced
and set to 120µm in X and Y for all MPW runs.
• This provides a significant bill contraction, positive for
our user community,
• Ex: considering a circuit area of : 3*2,5mm²
•
2014 charged area was : 8,88mm²
•
2015 charged area is now : 8,17mm²
•
Up to 10% charged area reduction
• To help us keep this scribe size, please follow our
design
guidelines
and
recommendations
described in our web site for future design
New quotation methods for 2015
• Many circuits designed to take advantage of CMP
minimum charge special offers (without scribe)
were not economically viable.
• Scribe will be added to quotation starting from the
1st mm².
• Minimum charge still apply as before on all MPW
run (please check on our web site) :
• Ex : for a minimum charge of 1mm²,
•
Designs with areas below 1mm² are charged 1,21mm²
•
1mm² designs are charged 1,21mm²
•
Designs with X * Y areas greater than 1mm² are charged (X+0,12)*(Y+0,12)mm²
New quotation methods for 2015
• Single price for academic and industry for most CMP MPW,
• Most technologies are charged with a minimum fixed area and have a significant price reduction for mm² above 5mm²,
• Ex : CMOS65GP : minimum charge : 1,21mm² • 6k€/mm² up to 5mm² and then 4,25k€/mm² for mm² above 5
• For 28nm FDSOI technology, an attractive charge per block has been defined. • Block area is 2*2mm² including scribe,
• For CNRS users, the block price is applied starting from the first mm². Please contact us for more information. New price list from Feb 2015 as it is on internet
ams (5)
0.18u CMOS C18A6
0.18u HV‐CMOS H18A6
0.35u CMOS C35B4C3
0.35u CMOS Bulk Micromachining
0.35u CMOS C35B4M3
0.35u CMOS‐Opto C35B4O1
0.35u SiGe BiCMOS S35D4M5
0.35u HV‐CMOS H35B4D3
STMicro (5)
28nm FDSOI CMOS28FDSOI
65nm CMOS CMOS065
1200 Euro/mm2 (2)
1200 Euro/mm2 (2) 650 Euro/mm2 (3)
650 Euro/mm2 (4) + 3700 Euro for 10 dies
890 Euro/mm2 (4)
810 Euro/mm2 (3)
890 Euro/mm2 (4)
1000 Euro/mm2 (5)
12000 Euro/mm2 (6)
36000 Euro/block ‐> Each block is 2x2mm2 (including scribes: effective design surface: 1,88x1,88mm2) Special price for CNRS Institutions: 9,000 €/mm2 (6) 6000 Euro/mm2 (6) if Area less or equal to 5mm2
30000 Euro + [(Area‐5) * 4250 Euro] if 5mm² < Area < 15mm² (7)
130nm CMOS HCMOS9GP
2200 Euro/mm2 (6) if Area less or equal to 5mm2
11000 Euro + [(Area‐5) * 2,000 Euro] if 5mm2 < Area < 15mm2 (7) 130nm SiGe BiCMOS9MW
2900 Euro/mm2 (6) if Area less or equal to 5mm2
11000 Euro + [(Area‐5) * 2300 Euro] if 5mm2 < Area < 15mm2 (7) 130nm SOI H9SOI‐FEM
2200 Euro/mm2 (6) if Area less or equal to 5mm2
11000 Euro + [(Area‐5) * 1800 Euro] if 5mm2 < Area < 15mm2 (7)
130nm CMOS HCMOS9A
0.18u BCD BCD8sP
2200 Euro/mm2 (6) if Area less or equal to 5mm2
11000 Euro + [(Area‐5) * 1900Euro] if 5mm2 < Area < 15mm2 (7)
2600 Euro/mm2 (6) if Area less or equal to 5mm2
13000 Euro + [(Area‐5) * 2100 Euro] if 5mm2 < Area < 15mm2 (7)
New price list & quotation method
• Illustrations :
• For designs in STM CMOS65,
• A 1mm² design is now charged : • A 1x2mm² design : • A 3x3mm² design : •
Prices
in 2015
Prices
in 2014
7,26k€
14,25k€
50,1k€
7,5k€
20,83k€
67,75k€
2,78k€
3,64k€
7,88k€
2,43k€
4,06k€
8,5k€
For designs in ams 0,35µm Opto,
• A 3mm² design is now charged : • A 2x2mm² design :
• A 3x3mm² design : Design Center initiative on 28nmFDSOI technology
Initiated by a STMicroelectronics, CEA, INRIA, Minalogic consortium, its objectives are to provide a full environment to answer Start up and small and medium companies needs for IC disruptive products or/and Product
applications.
Product
2
Company
ETI 2
ETI 1
Start up
Company
A
Start up
B
Services
IP libraries
EDA tools
access
Prototyping
Packaging
tests
Product 3
Product
4
Support / Design
Foundry
Research
1
Design Center initiative on 28nmFDSOI technology
Initiated by a STMicroelectronics, CEA, INRIA, Minalogic consortium, its objectives are to provide a full environment to answer Start up and small and medium companies needs for IC disruptive products or/and Product
applications.
Product
2
Company
ETI 2
ETI 1
B
Start up
Identification:
Company
A
Start up
Components
Technologies
Partners
Development:
Design
Prototyping
Proof of concept
Industrialization : Assessment
Project cost
Faisibility
1
Product 3
Product
4
Secured runs in 2015 and more in 2016
• 2014 was a difficult year for CMP :
• Delayed or even advanced 28nm MPW dead‐time
• Cancelled STMicroelectronics S65C14‐3 MPW
• Delayed ams A35C14_1 MPW
• To overcome these occurrences, CMP is working
with its partners to secure its MPW :
•
•
•
•
In 2015, we have secured the first 65nm MPW
We are working in securing the second one
We work with ams and ST to maximize CMP autonomy
In 2016, January and July 28nm MPW are secured
thanks to partnership with the design center intitiative
My CMP, a tool for CMP user high quality services
Thank you!