ECEN 468
Advanced Logic Design
Lecture 34: Chip I/O
ECEN 468 Lecture 34
Chip I/O
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Properties of I/O System
v  Drive large capacitances typical of off-chip signals
v  Operates at voltage levels compatible with other chips
v  Provide adequate bandwidth
v  Limits slew rates to control high-frequency noise
v  Protects chip against damage from electrostatic discharge (ESD)
v  Protects against over-voltage damage
v  Has a small number of pins (low cost)
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VDD and GND Pads
v  Squares of metal connected to package and on-chip power grid
v  For high-performance designs, over a half of I/O pins are for
P/G
v  Switching at pads => inductive noise => ground bounce
v  Decoupling capacitors
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Output Pads
v  First and foremost, sufficient driving capability
v  Tapered buffer chain
v  Guard rings to prevent latch-up
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Input Pads
v  Buffer to filter noise
v  ESD protection
v  Level-converting
v  Schmitt trigger to further filter noise
VY
A
Y
VY
VA
VA
t
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Electrostatic Discharge (ESD) Protection
v  ESD may cause
o  gate oxide breakdown
o  drain punchthrough
v  Protection: provide a controlled path do discharge
PAD
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Level Converter
VDDH
VDDL
Y
A
VDDL
A
Y
0~VDDH
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