1. No category

Boolean Simplifications
One of an ALU system is to execute the function below:Output = input + 1
input
4 bits
a,b,c,d
Output
4 bits
f,g,h,i
ALU System
(i) Design the ALU system above. In your design, include these items:(a) truth table
(b) minimized SoP for each output function (f,g,h,i) using VEKM.
(c) Realize the SoP function in section (a) in PLA.
(a)
truth table
output
a
0
input
b c
0 0
d
0
1
1
1
1
f
g
h
i
f
vekm
g h
i
Answer Q1(ii)
f
g
Boolean Simplifications
Figure 1
2
h
i
1. Convert the circuit of Figure 1 to all NAND gates.
(6 marks)
Adders
1. A full adder can be implemented in many different ways. Figure 2 shows how one
may be constructed from two half adders. Construct a truth table for this
arrangement, and verify that it operates as a FA.
(3 marks)
Figure 2
i.
Identify the function of A and B
X
Y
Z
3
A
B
Boolean Simplifications
For each of the following Boolean functions,
f1 ( w, x, y, z ) = ∑m (1,2,3,5,8,9,10,12,13,14)
f 2 ( w, x, y, z ) = ∑m (2,5,10,11,12,13,14)
(i) Determine the minimal sum of product using variable-entered map where w, x and y
are the map variables.
[12 Marks]
[CO3, PO1]
(ii) Realized the equations using 4x5x3 Programmable Logic Array (PLA) having only
the true outputs. Draw the logic diagram of the realization using PLA diagram in
Appendix A.
[13 Marks]
[CO3, PO1]
4
VHDL / FPGA
(a) Figure 1 shows the VHDL code of combinational network that implements a function
of its inputs based on either logic or arithmetic operations. Sketch function table of
this circuit.
[7 Marks]
ENTITY test1 IS
port(a, b
sel
zero
f
END test1;
F
i
:
:
:
:
in std_logic_vector(7 downto 0);
in std_logic_vector(2 downto 0);
out std_logic;
out std_logic_vector(7 downto 0));
architecture behavioral of test1 is
begin
process(sel)
variable temp: std_logic_vector(7 downto 0);
begin
case sel is
when "000" =>
temp <= a and b;
when "100" =>
temp <= a and b;
when "001" =>
temp <= a or b;
when "101" =>
temp <= a or b;
when "010" =>
temp <= a + b;
when "110" =>
temp <= a - b;
when "111" =>
if a < b then
temp <= "11111111";
else
temp <= "00000000";
end if;
when others =>
temp <= a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
f <= temp;
end process;
end behavioral;
Figure 1
5
(b) A bit slice (1-bit) Arithmetic Logic Unit (ALU) design is shown in Figure 2. The
multiplexer can select four different functions. Designs the logic circuit for Block
A. Justify your design using truth table.
[8 Marks]
[CO3, PO1]
A
Figure 2
6
APPENDIX A : Programmable Logic Array Diagram
7
Boolean Simplifications
A digital circuit with the following Boolean function
f 1 = AB + AC + ABC
f 2 = A BC + BC + AC + AB
are to be implemented on these template-based logic device. As a system engineer,
you are to implement the function using the following resources;
(a) A 4x8x3 Programmable Array Logic (PAL) device in Appendix A.
(b) A 3x6x3 Programmable Logic Array (PLA) device in Appendix B.
[15 Marks]
[CO3, PO4]
Boolean Simplifications
Use the K map to simplify the expression = + + . Draw the simplified logic
diagram. Later on, simplify the logic diagram below using K map and draw the final
simplified logic diagram.
Figure 1
8
[10 Marks]
[CO3, PO4]
9