Download Report

EE 457 HW1
EE 457 HW 1
Digital Design Review
Redekopp  Puvvada
Name: _________________________________________
Due: See Website
Score: ________
Please post any questions regarding HW problems on Piazza.
1. (25 pts.) Mealy machine Design
Design a simple (though inefficient) DIVIDER to divide X by Y to obtain
quotient Q and remainder R. All are 4-bit unsigned numbers. Y is a non-zero
number.
Method: Subtract Y from X repetitively until Y does not go through X anymore.
There shall be an INITIAL state I, COMPUTE state C, and a DONE state D.
Remain in the I state until the START command S is received. In the initial state,
clear the Q register. In the compute state, perform the subtraction (X - Y), and
based on borrow output from the subtractor, which indicates whether Y went
through X or not, update X with (X - Y) and increment Q. If Y did not go through
X, you should exit the compute state (without updating X or incrementing Q) and
go to the Done state. Remain in the done state while the END command is 0.
Once END is 1 then go back to the initial state. While in Done state, the register
X shall contain the remainder R and the register Q shall contain the quotient.
Use two 4-bit registers described in the datapath below for X and Y. Use
74LS163A counter for Q. Use one-hot state assignment and three D-FFs for your
state memory. If you do not know one-hot method for designing a control unit
please get help from your TA, the grader, or the instructor. State machine design
using one-hot state assignment will be covered in the first week of classes in
EE457.
Incomplete designs of the DPU (Datapath unit) and the CU (Control unit) are
provided on the next two pages. Complete the designs. All inputs to logic blocks
must be in terms of the primary inputs: XIN[3:0], YIN[3:0], START, END, RSTb
and the SYSCLK or other intermediate signals that you generate. You may tie
unused inputs to appropriate constants GND or VDD if desired. You should
define two intermediate signals: X_LOAD, Y_LOAD (data enables for the
respective registers), Q_INC (count enable), Q_CLR (counter reset), and
BORROW.
For sample values of X = 1101 (thirteen) and Y = 0011 (three), draw typical
waveforms for this divider showing the clock, the inputs S and E, the control
signals from the controller to the datapath unit such as X_LOAD, Q_INC
(increment counter), the values of X and Q over time, the state Flip-flop outputs,
QI, QC, and QD over time, etc.
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
1
EE 457 HW1
Q1 Datapath:
R[3:0]
Q[3:0]
S
74LS283
(4-bit Adder)
[C0=Carry-In,
C4=Carry-out]
Q[3:0]
D[3:0]
4-bit Register with active-hi
Data Enable (EN) and
active-hi Tri-State Output
Control (OE)
C0
A0
A1
A2
CLK
CLR
EN
OE
A3
B0
B1
4-bit Adder
X_M_Y[3:0]
(X_Minus_Y)
Y[3:0]
XIN[3:0]
B[3:0] A[3:0]
2-to-1 Mux
(S=0, Y<=A,
S=1 Y<=B)
S0
S1
S2
S3
X_M_Y[0]
X_M_Y[1]
X_M_Y[2]
X_M_Y[3]
X_M_Y[3:0]
(X_Minus_Y)
B2
C4
Q[3:0]
D[3:0]
B3
YIN[3:0]
CLK
CLR
EN
OE
SYSCLK
74LS163A
(4-bit Counter)
Vdd
P0
P1
P2
Q0
Q1
Q2
P3
/LOAD
Q3
CLK
RSTb
Q[3:0]
RCO
/CLR
ENP
ENT
Q_INC
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
2
Q[0]
Q[1]
Q[2]
Q[3]
EE 457 HW1
Q1 Control Unit:
NSL
SM
OFL
START
DI
D
END
/PRE
Q
QI
CLK Q
Add other inputs
from the datapath
/CLR
DC
D
/PRE
Q
QC
CLK Q
/CLR
DD
D
/PRE
Q
QD
CLK Q
/CLR
RSTb
(active-lo)
SYSCLK
Use labels to make connections where appropriate rather
than drawing long, looping wires
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
3
EE 457 HW1
Q1 Sample Waveform:
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
SYSCLK
RSTb
START
END
X_IN
13 dec.
Y_IN
3 dec.
X
Y
X_M_Y
BORROW
Q (CNT)
QI
QC
QD
X_LOAD
Y_LOAD
Q_CLR
Q_INC
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
4
EE 457 HW1
2. (25 Pts.) Datapath and Control Design
You are given two 4-bit unsigned numbers, P and Q. You need to compare them and
deposit the smaller in SMALL_REG and the bigger BIG_REG. The next page contains
a complete data path. Notice that you can bring either P or Q on bus #1 (B_ONE) or bus
#2 (B_TWO). SMALL_REG is only tied (i.e. connected) to B_ONE where as BIG_REG
is only tied to B_TWO.
2.1. 4-state State Machine
2.1.1. Complete the state diagram below by writing the state transition conditions.
1
/RESET
PQL
START
Load P (from B_ONE) into Small
Load Q (from B_TWO) into Big
I
Initial
START
CPQ
Compare P (on
B_ONE) w/ Q
(B_TWO)
QPL
Load Q (from B_ONE) into Small
Load P (from B_TWO) into Big
1
2.1.2. Complete the one-hot implementation of the above 4-state state machine on page
7. Before you produce the outputs, answer the following questions.
2.1.2.1.
[Yes / No] (Circle one) Can we say that whenever we put P or Q on one of
the two buses, we may put the other on the other bus?
2.1.2.2.
[Yes / No] (Circle one) Can we say that, in the initial state, we may drive
the buses even though it is not necessary?
2.1.2.3.
[Yes / No] (Circle one) Can we say that we either load both
SMALL_REG and BIG_REG or load neither?
2.1.3. Complete the waveform on page 8.
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
5
EE 457 HW1
Q2 Datapath. Note: This datapath is complete and is for your reference.
B_TWO[3:0]
/P2B1
(First [B_ONE] Greater than
Second [B_TWO])
AEQB
ALTB
4-bit Register with active-hi Data
Enable (EN) and active-hi Tri-State
Output Control (OE).
CLR is active-high
P[3:0]
B_ONE[3:0]
D[3:0]
/Q2B1
SYSCLK
CLK
GND
CLR
EN
/Q2B2
Q[3:0]
Q[3:0]
B_ONE[3:0]
B[3:0] A[3:0]
FGS
AGTB
SMALL[3:0]
OE
SMALL_LOAD
VDD
D[3:0]
B_TWO[3:0]
Q[3:0]
4-bit Register with active-hi Data
Enable (EN) and active-hi Tri-State
Output Control (OE).
CLR is active-high
/P2B2
SYSCLK
GND
CLK
CLR
EN
OE
BIG_LOAD
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
VDD
6
BIG[3:0]
EE 457 HW1
Q2.1 Control Unit. Complete this.
SMALL_LOAD
VDD
/PRE
D
SYSCLK
Q
QI
/PRE
D
CLK Q
QPQL
CLK Q
SYSCLK
/CLR
Q
BIG_LOAD
/CLR
/RESET
/P2B2
VDD
VDD
/Q2B1
START
QI
D
SYSCLK
/PRE
Q
CLK Q
QCPQ
/PRE
D
SYSCLK
QQPL
CLK Q
/P2B1
/RESET
/Q2B2
/CLR
/CLR
/RESET
Q
Use labels to make connections where appropriate rather
than drawing long, looping wires
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
7
EE 457 HW1
Q2.1 Waveform. Complete this based on your design.
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
SYSCLK
/RESET
START
QI
QCPQ
QPQL
QQPL
/P2B1
/Q2B1
/P2B2
/Q2B2
FGS
SMALL_LOAD
BIG_LOAD
P
06 dec.
03 dec.
Q
02 dec.
05 dec.
SMALL
XX
02 dec.
03 dec.
BIG
XX
06 dec.
05 dec.
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
8
EE 457 HW1
2.2. 3-state State Machine
2.2.1. The previous 4-state state machine is a ____________ (Mealy / Moore) as the
outputs generated are not influenced by the current inputs. The outputs are
completely determined by the current state.
Let us now reduce the states by combining CPQ and PQL into CPQL "compare and
load". The load operation is conditional in the CPQL state as can be seen below.
2.2.2. This 3-state machine is a ____________ (Mealy / Moore).
Complete the state diagram below by correctly labelling the transitions.
START
/RESET
CPQL
I
Initial
START
Compare P (on B_ONE) w/ Q (B_TWO)
If appropriate:
Load P (from B_ONE) into Small
Load Q (from B_TWO) into Big
QPL
Load Q (from B_ONE) into Small
Load P (from B_TWO) into Big
1
2.2.3. Complete the one-hot implementation of the above 3-state state machine on page
10.
2.2.4. Complete the waveform on page 11.
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
9
EE 457 HW1
Q2.2 Control Unit. Complete this.
SMALL_LOAD
VDD
D
SYSCLK
/PRE
Q
QI
START
QI
CLK Q
D
SYSCLK
/CLR
/PRE
Q
QCPQL
CLK Q
BIG_LOAD
/CLR
/RESET
/P2B2
VDD
/Q2B1
D
SYSCLK
/PRE
Q
QQPL
CLK Q
/P2B1
/CLR
/RESET
/Q2B2
Use labels to make connections where appropriate rather
than drawing long, looping wires
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
10
EE 457 HW1
Q2.2 Waveform. Complete this.
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
SYSCLK
/RESET
START
QI
QCPQL
QQPL
/P2B1
/Q2B1
/P2B2
/Q2B2
FGS
SMALL_LOAD
BIG_LOAD
P
04 dec.
09 dec.
Q
08 dec.
01 dec.
SMALL
XX
04 dec.
01 dec.
BIG
XX
08 dec.
09 dec.
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
11
EE 457 HW1
3. (13 pts.) Combinational Logic Design
We need an adder to perform Y = (X + 11 dec.) MOD 16. X and Y are 4-bit unsigned
numbers represented as X[3:0] and Y[3:0]. Note: 11 dec. = 1011 bin. Build this special
adder from SSI gates (Small Scale Integrated circuits such as INVERTER, AND, OR, XOR,
NAND, NOR, and XNOR). You may refer to full adder and half-adder designs in your book
if you wish. However you should use as few gates as possible.
The constant to be added is always 11 dec. and not a variable! This should make
optimization possible. Note: MOD 16 means modulo 16 so if X=12 dec. then 12 + 11 = 23;
23 MOD 16 = 7. Hence Y = 7 dec. Because of the MOD 16 operation you need not produce
a carry out (a.k.a. Y4) output.
X3
X2
X1
X0
Y3
Y2
Y1
Y0
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
12
EE 457 HW1
4. (12 pts.) State Diagram Design
In previous problems we have seen "one-hot" coded data where only 1-bit can be a '1'. Here
the data is ”two-hot" coded. There shall be TWO ones and SIX zeros in any order.
Example: "01001000" is correctly coded. Design a state machine to verify whether an 8-bit
value: B[7:0] is correctly coded using "two-hot" coding. In the state diagram below, the
states C01, C11, C21 stand for "Counted 0 '1s'", "Counted 1 '1s'", and "Counted 2 '1s'",
respectively. Complete the state transition conditions. Use BIT or ~BIT together with
signals such as MC7, MC6, and MC5 as necessary.
B0
B1
B2
B3
D0
D1
D2
D3
B4
B5
B6
B7
D4
D5
D6
D7
74LS163A
(4-bit Counter)
GND
GND
GND
P0
P1
P2
Q0
Q1
Q2
GND
VDD
P3
/LOAD
Q3
SYSCLK
QINI
CLK
S0
Y
8-to-1
Mux
BIT
I0
I1
I2
MC7
~BIT
I0
I1
I2
MC6
I0
I1
I2
MC5
Y
S1
S2
I0
I1
I2
RCO
/CLR
ENP
ENT
QC01
QC11
QC21
START
/RESET
I
START
Initial
ACK
C01
C11
C21
I <= I+1
I <= I+1
I <= I+1
WRONG
RIGHT
I <= I+1
I <= I+1
ACK
ACK
ACK
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
13
EE 457 HW1
5. (5 pts.) Datapath Design
Design a special down counter which counts down (7,6,5,…). However it shall always skip
4. So the sequence shall be 7,6,5,3,2,1,0,7,6,5,3,2,1,0,…. Use the mux to skip 4. Complete
all the connections and generate the select logic.
3-bit (A-B)
Subtractor
A0
A1
A2
1
0
0
B0
B1
B2
2-to-1, 3-bit
wide mux
A0
A1
A2
S0
S1
S2
B0
B1
B2
S
Register
Y0
Y1
Y2
BIT
Q0
Q1
Q2
D0
D1
D2
CLK
S
SYSCLK
6. (20 pts.) State Machine Design
6.1. Reproduced below is the state diagram for the divider from your classnotes. A student
has modified state transition conditions on the two diverging arrows on the "C" state as
shown.
Class Notes Design
Modified Design
START
/RESET
X>Y
X>=Y
I
C
Initial
Compute &
Update
If X >= Y
X <= X-Y
Q <= Q+1
START
X <= XIN
Y <= YIN
Q <= 0
X>=Y
C
START
END
Compute &
Update
If X >= Y
X <= X-Y
Q <= Q+1
D
Done
X>Y
END
Does it work? YES / NO (Circle one)
It if works, explain how it is better or worse in
performance? If it does not work, state why it
does not work.
_____________________________________
_____________________________________
_____________________________________
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
14
START
EE 457 HW1
6.2. In light of the above question, can you suggest an improvement to the Moore machine
for the divider (reproduced from the classnotes below) by modifying the state transition
conditions only?
Class Notes Design
Explanation of improvement (if possible) or
/RESET
U
why no improvement is possible:
Update
X>=Y
_____________________________________
I
C
X <= X-Y
Initial
START
Compute
Q <= Q+1
X <= XIN
Y <= YIN
Q <= 0
_____________________________________
1
_____________________________________
END
D
X>=Y
_____________________________________
Done
START
END
_____________________________________
6.3. Mr. Trojan suggested a better Moore machine for the divider (better than the one in the
classnotes and reproduced above) as shown below.
Class Notes Design
Using the example of 40 / 2 = 20, R=0,
/RESET
Note: The X+Y
X>=Y
Note: The If is
and Q-1
U
explain why this is better than our classnotes
removed
Update
design.
I
C
X>=Y X <= X+Y
Compute
&
_____________________________________
Initial
Q <= Q-1
START
Update
X <= XIN
Y <= YIN
Q <= 0
_____________________________________
X <= X-Y
Q <= Q+1
END
D
Done
_____________________________________
1
_____________________________________
END
_____________________________________
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
15
EE 457 HW1
6.4. Miss Trojan says that there is still a little more to improve by playing with the state
transition arrows and conditions! Can you guess what is in her mind by completing the
design below?
Class Notes Design
/RESET
U
Note: The If is
removed
START
I
Update
C
Initial
START
X <= XIN
Y <= YIN
Q <= 0
Note: The X+Y
and Q-1
X <= X+Y
Q <= Q-1
Compute &
Update
Using the example of 40 / 2 = 20, R=0,
explain why this is a little better than Mr.
Trojan's design.
_____________________________________
_____________________________________
X <= X-Y
Q <= Q+1
END
D
Done
_____________________________________
1
_____________________________________
END
_____________________________________
6.5. Miss Trojan says that the resulting datapath of Mr. Trojan's design is more expensive.
Mr. Trojan says the opposite. Explain who is right and why.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
© Copyright 2004 Gandhi Puvvada. Edited by Mark Redekopp with permission.
16