WHITE PAPER: WP006
Isolated Full Bridge Converters
Efficient DC-DC Brick Converters
Using eGaN FETs
EFFICIENT POWER CONVERSION
Alex Lidow PhD, CEO and Johan Strydom, PhD, Vice President Applications Engineering, Efficient Power Conversion Corporation
Isolated full bridge converters are widely used in servers and
A straightforward topology that we can use to explore the capabilities of
enhancement mode gallium nitride transistors in isolated DC-DC converters is a full bridge primary side and a synchronous rectifier secondary side.
Two test vehicles were chosen; a fully regulated eighth brick format with a
nominal 48 VIN and 12 VOUT, and a PoE-PSE half brick format with a nominal
48 VIN and 53 VOUT. In each case it is shown that eGaN FETs allow the user to
significantly improve efficiency, and therefore power output and cost, while
maintaining the required size constraint.
telecommunication systems and are available in a variety of
standard sizes, input and output voltage ranges. Their modularity, power density, reliability and versatility has simplified and to
some extent commoditized the isolated power supply market.
Brick Converters
As these types of converters are of a defined size, designers are motivated to come up with innovative ideas to increase the converters’ output power and power density. For example, within the spectrum of eighth brick converters there are numerous input and output voltage configurations, topologies and output range tolerances
(e.g., regulated, semi-regulated, un-regulated), and they all have a very similar maximum power loss at full power; between 12-14 W. This is a physical limit based on the
fixed volume of the converter and the common method of heat extraction. Thus, for an eighth brick converter that is 90% efficient (η = 0.9) at full load, the maximum
output power, assuming 14 W loss, will be:
Poutmax = Pmax loss x η/(1-η) = 14 W x 0.90/(1-0.90) = 126 W
If the efficiency can be improved by just 2%, the output power is increased to 160 W. That is 28% more output power.
It is possible to reduce the power loss in the magnetic components by increasing the operating frequency, however, this is not normally done because the increase
in the silicon MOSFET switching losses outweighs the potential improvement. For that reason, the operating frequency is typically reduced to the point where the
magnetic structure size is maximized within the overall brick size constraints.
Comparing Isolated Brick Converters
The eGaN FET-based eighth brick converter developed for this study is not
necessarily an optimal solution. The design goal was to deliberately push the
operating frequency much higher than current commercial systems to show
that eGaN devices could enable someone skilled in power supply design to
take advantage of the superior switching characteristics to develop nextgeneration products.
48 V to 12 V Brick Efficiency Comparison
100%
98%
96%
94%
Efficiency
Even when limiting our comparison to regulated 12 V output, eighth brick converters, there are still a significant number of variations between commercial
designs. Over time, advances in devices, materials, construction and other innovations have enabled greater and greater output power. Even so, the efficiency achieved in a specific brick converter can easily be improved simply by
allowing the converter to increase in size. This increase in efficiency with size is
shown in figure 1 by comparing eighth brick and quarter brick efficiency for the
same generation products.
92%
90%
88%
86%
Quarter Brick
84%
Eighth Brick
82%
80%
0
5
10
15
20
25
30
Output Current (A)
Figure 1: Comparison of eighth brick and quarter brick efficiencies [1, 2].
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 1
35
WHITE PAPER: WP006
Isolated Full Bridge Converters
A Fully Regulated eGaN® FET-Based Eighth Brick Converter
L
36 V-75 V
For the 48 V to 12 V eGaN FET-based eighth brick converter, a phase-shifted full bridge
(PSFB) converter with a full bridge synchronous rectifier (FBSR) topology was chosen
as shown in figure 2 (A more complete schematic is shown in the figure 3). The objective was to show that, due to their relatively small device size, a significant number of
eGaN FETs can be used within the restrictive eighth brick size limitations.
Isolation
Feedback
Isolation
Figure 2: 180 W 1/8th brick fully regulated, phase shifted full bridge (PSFB) topology,
with full bridge synchronous rectification (FBSR) using eGaN FETs
Figure 2: 200 W eighth brick fully regulated, phase shifted full bridge (PSFB)
topology, with full bridge synchronous rectification (FBSR) using eGaN FETs.
VDD
HB
HOH
HOL
HS
EPC2001
10
4.7uF
LM 5113
GND
ER18
HI
LI
VSS
LOL
LOH
OUT1
OUT2
EPC2001
GND
Isolated bias supply
22uF
10
5V pri
LOH
LOL
VSS
LI
HI
LM 5113
5V pri
HS
HOL
HOH
HB
Vdd
5V sec
0.1uF
4.7uF
5 turns
EPC2001
EPC2001
10
OUT2
OUT1
Deadtime adjust
Deadtime adjust
0.006 Ohm
2.0k
0.1uF
0.1uF
5V pri
EPC2001
HS
HOL
HOH
HB
Vdd
LM 5113
5V sec
HI
LI
VSS
LOL
LOH
GND
2 turns
EPC2001
4.7uF
2.2
LM 5113
22uF x 3
2.2
EPC2001
Isolation and logic
12V
GND
ER18
4.7uF
1.1uF ER18
2.2
VDD
HB
HOH
HOL
HS
2.2
LOH
LOL
VSS
LI
HI
22pF
Controller
2.2uF x 3
10
0.1uF
Gate Drive
EPC2001 x 4
0.1uF
5V pri
RT
VIN
SS
VCC
COMP
VFB OUT1
CS
OUT2
GND
Gate Drive
EPC2001 x 4
0.68uH
VIN
GND
7.5k
Gate Drive
Gate Drive
Cin
The choice of transformer turns ratio (5:2) means that, at 60 VIN, the secondary side
winding voltage is only 24 V but the overshoot can be as high as 60 V without a clamp.
For this reason 100 V devices were used on both the primary the secondary sides. For
optimal performance, the Texas Instruments LM5113 half bridge driver, designed for
eGaN FETs, was chosen. The actual prototype is shown in figure 4 and is compared
side by side to a similar [3] silicon-based converter. The significant amount of unfilled
PCB area (green space) could certainly be further exploited to improve efficiency.
LM 5030
12 V/17 A
Cout
EPC2001
OV
Deadtime adjust
Deadtime adjust
Isolation and feedback
Figure 3: eGaN FET-based 200 W 1/8th brick schematic.
Simplified schematic of eGaN FET-based eighth brick 36 V – 75 V to 12 V / 15 A converter operating at 333 kHz
Transformer
Output
Inductor
Primary Side FB
eGaN FET based brick (Top View)
MOSFET based brick (Bottom View)
Output Capacitors
MOSFET based brick (Top View)
Secondary Side
FBSR
Primary
Side
HB
Secondary Side
SR
Bias
Supply
Bias
Supply
Transformer
Input
Capacitors
Output
Inductor
eGaN FET based brick (Bottom View)
Figure 4: Comparison between the eGaN FET-based eighth brick converter (lower image) and
Figure 3: Comparison between the 48 V to 12 V eGaN FET-based eighth brick converter prototype (lower image)
the silicon based converter (upper image) [3] showing top and bottom views (scale in inches).
and comparable silicon based converter (upper image) [3] showing top and bottom views (scale in inches).
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 2
WHITE PAPER: WP006
Isolated Full Bridge Converters
Eighth Brick Comparison
Efficiency and power loss comparison between eighth brick converters are
shown in figure 5 and figure 6 respectively. Despite the eGaN FET converter
operating at 50% higher frequency, it is able to produce 33% more output
power for the same power loss.
96%
375 kHz eGaN FET
94%
92%
More improvement is possible. For example, the full bridge synchronous rectifier, using 100 V eGaN devices, could be changed to a center tap with two
devices in parallel (similar to the MOSFET based design). Instead of the output inductor current flowing through two devices in series, it would then flow
through two devices in parallel. This would reduce the secondary-side device
conduction losses by 75% (i.e. 1.3 W or roughly 10% of total power losses) at
14 A output current.
Efficiency
250 kHz MOSFET
90%
88%
86%
84%
0
2
4
6
8
36 V eGaN FET
36 V MOSFET
48 V eGaN FET
48 V MOSFET
60 V eGaN FET
60 V MOSFET
10
Output Current (A)
12
14
16
18
Next Generation Eighth Brick
A next-generation MOSFET-based eighth brick converter [3] has an output
power increase of 67%, to 240 W, with a peak efficiency two percentage points
higher than the converter used in our comparison with eGaN FETs. This improved performance was achieved through multiple improvements. Some key
changes as follows:
Figure 4: Efficiency comparison between eighth brick converters .
Figure 5: Efficiency comparison between eighth brick converters.
a) Switching frequency was reduced by 30%, down to 180 kHz. Core cross
sectional area for both the transformer and output inductor was increased to accommodate the lower frequency.
14
b) Secondary side center-tap (CT) synchronous rectifier MOSFET device voltage was reduced to 60 V from 100 V. These new MOSFET devices have
about half the COSS x RDS(ON) product than the previous generation devices
and 25% lower RDS(ON).
12
Power Loss (W)
10
8
250 kHz MOSFET
c) Primary side topology was changed to full bridge (FB) from half bridge
(HB).
375 kHz eGaN FET
6
4
2
0
0
2
4
6
8
36 V eGaN FET
36 V MOSFET
48 V eGaN FET
48 V MOSFET
60 V eGaN FET
60 V MOSFET
10
Output Current (A)
12
14
16
Figure
5: Power
loss
comparisonbetween
between eighth
eighth brick
Figure
6: Power
loss
comparison
brickconverters.
converters.
d) Primary side MOSFET devices were doubled in number (for FB). Also, a
smaller die size was chosen to have one half the COSS and about one third
the QGD of the current eighth brick converter devices, but double the
RDS(ON).
18
e) To accommodate these 60 V devices, it is calculated that the transformer
turns ratio was changed from 4:3:3 (HB:CT) to 9:3:3 (FB:CT). This requires
a 100%+ duty cycle at 36 VIN to maintain regulation and, at 75 VIN, the secondary winding voltage is 50 V (excluding commutation spike voltage).
f) The use of a digital controller reduced the required board area for control, and also enabled nearly a 100% duty cycle.
Considering (b), (e) and (f) above, there were significant advantages from going to a lower RDS(ON) secondary side devices , whereas (a) and (d) improved
efficiency by reducing primary side switching losses.
To see what eGaN FETs can offer to further improve this benchmark performance, consider the comparison in table 1. To make direct comparison possible, the equivalent eGaN FETs have been scaled to match the RDS(ON) of the
MOSFETs.
Using eGaN FETs for the primary side devices, a 60% lower QOSS losses and a
staggering 93% reduction in switching figure of merit (RDS(ON) x QGD) can be
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 3
WHITE PAPER: WP006
Isolated Full Bridge Converters
achieved. The actual switching loss improvement is dependent on gate
drive strength and layout. To put this in perspective, the changes in QOSS and
QGD between the next-generation eighth brick and the previous version is
devices are 45% and 42% respectively. Although the improvement in QOSS
does not offer much of an efficiency improvement, it is estimated that the
reduction in switching time can reduce the primary side switching losses by
as much as 2.3 W at full load. As for the secondary side devices, the key is to
reduce RDS(ON) as much as possible while limiting the QOSS and QG losses. In
this case, the equivalent eGaN FET has been scaled to have the same total
synchronous rectifier switching charge (QG+QOSS). The equivalent eGaN FET
has 40% lower RDS(ON) while offering 100 V capability. At full output current (20
A), this 40% reduction in RDS(ON) is equivalent to 1.3 W, or roughly 10% reduction in total power loss. All of these eGaN FET characteristics could result in as
much as 28% lower power losses if applied to this state-of-the-art converter.
This would improve full load efficiency by more than a full percentage point
and could allow the full load output power to increase by 25% to 300 W.
Primary Side
MOSFETs
eGaN FETs
Relative eGaN FET
Improvement
HAT2174
EPC2007
Device voltage rating
RDS(ON) (mΩ)
QOSS (nC @ 50 Vds)
QGD (nC @ 50 Vds)
Switching FOM (RDS(ON) x QGD )(pC Ω)
100 V
22
22#
8.4
184
100 V
22
8.9
0.56
12
same
same
60% less
93% less
93% less
Secondary Side
Device voltage rating
Total RDS(ON) (mΩ)
QOSS (nC @ 50 Vds)
QG (nC)
SR FOM(R DS(ON) x (QG+QOSS))(pC Ω)
HAT2266
60 V
9.5
18#
25
237
EPC2001
100 V
5.6
35
8
59
40 V more
40% less
17 nC more
17 nC less
75% less
# calculated from datasheet graphs
Table 1: Comparison of next generation eighth brick MOSFET devices and
equivalent eGaN FETs
Isolated PoE-PSE Converters
The Power over Ethernet (PoE) standard has been evolving over the last few years. The main focus is the systematic increase of power with each new class
and type. According to the IEEE 802.3at standard on PoE [4], the power source equipment (PSE) requires an output voltage between 44 V and 57 V for PoE
type 1 and between 50 V and 57 V for PoE type 2 (PoE+). It also has to be capable of delivering 15.4 W (type 1) or 25.5 W (type 2) per port on the PSE Ethernet
switch. For the PSE, the output requires some form of regulation, but tight regulation is not required. It is interesting to note that there is an increase in minimum voltage to account for the increase in maximum line droop with the increased power level – future PSE equipment may require even smaller voltage
ranges closer to the 57 V maximum. With 24, 36 or even 48 ports per Ethernet switch being typical, the total PSE supply power requirement can be as high as
1.2 kW. This drives the need for higher efficiency and higher power density converters.
It is difficult to remove more than 35 W of losses from a typical PoE-PSE half brick converter, even with significant airflow or base plate. In figure 8, the resultant output
power that is achievable in a half brick is plotted versus the required minimum full load efficiency to achieve this. Since most commercial half brick PSE converters already
have about 95% efficiency, even a half percent efficiency improvement is important and can increase output power by as much as an additional 100 W. As with other
brick converters, the most important aspect is cost per watt, thus by increasing brick efficiency and therefore output power, the cost of the module per watt is reduced.
Comparing Isolated PoE-PSE Converters
It is difficult to compare half brick PoE-PSE converters because there are a significant number of variations between current commercial designs. Each manufacturer’s
98%
eGaN FET Prototype
96%
Commerical half brick
PSE converters
94%
Efficiency
92%
90%
88%
Minimum Required Efficiency
86%
84%
Nominal Half Brick Full Load Efficiency
0
100
200
300
400
500
600
Output Power (W)
700
800
900
1000
Figure 8: Minimum required efficiency for a half brick converter to achieve the specific output power (assuming a maximum power loss of 35 W).
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 4
WHITE PAPER: WP006
Isolated Full Bridge Converters
advances in topology, materials, construction, layout and other innovations have allowed ever greater output power and enable them to differentiate themselves in the
market. With each generation of power supply, an increase in output power level is achieved as each manufacturer improves their design in terms of structure, layout and
topology. Determining the ‘best’ solution is an iterative process, which may further be complicated by differences in opinions as to what exactly defines the best solution.
A two-phase interleaved converter design with a single stage conversion was selected for this eGaN FET demonstration. The design goal was to deliberately push the
operating frequency much higher than current commercial systems to show that eGaN FETs could enable someone skilled in power supply design to develop stateof-the-art next-generation products with increased efficiency and output power
For larger brick sizes, such as the half brick, the resultant output power levels and overall converter losses are high enough that multiple power devices are usually
required for each switch – both from a thermal requirement as well as from a minimum available RDS(ON) (largest die size) perspective. Thus if the converter is split into
two converters – each for half the power – the overall power device count is not affected. The added cost and size of using an increased number of inductors and transformers is also small, as these components are smaller and interleaving of the power converters allow a reduction in the required output capacitance. Furthermore,
the size and height restrictions of the bricks mean that a single high-power transformer is height limited with a less optimal magnetic pathlength than two smaller
transformer cores. The remaining differences, gate drive and control, are likely the determining factors. Can their cost increase be justified through better efficiency
and therefore increased output power?
L
38 V - 60 V
53 V / 6.6 A
Cout
An eGaN® FET-Based PSE Converter
L1
Gate Drive
Gate Drive
Gate Drive
Gate Drive
Cin
For the 48 V to 53 V eGaN FET-based half brick PSE converter, a phase-shifted full
bridge (PSFB) converter with a full bridge synchronous rectifier (FBSR) topology was
chosen as shown in figure 9 (A more complete schematic is shown in figure 10). Not
only does the interleaving of two phases avoid any of the complexity associated with
paralleling devices (see Shootout Volume 5, Paralleling eGaN FETs - Part 1, Johan
Strydom, http://powerelectronics.com/power_semiconductors/gan_transistors/
paralleling-egain-fets-part1-0911/), the use of two separate converters conceptually
allow for phase shedding to improve light load efficiency. Efficiency results showing
that light load efficiency can be improved by at least 2% for one and two-phase operation are plotted in figure 11. Each converter operates at a 250 kHz device switching frequency, resulting in an output ripple frequency of 1 MHz. Figure 12 shows that
EPC2001 x 4
EPC2010 x 4
Controller
Isolation
Feedback
Isolation
Figure 9: 350 W fully regulated, phase shifted full bridge (PSFB) topology,
with full bridge synchronous rectification (FBSR) using eGaN FETs (two 250
kHz converters interleaved for half brick design).
0.2 µH
VIN
CT1
2.2 µF x 18
CT
GND
Enable
0V
Isolation
0.1 µF
5 Vsec
GND
LM5113
OUT 1
OUT 2
DSP Controller and Logic
Zero
4.7 µF
LM5113
ER23
4 turns
Q4
EPC2001
Q3
EPC2001
Zero
VDD
HB
HOH
HOL
HS
Q2
EPC2001
T1
H1
L1
VSS
LOL
LOH
Isolated bias supply
Q1
EPC2001
GND
LOH
LOL
VSS
L1
H1
Zero
3.3 V Regulator
5 Vpri
5Vpri
HS
HOL
HOH
HB
VDD
CT1
Circuit
2X
0.1µF
5 Vpri
4.7 µF
Zero
Isolation
OUT 3
OUT 4
L2
Isolation
53 V
OUT 8
OUT 6
OUT 7
OUT 5
IHLP6767GZ, 15 µH
5 Vsec
Q5
EPC2010
Q6
EPC2010
ER23
T1
Discrete drive
gate level
and shifter
Discrete drive
gate level
and shifter
7 turns
Q7
EPC2010
5 Vsec
3.3 µF x3
Q8
EPC2010
0V
Figure 10: Simplified schematic of eGaN FET-based eighth brick 38 V – 60 V to 53 V / 700 W converter operating at 250 kHz switching.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 5
WHITE PAPER: WP006
Isolated Full Bridge Converters
parallel, within the winding window.
98%
97%
96%
95%
94%
Efficiency
with the increase in switching frequency and the relatively small eGaN FET device size, two of these converters can be constructed within the available volume constraints. The choice of transformer turns ratio (4:7) means that, at 60
VIN the secondary side winding voltage, not including switching spike, would
be about 105 V, and therefore 200 V devices were used on the secondary side
with 100 V devices on the primary side. Unlike conventional brick designs,
the magnetic components are not integrated within the main printed circuit
board (PCB), but are separate PCBs. Not only does this reduce the number of
layers required for the main PCB, but it also allows the use of conventional
surface mount inductors for the output filters. The converter was constructed
using an 8 layer, 2-ounce copper per layer, printed circuit board. The transformer windings are created by laminating two 8 layer PCBs together, in
93%
92%
91%
90%
89%
88%
0
2
4
38 V Two Phase
36 V Single Phase
48 V Two Phase
48 V Single Phase
60 V Two Phase
60 V Single Phase
6
8
Output Current (A)
10
12
14
Figure
eGaN FET-based
brick
PSE converter
efficiency
resultsresults
showing
both both
Figure
3: 11:
Prototype
eGaN FET half
based
half-brick
PSE converter
efficiency
showing
single
phase
(half
the
converter
powered
down)
and
normal
two
phase
operation.
single phase (half the converter powered down) and normal two phase operation.
PSE Converter Comparisons
The eGaN FET-based half brick PSE converter can be compared with similar 48
V to (nominal) 53 V fully regulated commercial half brick converters. As stated
previously, these commercial converters span a range of topologies and configurations as listed in table 2. To emphasize how the eGaN FET-based prototype compares to these converters, two products (Converters B and D in table
Secondary Side
FBSR
Primary Side
FB
Input Capacitors
Output
Inductor
Transformer
Output Capacitor
DSP
Controller
Bias
Supply
CTs
Output Capacitor
Primary Side
FB
Secondary Side
FBSR
eGan FET based brick (top view)
Output
Inductor
Transformer
eGan FET based brick (bottom view)
Figure 12:
5: eGaN
FET
based 48 V48toV53
FET half-brick
PSE converter
prototype
showing
bottom
views
(scale
inches)
Figure
eGaN
FET-based
toV53eGaN
V eGaN
FET half brick
PSE converter
showing
top top
andand
bottom
views
(scale
inininches).
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 6
WHITE PAPER: WP006
Isolated Full Bridge Converters
2) have been selected to highlight the overall results.
Converter D is a conventional single-stage, single-transformer converter with a similar topology to the eGaN FET-based converter, although the eGaN FET prototype has
two parallel converters. The efficiency comparison in figures 13 and 14 shows the light load efficiency advantage that is possible with lower switching frequency and possible light load optimization through careful design of the core losses and leakage inductance. By comparison, in the eGaN FET converter the core was designed only to
Converter A
Converter B
Converter C
Converter D
Converter E
eGaN FET Prototype
Output Voltage
(V) / Power (W)
Conversion
Stages
Parallel
Converters per
Stage
Datasheet
Frequency (kHz)
Device Switching
Frequency (kHz)
Output Ripple
(kHz)
53 / 400
50 / 600
53 / 424
54 / 550
54 / 550
53 / 700
2
2
1
1
1
1
1/2
2/2
1
1
1
2
300 / 300
120 / 240
270
275
140
250
150
120
135
138
140
250
300
240
270
275
280
1000
Table 2: Comparison of commercial half brick PSE converters.
minimize leakage inductance and deliberately switch at 75% higher switching
frequency. Although light load efficiency is lower, the eGaN FET prototype has
similar efficiency around 50% of full load and produces 25% more power at full
load for a similar total converter loss.
The efficiency comparison between the eGaN FET prototype and the two
stage converter is shown in figure 15. This shows the optimization process
that has gone into Converter B as the peak efficiency is achieved at the nominal input of 48 V.
The distinctions in topology can best be highlighted by comparing the 38 V
(low line) input voltage results: Since the two-stage circuit employs a boost
regulation stage, this is actually a worst-case condition (i.e. conduction loss
increased with no appreciable reduction in switching loss), while for the traditional single stage approach, low-line is the best case, as switching loss is
minimized. The power losses are shown in figure 16. The two-stage converter’s power losses at low-line reach almost 50 W, which is about double that of
the eGaN FET converter under the same conditions. For 75 V input (high-line)
losses are very respectable, only 15% higher than the eGaN FET prototype
while operating at 25% higher voltage.
97%
250 kHz eGaN FET
96%
140 kHz MOSFET
700 W
95%
550 W
Efficiency
94%
93%
92%
91%
90%
89%
88%
0
2
4
An eGaN FET-based fully regulated eighth brick converter and an eGaN FETbased half brick PoE-PSE converter are both more efficient than their MOSFETbased counterparts. The eighth brick has improved efficiency and 15% more
output power at a 33% higher switching frequency, and the half brick PoE-PSE
36 V MOSFET
48 V eGaN FET
48 V MOSFET
60 V eGaN FET
60 V MOSFET
6
8
Output Current (A)
10
12
14
MOSFET-based solution.
35
140 kHz MOSFET
30
25
250 kHz eGaN FET
20
15
10
5
Summary
38 V eGaN FET
13: Efficiency
comparison
betweenPSE
halfconverters
brick PSE showing
converters
Figure 6:Figure
Efficiency
comparison
between half-brick
an eGaN FET
based prototype
vs. Converter
D - a commercial
MOSFET
solution
showing
an eGaN FET-based
prototype
vs. Converter
D – abased
commercial
Power Loss (W)
The second commercial half brick (Converter B) used for comparison, has a twostage approach. Although the two-stage approach is different than our prototype approach, both have the output power split into two separate converters
operating in parallel. The advantages of the two-stage approach are that it allows efficiency optimization of the unregulated isolation stage since it operates
at a fixed duty cycle and voltage regardless of converter input voltage, and the
controlled input and output voltage allow the use of lower voltage rated devices with better figures of merit (FOMs). The disadvantages are additional conduction losses for two stages and increased complexity and component count.
98%
0
0
2
4
38 V eGaN FET
36 V MOSFET
48 V eGaN FET
48 V MOSFET
60 V eGaN FET
60 V MOSFET
6
8
Output Current (A)
10
12
14
Figure 14:Figure
Power
comparison
between
half brick
PSE converters
7: loss
Power
loss comparison
between
half-brick
PSE
converters
eGaN FETprototype
based prototype
vs. Converter
showingshowing
an eGaNanFET-based
vs. Converter
D. D
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 7
WHITE PAPER: WP006
Isolated Full Bridge Converters
98%
50
97%
45
250 kHz eGaN FET
96%
700 W
95%
35
600 W
30
Power Loss (W)
Efficiency
94%
120 kHz MOSFET
93%
92%
91%
90%
89%
88%
120 kHz MOSFET
40
38 V eGaN FET
36 V MOSFET
48 V eGaN FET
48 V MOSFET
60 V eGaN FET
0
2
4
6
8
Output Current (A)
10
250 kHz eGaN FET
20
15
10
5
75 V MOSFET
12
25
14
Figure
15: 8:
Efficiency
brick PSE
an
Figure
Efficiencycomparison
comparisonbetween
betweenhalf
half-brick
PSEconverters
converters showing
showing an
eGaNvs.
FETConverter
based prototype
vs. Converter
B
eGaN FET-based prototype
B - a two-stage
MOSFET-based
solution.
0
0
2
4
38 V eGaN FET
38 V MOSFET
48 V eGaN FET
48 V MOSFET
60 V eGaN FET
75 V MOSFET
6
8
Output Current (A)
10
12
14
Figure 16:Figure
Power9:loss
comparison
between
half brick
PSE converters
showing an
Power
loss comparison
between
half-brick
PSE converters
showing
eGaN FET
based prototype
vs. Converter
B
eGaN an
FET-based
prototype
vs. Converter
B.
converter is capable of 100 W more output power than the nearest commercial converter in the comparison group.
The choice of topology and component optimization is as important in brick converter design as the selection of the best power devices. Someone skilled in these arts
should be able to further improve the eGaN FET converters presented here.
References:
[1] [2] [3] [4] Ericsson BMR453 series 48 V to 12 V quarter brick converter, Ericsson website, http://www.ericsson.com/ourportfolio/products/bmr453-series-quarter-brick
Ericsson BMR454 series 48 V to 12 V eighth brick converter, Ericsson website, http://www.ericsson.com/ourportfolio//products/bmr454-series-eighth-brick-intermediate-bus-converter
Ericsson PKB4000-C series 48 V to 12 V eighth brick converter, Ericsson website, http://www.ericsson.com/ourportfolio//products/pkb-c-series-eighth-brick
EEE 802.3atTM-2009 Ethernet standard, http://standards.ieee.org/about/get/802/802.3.htm
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 |
| PAGE 8