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SCHOOL OF ELECTRICAL ENGINEERING &
TELECOMMUNICATIONS
ELEC2141 – DIGITAL CIRCUIT DESIGN
ASSIGNMENT I
DUE DATE: 17th April 2015

Your assignment solutions are to be submitted at the assignment box at the school
office.

Attach completed and signed assignment submission form as a front page to your
submission.

For each of the design question, you may use Xilinx ISE or PSPICE or any other
appropriate CAD tool to simulate and verify your design.
Question 1
An Arithmetic Logic Unit (ALU) is at the heart of all computers as well as most
digital hardware systems. It is a combinational network that performs logical and
arithmetic operations. An n-bit ALU typically has two input words A and B, each of
which denoted by A=An-1An-2…Ao and B = Bn-1Bn-2…Bo. The output word is denoted
by F = Fn Fn-1…Fo, where the high order output Fn is actually a carry-out. In addition,
there is a carry-in input Co. Besides data inputs and outputs, an ALU must have
control inputs for specifying the operations to be performed. The control inputs
include a mode selector, M, and operation selector inputs, So and S1. The mode
selector is needed to decide whether logical or arithmetic operation is to be performed
and the operation select inputs are required to determine which particular logic or
arithmetic function is to be performed. The specification of a simple ALU bit slice,
that is the behaviour of a single bit of an ALU, is given in Table 1. The operations are
broken down into three sections: logical operations, arithmetic operations where the
carry-in is 0, and arithmetic operations where the carry-in is 1.
Based on the specification, design an 8-bit ALU. Your design should begin with a 1bit slice of the ALU and then cascade them to build the desired 8-bit ALU. Note the
single bit slice will have six inputs: Ai, Bi, Ci, M, S1, and So, and two outputs: Fi and
Ci+1 (carry-out). Your design should include your choice of circuit implementation,
simulation and verification. For the purpose of this assignment, it will be suffice to
show the simulation and verification of the 1-bit slice of the ALU. Your design should
aim at achieving optimized implementation and include calculation of gate input cost.
M=0, Co=X
S1
So
0
0
0
1
1
0
1
1
M=1, Co=0
S1
So
0
0
0
1
1
0
1
1
M=1, Co=1
S1
So
0
0
0
1
1
0
1
1
Function
Logical Bitwise Operation
comment
Fi = Ai
Fi = NOT Ai
Fi = Ai XOR Bi
Fi = Ai XNOR Bi
Arithmetic Operations
F=A
F = NOT A
F=A+ B
F = (NOT A) + B
Arithmetic Operations
F=A+1
Increment
F = (NOT A) + 1
F=A+ B+1
F = (NOT A) + B + 1
B-A
Table 1: Specification for ALU
Question 2
Design a digital circuit that controls a security system. The security system consists of
an alarm (E), a floodlight (F), a daylight detector (D), a motion detector for potential
criminals (C) and a switch that sets the security mode. The switch has four settings
marked as mode 0, 1, 2 and 3.
When the switch is set to mode 0, the floodlight will be turned OFF but the alarm
should be ON if a potential criminal is detected at night time. When the switch is set
to mode 1, the floodlight should be turned ON and the alarm should be OFF. The
switch needs to be set to mode 2 if the floodlight is to be turned ON when a potential
criminal is detected at night time. When turning the floodlight ON at night time is
required, the switch is to be set to mode 3. In any mode, the floodlight and alarm
should not be ON at the same time.
The switch outputs 2-bit binary code (A, B) corresponding its mode. For example,
when the switch is set to mode 2, it outputs AB = ‘10’. Assume the floodlight and
detector signals are active high. This means floodlight is turned ON when driven by
logic “1” and the detector output is “1” when detection is asserted.
The desired digital circuit will generate a binary output which will control the
floodlight and the alarm through their respective driving circuits and will take the
daylight detector, the motion detector, and the binary outputs from the switch that sets
the security mode as inputs.
Your design should include your design procedure, choice of implementation,
simulation and verification. The gate input cost must be calculated.