1. No category

SCHEME AND SYLLABI
FOR
M. Tech. DEGREE PROGRAMME
IN
ELECTRONICS AND COMMUNICATION
ENGINEERING
(SPECIALIZATION - VLSI & EMBEDDED SYSTEM)
Curriculum & Syllabi for M. Tech. Degree Programme in
ELECTRONICS AND COMMUNICATION ENGINEERING
(SPECIALIZATION - VLSI & EMBEDDED SYSTEM)
SEMESTER - I
Hrs / Week
Sl.
No.
Course
No.
Evaluation Scheme (Marks)
Subject
Sessional
L
T
P
TA
CT
Sub
Total
ESE
Total
Credits
(C)
1
LMV 101
Analog Integrated Circuit Design
4
0
0
25
25
50
100
150
4
2
LMV 102
CMOS Digital Integrated circuits
4
0
0
25
25
50
100
150
4
3
LMV 103
Advanced Digital System Design
4
0
0
25
25
50
100
150
4
4
LMV 104
Introduction to VLSI Technology &
Design
4
0
0
25
25
50
100
150
4
5
LMV 105
Elective – I
3
0
0
25
25
50
100
150
3
6
LMV 106
Elective – II
3
0
0
25
25
50
100
150
3
7
LMV 107
Seminar – I
0
0
2
25
25
50
0
50
1
8
LMV 108
VLSI Design and Signal Processing
Lab
0
0
3
25
25
50
100
150
2
22
0
5
200
200
400
700
1100
25
Total
Elective – I (LMV 105)
Elective – II (LMV 106)
LMV 105 - 1
Wireless Communication
LMV 106 - 1
Advanced Microcontrollers
LMV 105 - 2
DSP Integrated Circuits
LMV 106 - 2
Design of Digital Signal Processing
Systems
LMV 105 - 3
CAD for VLSI
LMV 106 - 3
Communication Network
LMV 105 - 4
Testing of VLSI Circuits
LMV 106 - 4
ASIC Design
L – Lecture, T – Tutorial, P – Practical
TA – Teacher‟s Assessment (Assignments, attendance, group discussion, tutorials,
seminars, etc.)
CT – Class Test (Minimum of two tests to be conducted by the Institute)
ESE – End Semester Examination to be conducted by the University
Electives: New Electives may be added by the department according to the needs of
emerging fields of technology. The name of the elective and its syllabus should
be submitted to the University before the course is offered
1
SEMESTER - II
Hrs / Week
Sl.
No.
Course
No.
Evaluation Scheme (Marks)
Subject
Sessional
L
T
P
TA
CT
Sub
Total
ESE
Total
Credits
(C)
1
LMV 201
Principles of Real Time System
4
0
0
25
25
50
100
150
4
2
LMV 202
Introduction to Embedded System
4
0
0
25
25
50
100
150
4
3
LMV 203
Digital Image Processing
4
0
0
25
25
50
100
150
4
4
LMV 204
High Speed Digital Design
4
0
0
25
25
50
100
150
4
5
LMV 205
Elective – III
3
0
0
25
25
50
100
150
3
6
LMV 206
Elective – IV
3
0
0
25
25
50
100
150
3
7
LMV 207
Seminar – II
0
0
2
25
25
50
0
50
1
8
LMV 208
Embedded System Lab
0
0
3
25
25
50
100
150
2
22
0
5
200
200
400
700
1100
25
Total
Elective – III (LMV 205)
LMV 205 - 1
LMV 205 - 2
Real Time Embedded System and
Controllers
Analysis and Design of Analog and Mixed
VLSI Circuits
Elective – IV (LMV 206)
LMV 206 - 1
System Design using Embedded Processors
LMV 206 - 2
Artificial Neural Networks
LMV 205 - 3
DSP Algorithms and Architecture
LMV 206 - 3
Multirate Signal Processing and Filter
Banks
LMV 205 - 4
Micro Electro Mechanical System
LMV 206 - 4
Hardware/Software Co Design
L – Lecture, T – Tutorial, P – Practical
TA – Teacher‟s Assessment (Assignments, attendance, group discussion, tutorials,
seminars, etc.)
CT – Class Test (Minimum of two tests to be conducted by the Institute)
ESE – End Semester Examination to be conducted by the University
Electives: New Electives may be added by the department according to the needs of
emerging fields of technology. The name of the elective and its syllabus should
be submitted to the University before the course is offered
2
SEMESTER - III
Hrs / Week
Sl.
No.
Course
No.
Subject
Sessional
L
T
P
1
LMV 301
Industrial Training
0
0
20
2
LMV 302
Master‟s Thesis Phase - I
0
0
10
0
0
30
Total
*
Evaluation Scheme (Marks)
ESE**
Total
(Oral)
Credits
(C)
TA*
CT
Sub
Total
50
0
50
100
150
10
50
0
50
100
150
10
TA based on a Technical Report submitted together with presentation at the end of the
Industrial Training
** Evaluation of the Industrial Training will be conducted at the end of the third semester
by a panel of examiners, with at least one external examiner, constituted by the
University
SEMESTER - IV
Hrs / Week
Sl.
No.
Course
No.
Subject
LMV 401
Master‟s Thesis
2
LMV 402
Master‟s Comprehensive Viva
Credits
ESE**
(C)
(Oral
Total
&
Sub
Total Viva)
Sessional
L
1
0
Total
T
0
P
30
30
Grand Total of all Semesters
*
Evaluation Scheme (Marks)
TA*
CT
150
0
150
0
150
150
150
300
20
100
100
0
400
20
2750
80
50% of the marks to be awarded by the Project Guide and the remaining 50% to be
awarded by a panel of examiners, including the Project Guide, constituted by the
Department
** Thesis evaluation and Viva-voce will be conducted at the end of the fourth semester by a
panel of examiners, with at least one external examiner, constituted by the University
3
LMV 101
ANALOG INTEGRATED CIRCUIT DESIGN
L T P C
4 0 0 4
Module 1
MOS transistors - Advanced MOS modeling in linear, saturation and cutoff - high
frequency equivalent circuit.
Module 2
Current mirrors – active loads - output stages- cascode and Folded cascode structuresfrequency response
Module 3
Differential amplifiers - frequency response- CMOS operational amplifiers - one-stage opamps and two stage op-amps -Noise in op-amps
Module 4
Frequency response and stability of feedback amplifiers - frequency compensationNonlinearity and mismatch in MOS differential circuits.
References:
1. David A Johns & Ken Martin, „Analog Integrated Circuit Design‟ John Wiley and
Sons, 2008
2. Gray, Hurst, Lewis, and Meyer, “Analysis and Design of Analog Integrated
th
Circuits”, 5 edition by, John Wiley and Sons, 2009.
3. Behzad Razavi, „Design of Analog CMOS Integrated Circuit‟ Tata-Mc GrawHill,
2008
4. Philip Allen & Douglas Holberg, „ CMOS Analog Circuit Design‟, Oxford
University Press, 2009
5. R. Gregorian, G.C. Temes, "Analog MOS ICs for Signal Processing", Wiley 2004.
4
LMV 102
CMOS DIGITAL INTEGRATED CIRCUITS
L T P C
4 0 0 4
Module 1
MOS Transistors-Structure-electrical characteristics-first order and second order effects
scaling of MOS transistors-Spice modeling-CMOS fabrication process-Schematic, Stick
diagram- layout of simple CMOS gates.
Module 2
Parasitic associated with MOS structure layout-RC delay-interconnect delay-CMOS
inverter-static and dynamic characteristics-Design of inverters, combination circuits-Design
of sequential circuits-clocking strategies-semiconductor memories.
Module 3
Inverters and logic gates- NMOS and CMOS inverters, inverter ratio, DC and transient
characteristics, switching times, super buffers, driving large capacitance loads, CMOS logic
structures, transmission gates.
Module 4
VLSI system components circuits-Multiplexers, decoders, Priority encoders, shift registers.
Arithmetic circuits- ripple carry adders, carry look ahead adders, high-speed adders,
Multipliers.
References:
1. Sung Mo Kang and Yusuf Lebelci, “CMOS Digital integrated Circuits Analysis and
Design”, Tata McGraw- Hill , New Delhi, 2003.
2. Jan M Rabaey and Anantha Chandrakasan, “ Digital integrated Circuits- A Design
Perspective” ,Prentice Hall, Second Edition, 2002.
3. Neil H E Weste, David Harris and Ayan Banerjee,” CMOS VLSI Design- A circuit
System Perspective”, Pearson Education, 2004.
4. Muller Richards, Kamins and Theodre “Device Electronics for Integrated Circuits”
John Wiley, New York, 2003.
5
LMV 103
ADVANCED DIGITAL SYSTEM DESIGN
L T P C
4 0 0 4
Module 1
Combinational Circuits Design- Synchronous Sequential Circuits design-Fault detection and
Analysis in combinational and sequential systems-Path sensitizing method-SPOOF methodBoolean Difference Method- initial State Method
Module 2
Asynchronous Sequential Circuit Design and analysis-Flow table reduction-state
assignment-problem and transition table-static and dynamic hazards-essential hazards-mixed
operating mode asynchronous circuits.
Module 3
Study of programmable Logic Families- PLD, CPLD, FPGA, PLA. Synthesis and
implementation issues
Module 4
Verilog Description of combinational Circuits-arrays-Verilog operaters-Compilation and
simulation of Verilog codes-Modelling using Verilog-Flip Flops-registers-counterssequential machine-combinational logic circuits-Verilog codes –serial adders-binary
multipliers-binary divider.
References:
1. Richard F Tinder, “Engineering Digital Design”, Mc Graw Hill, 2003.
2. Donald D Givone , “Digital Principles and Design “, Tata Mc Graw Hill, 2004.
3. Parag K Lala, “Digital Circuit Testing and Testability” ,Academic Press, 1997.
4. Samir Palnitkar, “ Verilog HDL ”, Pearson Education, 1996.
5. K. Chan and S. Mourad,”Digital Design Using Field Programmable Gate Array”,
Prentice Hall, 1994.
6. Greweal B S, “Higher Engineering Mathematics”, Khanna Publishers, 2005
6
LMV 104
INTRODUCTION TO VLSI TECHNOLOGY &
DESIGN
L T P C
4 0 0 4
Module 1
Oxidation technologies in VLSI and ULSI -.Kinetics of Silicon dioxide growth both for
thick, thin and ultra thin films- High k and low k dielectrics for ULSI- Solid State diffusion
modeling and technology; Ion Implantation modeling, damage annealing
Module 2
Photolithography, E-beam lithography and newer lithography techniques for VLSI/ULSI.
CVD techniques for deposition of films; Etching- Evaporation and sputtering techniquesmetal interconnects; Multi-level metallization schemes. Plasma etching and RIE techniques
Module 3
Process integration -NMOS, CMOS and Bipolar process.
Module 4
VLSI Design - Introduction to ASICS, CMOS LOGIC and ASIC Library Design - Types of
ASICs – design flow- CMOS transistors CMOS design rules – combinational logic cell –
sequential logic cell- Data path logic cell – transistors and resistors – transistor parasitic
capacitance – logical effort – library cell design – library architecture
References:
1. C.Y. Chang and S.M.Sze (Ed), ULSI Technology, McGraw Hill Companies Inc,
2002, reprinted.
2. S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 2008.
3. Stephen Campbell, “The Science and Engineering of Microelectronics”, Oxford
University Press, 2001.
4. M.J.S. Smith, “Application – Specific Integrated Circuits” – Addison – Wesley
Longman Inc. 2008.
5. S.K. Ghandhi, “VLSI Fabrication Principles”, John Wiley Inc., New York, 2008.
6. James Plummer, M. Deal and P.Griffin, “Silicon VLSI Technology”, Prentice Hall
7
LMV 105 - 1
WIRELESS COMMUNICATION
L T P C
3 0 0 3
Module 1: Fading and Diversity
Wireless Channel Models- path loss and shadowing models- statistical fading modelsNarrow band and wideband Fading models- Review of performance of digital modulation
schemes over wireless channels - Diversity- Repetition coding and Time DiversityFrequency and Space Diversity- Receive Diversity- Concept of diversity branches and
signal paths- Combining methods- Selective diversity combining - Switched combiningmaximal ratio combining- Equal gain combining- performance analysis for Rayleigh fading
channels.
Module 2: Cellular Communication
Cellular Networks- Multiple Access: FDM/TDM/FDMA/TDMA- Spatial reuse- Co-channel
interference Analysis- Hand over Analysis- Erlang Capacity Analysis- Spectral efficiency
and Grade of Service- Improving capacity - Cell splitting and sectorization.
Module 3: Spread spectrum and CDMA
Motivation- Direct sequence spread spectrum- Frequency Hopping systems- Time
Hopping.- Anti-jamming- Pseudo Random (PN) sequence- Maximal length sequences- Gold
sequences- Generation of PN sequences.- Diversity in DS-SS systems- Rake ReceiverPerformance analysis. Spread Spectrum Multiple Access- CDMA Systems- Interference
Analysis for Broadcast and Multiple Access Channels- Capacity of cellular CDMA
networks- Reverse link power control- Hard and Soft hand off strategies.
Module 4: Fading Channel Capacity
Capacity of Wireless Channels- Capacity of flat and frequency selective fading channelsMultiple Input Multiple output (MIMO) systems- Narrow band multiple antenna system
model- Parallel Decomposition of MIMO Channels- Capacity of MIMO Channels. Cellular
Wireless Communication Standards
Second generation cellular systems: GSM specifications and Air Interface - specifications,
IS 95 CDMA- 3G systems: UMTS & CDMA 2000 standards and specifications
8
References:
1. Andrea Goldsmith, “Wireless Communications”, Cambridge University Press, 2005.
2. Simon Haykin & Michael Moher, “Modern Wireless Communications”, Person
Education, 2007.
3. T. S. Rappaport, “Wireless Communication, Principles & Practice”, Dorling
Kindersley (India) Pvt. Ltd., 2009.
4. G. L. Stuber, “Principles of Mobile Communications”, 2nd Edition, Springer Verlag.
2007.
5. Kamilo Feher, 'Wireless Digital Communication', Dorling Kindersley (India) Pvt.
Ltd., 2006.
6. R. L. Peterson, R. E. Ziemer & David E. Borth, “Introduction to Spread Spectrum
Communication”, Prentice Hall, 1995.
7. A. J. Viterbi, “CDMA- Principles of Spread Spectrum”, Prentice Hall, 1995.
9
LMV 105 - 2
DSP INTEGRATED CIRCUITS
L T P C
3 0 0 3
Module 1: Multi rate systems:
Decimation and interpolation, polyphase structures, Filters for decimation and interpolation,
multistage decimators and interpolators, filter banks, uniform DFT filter bank, two channel
QMF filter bank, PRQMF.
Module 2: Adaptive signal processing:
Adaptive systems, open loop and closed loop adaptation, Adaptive linear combiner,
Adaptive algorithms and structures, LMS algorithm, ideal LMS/Newton algorithm,
Sequential regression algorithm, Random search algorithms and applications
Module 3: Two dimensional signal processing
2 D signals and systems, two dimensionalsampling, difference equations, convolution, two
dimensional DFT, two dimensional DCT, Two dimensional Z Transforms, stability
conditions
Module 4: General Purpose DSP Architecture
TMS 320 C 54 X fixed point processor, TMS 320 C 6X processor, ADSP 21xxx SHARC
processor
References:
1. Tamal Bose, “Digital signal and Image processing”, Wiley, 2004.
2. P P Vaidyanathan, “Multirate Systems and Filter Banks”, Prentice Hall. V, 2008.
3. Bernard Widrow and S D Streams, “Adaptive Signal Processing”, Prentice Hall,
2007.
4. D E Dudgeson and R M Mersereau, “Multidimensional Digital Signal Processing”,
Prentice Hall, 1984
5. Texas Instruments Documentation, Analog Devices Documentation
10
LMV 105 - 3
L T P C
3 0 0 3
CAD FOR VLSI
Module 1
Logic Synthesis and Technology Mapping-Introduction, Y Chart-physical design top-down
flow, comparison of FPGA/ASIC design styles. review of graph theory and data structurescomputer aided sythesis and optimization, circuit models synthesis-logic synthesis,
architectureral synthesisis and optimization. Graph, graph optimization problems and
algorithms.
Introduction
to
combinational
logic
synthesis-binary
decision
diagrams:principles implementation and constructions, manipulation, variable ordering,
applications to verification and optimizations. Two level and multi level optimization,
sequential logic optimization. Technology mapping. Cell library binding,.
Module 2
Physical design automation- floor planning. Power planning. Clock tree synthesis.
Placement. Pin assignment.routing:global,detail,over the cell routing. Clock and power
routing.
Module 3
Global compaction and layout compaction-power formulation, 11/2 dimentional compaction,
two dimentional compactional,hierarchical compaction, F algorithm for constrain
compaction Longest path algorithm for for DAGs ,longest path in graphs with cycles,
Bellman-Ford Algorithm, Horizontal and vertical virtual grid copaction, constrain graph
based compaction.
Module 4
Timing analysis prelayout and post layout, static and dynamic timing analysis for single and
multiple
path
data
flows.copensational
techniques.
Critical
path
delays.
Back
annotation,circuit extraction and DRC, BIST.
References:
1. Giovanni De Micheli “Synthesis and Optimization of Digital Circuits”, 1 st Edition
Mc Graw Hill, 1994.
11
2. Naveed Sherwani “Algorithms for VLSI Physical Design Automation”, 3rd edition,
Springer International edition, 2005.
3. H Yosuff and S M Sait “VLSI Physical Design Automation Theory and Practice”,
Mc Graw Hill Pub. , 1995.
4. Michael John Sebastian Smith, “Application Specific Integrated Circuits”, Pearson
Education Asia, 2009.
5. Sabih. H. Gerez, “Algorithm for VLSI Design Automation Theory and Practice”,
John Willey & Sons Ltd., 2004
12
LMV 105 - 4
TESTING OF VLSI CIRCUITS
L T P C
3 0 0 3
Module 1
Introduction-VLSI testing process and Test Equipment-Test Economics and Product
Quality- why fault modeling-Fault Modeling-Logic and Fault Simulation-glossary of Faultssingle stuck-at-faults-functional equivalence-bridging faults.
Module 2
Logic simulation-modeling single states-algorithm for true value simulation-serial and
parallel fault simulation-Testability Measures-Combinational Circuit Test GenerationSequential Circuit Test Generation.
Module 3
Introduction to SCAN-Binary Decision Diagram-combinational ATPG Algebra-redundancy
–D algorithm-PODEM algorithm-FAN algorithm-circuit test approach-observabilitycontrollability.
Module 4
Memory Test-Analog and Mixed signal Test-delay test-IDDQ Test. DFT FundamentalsATPQ Fundamental-Scan Architecture and Technique. System Test- Embedded Core TestFuture Testing.
References:
1. Viswani D Agarwal and Michael L Bushnell, “Essentials of Electronic Testing of
Digital Memory and Mixed Signal VLSI Circuits”, Springer, 2000.
2. Alfred L Cronch, “Design for Test for Digital IC‟s and Embedded Core system”,
Prentice Hall, 1999.
3. Niraj Jha and Sanjeep K Gupta, “Testing of Digital Systems”, Cambridge University
Press, 2003.
4. M. Abramovici, M A Breuer and A D Friedman, “Digital systems Testing and
Testable Design”, IEEE Press, 1994.
13
LMV 106 - 1
ADVANCED MICROCONTORLLERS
L T P C
3 0 0 3
Module 1
Low pin count controllers – Atmel AVR family – ATTiny15L controller - architecture – pin
descriptions – features – addressing modes – I/O space – reset and interrupt handling – reset
sources - Tunable internal oscillator.
Module 2
Timers – Watch dog timer – EEPROM – preventing data corruption – Analog comparator –
A/D converter – conversion timing – ADC noise reduction – PortB – alternate functions –
memory programming – fuse bits – high voltage serial programming – algorithm.
Module 3
National semiconductor COP8 family - COP8CBR9 processor – features – electrical
characteristics – pin descriptions – memory organization –EEPROM - security – brownout
reset – in system programming – boot ROM. Idle timer – Timer1, Timer2, Timer3 operating modes – PWM mode – event capture mode
Module 4
Power saving modes – Dual clock operation – Multi input wake up – USART – framing
formats – baud rate generation – A/D conversion – operating modes – prescaler – Interrupts
– interrupt vector table – Watch dog – service window – Micro-wire interface – waveforms.
Microchip PIC16 family – PIC16F873 processor – features – architecture – memory
organization - register file map – I/O ports – PORTA - PORTB – PORTC – Data EEPROM
and flash program memory – Asynchronous serial port – SPI mode – I2C mode.
References:
1.
2.
3.
4.
5.
6.
John B Peatman , ”Design with PIC micro-controllers”, Pearson Education, 2006.
DS101374: National Semiconductor reference manual.
National semiconductor web site – www.national.com
1187D: Atmel semiconductor reference manual.
Atmel semiconductor web site – www.atmel.com
DS30292B: Microchip reference manual. Microchip semiconductor web site –
www.microchip.com
14
LMV 106 - 2
DESIGN OF DIGITAL SIGNAL PROCESSING
SYSTEM
L T P C
3 0 0 3
Module 1
Introduction to a popular DSP from Texas Instruments TMS320C6XXX– CPU
Architecture (VLIW) - CPU Data Paths and Control - Timers - Internal Data/ Program
Memory - External
Memory Interface ,Difference between fixed and floating point
processors
Module 2
Programming - Instruction Set and Addressing Modes - Code Composer Studio - Code
Generation Tools - Code Composer Studio Debug Tools – Simulator.
Module 3
Digital Signal Processing Applications : Filter Design - FIR & IIR Digital Filter Design filter Design programs using MATLAB - Fourier Transform: DFT, FFT programs using
MATLAB - Real Time Implementation : Implementation of Real Time Digital filters using
DSP - Implementation of FFT applications using DSP - DTMF Tone Generation and
Detection
Module 4
Current Trends in Digital Signal Processors / DSP Controllers - Architecture - DSP
Applications.
References:
1. Naim Dahnoun, Digital Signal Processing Implementation Using the TMS320C6000
DSP Platform, 1st Edition, 2000.
2. T.J. Terrel and Lik-Kwan Shark, “Digital Signal Processing - A Student Guide”, 1st
Edition, MACMILLAN PRESS, Ltd, 2000.
3. David J Defatta J, Lucas Joseph G & Hodkiss William S, “Digital Signal Processing:
A System Design Approach”, 1st Edition; John Wiley, 2009
15
4. John G Proakis, Dimitris G Manolakis, “Introduction to Digital Signal Processing”,
4th Edition, 2006.
5. Oppenheim A.V and Schafer R.W, “Digital Signal Processing”, 1st Edition; PH,
1975
16
LMV 106 - 3
COMMUNICATION NETWORK
L T P C
3 0 0 3
Module 1
Architectural concepts in ISO‟s OSI layered model, layering in the Internet. TCP/IP
protocol stack. Transport layer - TCP and UDP. Network layer - IP, routing,
internetworking.
Module 2
Data link layer - ARQ schemes, multiple access, LANs.
Quality of Service issues in networks- Integrated service architecture- Queuing DisciplinesWeighted Fair Queuing- Random Early Detection- Differentiated Services- Protocols for
QOS support- Resource reservation-RSVP- Multi protocol Label switching- Real Time
transport protocol.
Module 3
Markov chain- Discrete time and continuous time Markov chains- Poisson process- Queuing
models for Data gram networks- Little‟s theorem- M/M/1 queuing systems- M/M/m/m
queuing models- M/G/1 queue- Mean value analysis- Time reversibility- Closed queuing
networks- Jackson‟s Networks.
Module 4
Multiplexing: Network performance and source characterization; Stream sessions in packet
networks - deterministic analysis, stochastic analysis, circuit multiplexed networks; Elastic
transfers in packet networks - adaptive bandwidth sharing.
References:
1. James. F. Kurose and Keith.W. Ross, “Computer Networks, A top-down approach
featuring the Internet”, Addison Wesley, 2001.
2. D. Bertsekas and R. Gallager, “Data Networks”, PHI, 2000.
17
3. S. Keshav, “An Engineering Approach to Computer Networking”, Addison Wesley,
2008.
4. Peterson L.L. & Davie B.S., “Computer Networks: A System Approach”, Morgan
Kaufman Publishers, 2007.
5. Anurag Kumar, D. Manjunath, and Joy Kuri, “Communication Networking: An
Analytical Approach”, Morgan Kaufman Publ., 2004.
18
LMV 106 – 4
ASIC DESIGN
L T P C
3 0 0 3
Module 1
Programmable ASICS, Programmable ASIC Logic cells and Programmable ASIC I/o cells Anti fuse- static RAM – EPROM and EEPROM technology, PREP benchmarks- Actel
ACT-Xilinx LCA- Altera FLEX- Altera MAX DC & AC inputs and outputs – clock &
Power inputs – Xilinx I/O blocks.
Module 2
Programmable ASIC Interconnect, Programmable ASIC design software and Low level
design entry -Actel ACT-Xilinx LCA – Xilinx EPLD – Altera MAX 5000 and 7000 – Altera
MAX 9000 – Altera FLEX- Design systems – Logic synthesis – half gate ASIC schematic
entry – low level design language – PLA tools – ENDIF-CFI design representation.
Module 3
Logic Synthesis, Simulation and Testing - Verilog and logic synthesis – VHDL and logic
synthesis – types of simulation – boundary scan test- fault simulation automatic test pattern
generation.
Module 4
ASIC construction, Floor Planning, Placement and routing -System partition – FPGA
partitioning – partitioning methods – floor planning – placement – physical design flowglobal routing – detailed routing – special routing – circuit extraction – DRC.
References:
1. M.J.S. Smith, “Application – specific integrated circuits”–Addison–Wesley
Longman Inc., 1997.
2. Andrew Brown, - “VLSI circuits and systems in silicon”, Mc Graw Hill, 1991.
3. S.D. Brown, R.J. Francis, J.Rox, Z.G. Uranesic, “Field Programmable gate arrays”,
Khuever academic publisher, 1992.
4. S.Y.Kung, H.J. Whilo House, T.Kailath, “VLSI and Modern Signal Processing”,
Prentice Hall, 1984.
19
LMV 107
SEMINAR – I
L T P C
0 0 2 1
Each student shall present a seminar on any topic of interest related to the core / elective
courses offered in the first semester of the M. Tech. programme. He / she shall select the
topic based on the references from international journals of repute, preferably IEEE
journals. They should get the paper approved by the Programme Co-ordinator / Faculty
member in charge of the seminar and shall present it in the class. Every student shall
participate in the seminar. The students should undertake a detailed study on the topic and
submit a report at the end of the semester. Marks will be awarded based on the topic,
presentation, participation in the seminar and the report submitted.
LMV 108
VLSI DESIGN AND SIGNAL PROCESSING LAB
L T P C
0 0 3 2
System simulation experiments based on the courses LMV 102, LMV 103 and the elective
courses opted by the student in the first semester.
20
LMV 201
PRINCIPLES OF REAL TIME SYSTEM
L T P C
4 0 0 4
Module 1: Tasks and Scheduling
Introduction - Issues in Real Time Computing, Structure of a Real Time System, Task
classes, Performance Measures for Real Time Systems, Estimating Program Run Times.
Task Assignment and Scheduling - Classical uniprocessor scheduling algorithms,
Uniprocessor scheduling of IRIS tasks, Task assignment, Mode changes, and Fault Tolerant
Scheduling.
Module 2: Programming Languages and Data bases
Programming Languages and Tools - Desired language characteristics, Data typing, Control
structures, Facilitating Hierarchical Decomposition, Packages, Run - time (Exception) Error
handling, Overloading and Generics, Multitasking, Low level programming, Task
Scheduling, Timing Specifications, Programming Environments, Run - time support.
Module 3: Real time Databases
Basic Definition, Real time Vs General Purpose Databases, Main Memory Databases,
Transaction priorities, Transaction Aborts, Concurrency control issues, Disk Scheduling
Algorithms, Two-phase Approach to improve Predictability, Maintaining Serialization
Consistency, Databases for Hard Real Time Systems.
Module 4 :
a. Communication
Real-Time Communication - Communications media, Network Topologies Protocols, Fault
Tolerant Routing. Fault Tolerance Techniques - Fault Types, Fault Detection. Fault Error
containment Redundancy, Data Diversity, Reversal Checks, Integrated Failure handling.
b. Clock Synchronization
Clock Synchronization - Clock, A Non fault-Tolerant Synchronization Algorithm, Impact of
faults, Fault Tolerant Synchronization in Hardware, Fault Tolerant Synchronization in
software.
21
References:
1. C.M. Krishna, Kang G. Shin, "Real Time Systems", McGraw - Hill International
Editions, 1997.
2. Alam Javeed, “Real Time Systems and Software”, John Wiley & Sons Inc (sea) Pte Ltd,
2003.
3. Rajib Mall“Real time Systems: Theory and Practice”, Prentice hall, 2009.
22
LMV 202
INTRODUCTION TO EMBEDDED SYSTEM
L T P C
4 0 0 4
Module 1
a. Embedded Architecture
Embedded Computers – Characteristics of Embedded Computing Applications – Challenges
in Embedded Computing system design – Embedded System design process –Formalism for
System Design
b. Networks
Hardware and Software Architectures – Networks for Embedded Systems – I2C – CAN
Bus– Zig Bee - Blue tooth – SPI - USB - Ethernet – Myrinet – Internet – Network–Based
design – Communication Analysis – System Performance Analysis
Module 2: Program modeling concepts in single and multiprocessor systems softwaredevelopment process
Modeling process for software analysis before software implementation- Programming
models for event controlled or response time constrained programs - Modeling of
multiprocessor systems
Module 3: Inter-process Communication and Synchronisation of Processes ,Tasks
and Threads
Multiple Processes in an Application - Data sharing by multiple tasks and routines- Inter
Process Communication
Module 4: Real Time Operating Systems
Operating System Services , I/O Subsystems - Network Operating Systems - Real Time and
Embedded System Operating systems. Interrupt routines in RTOS Environments - RTOS
Task Scheduling models , Interrupt Latency and response Times – Performance metric in
scheduling models
23
References:
1. Wayne Wolf “Computers as Components: Principles of Embedded Computing
System Design”, Morgan Kaufman Publishers, 2008.
2. Raj Kamal “Embedded Systems – Architecture, Programming and Design”, Tata
McGraw Hill, 2nd Edition, 2008
3. Jane.W.S., “ Liu Real-Time systems”, Pearson Education , 2000.
4. C. M. Krishna and K. G. Shin, “Real Time Systems”, McGraw Hill, 1997.
5. Frank Vahid and Tony Givargi, “Embedded System Design: A Unified
Hardware/Software Introduction”, John Wiley & Sons, 2006
24
LMV 203
DIGITAL IMAGE PROCESSING
L T P C
4 0 0 4
Module 1
Image representation: Gray scale and colour Images, image sampling and quantization. Two
dimensional orthogonal transforms: DFT, WHT, Haar transform, KLT, DCT. Image
enhancement - filters in spatial and frequency domains, histogram-based processing,
homomorphic filtering. Edge detection - non parametric and model based approaches, LOG
filters, localisation problem.
Module 2
Image Restoration: Degradation Models, PSF, circulant and block - circulant matrices,
deconvolution, restoration using inverse filtering, Wiener filtering and maximum entropybased methods.Image Segmentation: Pixel classification, Bi-level thresholding, Multi-level
thresholding, P-tile method, Adaptive thresholding, Spectral & spatial classification, Edge
detection, Hough transform, Region growing.
Module 3
Fundamental concepts of image compression - Compression models - Information theoretic
perspective - Fundamental coding theorem - Lossless Compression: Huffman CodingArithmetic coding - Bit plane coding - Run length coding - Lossy compression: Transform
coding – Image compression standards.
Module 4
Fundamentals of Wavelet Transforms, DWT in one and two Dimensions, Mallat structure
for implementation in 2 Dimensions, Applications of DWT to Image Compression, SPIHT,
JPEG 2000
References:
1. R. C. Gonzalez, R. E. Woods,” Digital Image Processing”, Pearson Education. II
Ed., 2002.
2. A. K. Jain, “Fundamentals of Digital Image Processing”, Prentice Hall of India,
1989.
25
3. R. C. Gonzalez, R. E. Woods,” Digital Image Processing”, Pearson Education. II
Ed., 2002.
4. W. K. Pratt, “Digital Iimage Processing”, Prentice Hall, 1989.
5. A. Rosenfold and A. C. Kak, “Digital Image Processing”, Vols. 1 and 2, Prentice
Hall, 1986.
5. R. Jain, R. Kasturi and B.G. Schunck, Machine Vision, McGraw-Hill International
Edition, 1995.
6. A. M. Tekalp, “Digital Video Processing”, Prentice-Hall, 1995.
26
LMV 204
HIGH SPEED DIGITAL DESIGN
L T P C
4 0 0 4
Module 1: Introduction to high-speed digital design
Frequency, time and distance - Capacitance and inductance effects - High seed properties of
logic gates - Speed and power -Modelling of wires -Geometry and electrical properties of
wires - Electrical models of wires - transmission lines - lossless LC transmission lines lossy LRC transmission lines - special transmission lines
Module 2: Power distribution and noise
Power supply network - local power regulation - IR drops - area bonding - onchip bypass
capacitors - symbiotic bypass capacitors - power supply isolation - Noise sources in digital
system - power supply noise - cross talk - intersymbol interference
Module 3: Signalling convention and circuits
Signalling modes for transmission lines -signalling over lumped transmission media signalling over RC interconnect - driving lossy LC lines - simultaneous bi-directional
signalling - terminations - transmitter and receiver circuits
Module 4: Timing convention and synchronisation
Timing fundamentals - timing properties of clocked storage elements - signals and events open loop timing level sensitive clocking - pipeline timing - closed loop timing - clock
distribution - syncronisation failure and metastability - PLL and DLL based clock aligners
References:
1. William S. Dally & John W. Poulton; Digital Systems Engineering, Cambridge
University Press, 1998
2. Howard Johnson & Martin Graham; High Speed Digital Design: A Handbook of Black
Magic, Prentice Hall PTR, 1993
3. Masakazu Shoji; High Speed Digital Circuits, Addison Wesley Publishing Company,
1996
4. Jan M, Rabaey, Digital Integrated Circuits: A Design perspective, Second Edition, 2006
27
LMV 205 - 1
REAL TIME EMBEDDED SYSTEM AND
CONTROLLERS
L T P C
3 0 0 3
Module 1
Real Time Operating Systems: Introduction to OS-Multitasking OS-Scheduler AlgorithmsPriority inversion- Tasks- Threads and processes- Exceptions-Memory model-Memory
management address translation- Commercial operating systems-basic design using RTOS
Module 2
An Introduction to Processor Design-The ARM Architecture-ARM Assembly Language
Programming-ARM Organization and Implementation-The ARM Instuction Set –
Architectural Support for High –Level Languages-The Instuction Set –Architectural Support
for System Development-ARM Processor Cores –Memory Hierarchy-Architectural Support
for Operating System-ARM CPU Cores-Embedded ARM Applications
Module 3
Embedded
microcomputer
Systems:Motorola
MC68H11
Family
Architecture
Registers,Addressing modes.Interfacing methods parallel I/O interface,Parallel Port
interface, Memory Interfacing,High speed I/O interfacing, Interrupts-interrupt service
routine-features of inteerupts-Interrupt
vector and Priority ,timing generation and
measurements, Serial I/O devices RS485,Analog Interfacing,Applications
Module 4
Introduction, System requirements,Real Time Systems,Model Taxonomy,Specification
Languages,Embedded Processors,Embedded comuting platform,Real time interfacing and
exception handling,system performance,IP and platform based SoC designs, BehaviorArchitecture co-design, Real time Scheduling,Hardware accelerators(Hardware/Software
co-design),Power issues in Embedded systems..
References:
1. Andrew N Sloss, Dominic Symes, Chris Wright “ARM System Developers GuideDesigning and Optimizing System software”, Morgan Kaufmann Publishers, 2004.
2. Steave Furber, “ARM System on Chip Architecture”, Addison Wesley, 2000.
3. Vx Works Programmers Guide.
28
LMV 205 - 2
ANALYSIS AND DESIGN OF ANALOG AND
MIXED VLSI CIRCUITS
L T P C
3 0 0 3
Module 1
Depletion region of a PN junction-Large signal model of bipolar transistors-small signal
model of biplolar transistor-short channel effects in MOS transistors-weak inversion in
MOS transistors-substrate current flow in MOS transistor
Module 2
Analysis of difference amplifiers with active load using BJT and FET- Supply and
Temperature independent biasing techniques-voltage references. Output Stages-Emitter
follower-source follower and push pull output stages.
Module 3
Configuration for Linear IC Current sources-current mirrors- designs-difference amplifiers
with active load- biasing techniques-voltage reference-Operational amplifiers-CMOS
Opamp circuits-performance measures-Design of MOS Operational Amplifier-CMOS
voltage reference-MOS power amplifier and analog switches-Analog multiplier and PLLVCO-Closed loop analysis of PLL
Module 4
MOS switched Capacitor filters-Design-switched capacitor filter-CMOS switched capacitor
filters-MOS active RC filters. Mixed signal Design: A/D and D/A converters, Delta sigma
modulators
References:
1. Phillip E Allen and Douglas R Holberg “CMOS Analog Circuit Design”, Oxford
University Press, USA, 2002.
2. Behzad Razavi, “Analysis and Design of CMOS integrated Circuits”, Tata Mc Graw
Hill, 2008.
3. Gray, Meyer, Lewis Hurst “Analysis and Design of Analog IC”, Wiley International
4th Edition, 2009.
4. Nandita Dasgupat, Amitava Dasgupta “Semiconductor Devices: Modelling and
Technology”, Prentice Hall of India, 2007
29
LMV 205 - 3
DSP ALGORITHMS AND ARCHITECTURE
L T P C
3 0 0 3
Module 1
DSP array processor architectures, fast convolution- Cook Toom Algorithm, Winograd
algorithm, Iterated convolution, cyclic convolution, algorithmic strength reduction in filters
and transforms, pipelined and parallel recursive and adaptive filters.
Module 2
Scaling and round off noise, digital lattice filter structures, bit level arithmetic architectures,
parallel multipliers, interleaved floor plane and bit plane based digital filters, bit serial
multipliers, bit serial filter design and implementations
Module 3
Pipelining and parallel processing- pipelining of FIR digital filters, parallel processing,
pipelining and parallel processing for low power, retiming, unfolding and folding
transformations, register minimization techniques, register minimization in folded
architectures
Module 4
Synchronous wave and asynchronous pipelines, synchronous pipelining and clocking styles
clock skew and clock distribution in a bit level pipelined VLSI design, wave pipelining and
asynchronous pipelining
References:
1. Keshab K. Parhi, VLSI Signal Processing Systems, Design and Implementation.
John Wiley & Sons, 1999.
2. Uwe Meyer-Baese, “Digital Signal Processing with Field Programmable Gate
Array”,Springer- Verlag, 2001.
3. Pirsch, “Architectures for Digital Signal Processing”, John Wiley and Sons, 1998.
4. Lars Wanhammar, “DSP Integrated Circuits”, Academic Press, 1999.
30
LMV 205 - 4
MICRO ELECTRO MECHANICAL SYSTEM
L T P C
3 0 0 3
Module 1
History of MicroElectroMechanical Systems (MEMS), market for MEMS, basics of
microtechnology, lithography and etching techniques, principles of bulk and surface
micromachining: subtractive processes, additive processes (evaporation, sputtering,epitaxial
growth).
Module 2
Fundamental devices and processes, Multi User MEMS Process (MUMPs), SUMMiT:
design rules; applications; micro hinges and deployment actuators, CMOS MEMS,
cleanroom lab techniques, MicroOptoElectroMechanical Systems (MOEMS), bioMEMS
and biomaterials, piezoresistivity; scanning probe microscopy, scaling laws, applications.
Module 3
Lumped element modeling and design, Electrostatic Actuators , Electromagnetic
Actuators, Linear and nonlinear system dynamics, resonant systems, Elasticity (stress,strain,
material properties), Mechanical structure basics (bending of beams, torsion,natural
frequency), Optical system design basics (Gaussian beam optics, matrix optics, resolution)
Module 4
Application case studies: MEMS Scanners and Retinal Scanning Displays (RSD), Grating
Light Valve (GLV), Digital Micromirror Devices (DMD), Optical switching,Capacitive
Micromachined Ultrasonic Transducers (CMUT)
References:
1. Gregory T A, Kovacs Micromachined Transducers Sourcebook, WCB
McGraw-Hill, 1998.
2. Nadim Maluf, An introduction to Microelectromechanical system design, Artech
House, 2000.
31
3. Victor M. Bright, Editor, Selected papers on Optical MEMS, SPIE Milestone
Series, Volume MS 153, SPIE Press, 1999.
4. Mohamed Gad-el-Hak, Editor, The MEMS Handbook, CRC Press, Baco Raton,
2002.
5. Marc Madou, Fundamentals of Microfabrication, CRC Press, New York, 2002.
6. Gregory T. A. Kovacs, Micromachined Transducers Sourcebook, WCB /
McGraw-Hill, 1998.
7. W. Trimmer, Editor, Micromechanics and MEMS: Classic and Seminal Papers to
1990, IEEE Press, 1997.
32
LMV 206 - 1
SYSTEM DESIGN USING EMBEDDED
PROCESSORS
L T P C
3 0 0 3
Module1: Embedded Hardware, Software and Peripherals
Custom single purpose processors: Hardware - Combination Sequence - Processor design RT level design - optimizing software: Basic Architecture - Operation - Programmers view Development Environment - ASIP - Processor Design - Peripherals - Timers, counters and
watch dog timers - UART - Pulse width modulator - LCD controllers - Key pad controllers Stepper motor controllers - A/D converters - Real time clock.
Module 2: Memory and Interfacing
Memory: Memory write ability and storage performance - Memory types - composing
memory - Advance RAM interfacing communication basic - Microprocessor interfacing I/O
addressing - Interrupts - Direct memory access - Arbitration multilevel bus architecture Serial protocol - Parallel protocols - Wireless protocols - Digital camera example.
Module 3: Embedded Processor and Computing Platform
ARM processor–ARM Bus– designing with microprocessor development and debugging
Module 4: Process models and Hardware Software Co-design
Modes of operation - Finite state machines - Models - HCFSL and state charts language state machine models - Concurrent process model - Concurrent process - Communication
among process -Synchronization among process - Implementation - Data Flow model.
Design technology; Automation synthesis - Hardware software co-simulation - IP cores Design Process Model.
References:
1. David. E.Simon, "An Embedded Software Primer", Pearson Education, 2001
2. Frank Vahid and Tony Givargis, "Embedded System Design", John Wiley & sons, 2006
3. Steve Heath, "Embedded System Design", Elsevier, Second Edition, 2007
4. ARM, AMBA Bus Specification.
33
LMV 206 - 2
ARTIFICIAL NEURAL NETWORKS
L T P C
3 0 0 3
Module 1
Fundamentals of ANN , Biological prototype Neural Network Concepts, learning rulesHebbian learning rule - Delta rule, Kohonen learning law, perceptron learning, problem with
the perceptron training algorithm. The back propagation Neural network: Architecture of the
back propagation Network Back propagation learning algorithm, Back propagation error
surfaces, structure growing algorithms, fast variants of Back propagation learning
Module 2
Recurrent neural networks: preliminaries- states and state dynamics, Lyupanov stability,
Cohen Grossberg Theorem, associative learning, Hopfield neural networks, error
performance of Hopfield Neural Networks, applications of Hopfield Neural networks,
simulated annealing, Boltzmann machines, learning law in Boltzmann machines,BAMs.
Module 3
Support Vector machines and Radial Basis function networks-learning from examples and
generalization, Support Vector Machines, Regularization theory route to RBF NN,
Generalized RBFNN, learning in RBFNN, image classification, other models for valid
generalization.
Module 4
ART NETWORKS: noise saturation dilemma, building blocks of adaptive resonance,ART1
architecture. Self Organizing Maps: Self Organization, Maximal Eigen vector filtering,
Extracting principal components, generalized learning laws, competitive learning, vector
quantization, Mexican hat networks, Self Organizing feature maps, applications. Neural
Network Hardware: motivation and issues, analog building blocks, digital techniques.
References:
1. Haykin Simon “ Neural Networks: A Comprehensive Foundation,2nd Ed.”, Prenticehall Of India Pvt Ltd,2007.
2. Satish Kumar, “Neural Networks: A Class room approach”, TMH, 2004.
34
3. T N Shankar,”Neural Networks”, Usp, 2008.
4. Jacek M. Zurada, “Introduction to Artificial Neural Systems”, Jaico Book House,
2006.
35
LMV 206 - 3
MULTIRATE SIGNAL PROCESSING AND FILTER
BANKS
L T P C
3 0 0 3
Module 1: Fundamentals of Multi-rate Systems
Basic multi-rate operations and their spectral representation. Linear Periodically Time
varying systems, interconnection of building blocks, Fractional Sampling rate alteration
poly-phase representation, multistage implementation, applications of multi-rate systems,
special filters and filter banks.
Module 2: Maximally decimated filter banks
Errors created in the QMF bank, aliasfree QMF system, power symmetric QMF banks, Mchannel filter banks, poly-phase representation, perfect reconstruction systems, alias-free
filter banks, tree structured filter banks, trans-multiplexers.
Module 3: Para-unitary Perfect Reconstruction Filter Banks
Lossless transfer matrices, filter bank properties induced by paraunitariness, two channel
Para-unitary lattices, M-channel FIR Para-unitary QMF banks, transform coding.
Module 4
a. Linear Phase Perfect Reconstruction QMF Banks
Necessary conditions, lattice structures for linear phase FIR PR QMF banks, formal
synthesis of linear phase FIR PR QMF lattice.
b. Cosine Modulated Filter Banks
Pseudo-QMF bank and its design, efficient poly-phase structures, properties of cosine
matrices, cosine modulated perfect reconstruction systems.
References:
1. P.P. Vaidyanathan, “Multirate Systems and Filter Banks,"Pearson Education (Asia) Pte.
Ltd, 2008.
2.
Gilbert Strang and Truong Nguyen, "Wavelets and Filter Banks,"WellesleyCambridge Press, 1997.
3.
N. J. Fliege, "Multirate Digital Signal Processing,” John Wiley & Sons, USA, 2000.
36
LMV 206 - 4
L T P C
3 0 0 3
HARDWARE/SOFTWARE CO DESIGN
Module 1
Specification of embedded systems-Why Co-design? –Comparison of co-design
approaches-MoCs: State oriented, Activity oriented, Structure oriented, Data oriented and
Heterogeneous- Software CFSMs-Processor Characterization.
Module 2
HW/SW Partitioning Methodologies-principle of hardware/software mapping-Real time
scheduling-Design specification and constraints on embedded systems- trade offs –
Partitioning
granularity-Kernigan-Lin
Algorithm-
Extended
Partitioning-
Binary
Partitioning: GCLP algorithm.
Module 3
Co-synthesis & Estimation –Software synthesis –Hardware Synthesis –Interface SynthesisCo-synthesis Approaches: Vulcan, Cosyma, Cosmos, Polis and COOL-estimation:
Hardware area, execution timing and power: Software memory and execution timing.
Module 4
Co simulation and Co-verification- principles of co-simulation-abstract level:detailed levelco-simulation as partition support-cosimulation using Ptolemy approach.
References:
1. Felice Balarin, Massimiliano Chiodo Paolo Giusto, Harry Hsieh, Attila Jurecska,
Luciano
Lavagno, Claudio Passerone, Alberto Sangiovanni- Vincentelli, Ellen
Sentovich, Kei Suzuki, Bassamssam Tavvara, “Hardware-software co-design of
embedded system: POLIS Approach”, Springer, 2004.
2. Raf Niemann, “Hardware/ Software Co-design for Data Flow Dominated Embedded
Systems”, Spring, 1998.
3. Peter Marwedel, “Embedded System Design”, Springer, 2009.
4. Russlell John Rickford, Bernd kleinjohann, “Design and Analysis of Distributed
Embedded Systems”, Springer, 2002.
37
LMV 207
SEMINAR – II
L T P C
0 0 2 1
Each student shall present a seminar on any topic of interest related to the core / elective
courses offered in the second semester of the M. Tech. programme. He / she shall select the
topic based on the references from international journals of repute, preferably IEEE
journals. They should get the paper approved by the Programme Co-ordinator / Faculty
member in charge of the seminar and shall present it in the class. Every student shall
participate in the seminar. The students should undertake a detailed study on the topic and
submit a report at the end of the semester. Marks will be awarded based on the topic,
presentation, participation in the seminar and the report submitted.
LMV 208
EMBEDDED SYSTEM LAB
L T P C
0 0 3 2
System simulation experiments based on the courses LMV 201, LMV 202 and the elective
courses opted by the student in the second semester.
38
LMV 301
INDUSTRIAL TRAINING
L T P C
0 0 20 10
The student shall undergo an industrial training of 12 weeks duration in an industry /
company approved by the institution and under the guidance of a staff member in the
concerned field. At the end of the training, he / she have to submit a report on the work
being carried out.
LMV 302
MASTER’S THESIS PHASE - I
L T P C
0 0 10 0
The thesis (Phase - I) shall consist of research work done by the candidate or a
comprehensive and critical review of any recent development in the subject or a detailed
report of project work consisting of experimentation / numerical work, design and or
development work that the candidate has executed.
In Phase - I of the thesis, it is expected that the student should decide a topic of thesis, which
is useful in the field or practical life. It is expected that students should refer national &
international journals and proceedings of national & international seminars. Emphasis
should be given to the introduction to the topic, literature survey, and scope of the proposed
work along with some preliminary work / experimentation carried out on the thesis topic.
Student should submit two copies of the Phase - I thesis report covering the content
discussed above and highlighting the features of work to be carried out in
Phase – II of
the thesis. Student should follow standard practice of thesis writing. The candidate will
deliver a talk on the topic and the assessment will be made on the basis of the work and talks
there on by a panel of internal examiners one of which will be the internal guide. These
examiners should give suggestions in writing to the student to be incorporated in the Phase –
II of the thesis.
39
LMV 401
MASTER’S THESIS
L T P C
0 0 30 20
In the fourth semester, the student has to continue the thesis work and after successfully
finishing the work, he / she has to submit a detailed thesis report. The work carried out
should lead to a publication in a National / International Conference. They should have
submitted the paper before M. Tech. evaluation and specific weightage should be given to
accepted papers in reputed conferences.
LMV 402
MASTER’S COMPREHENSIVE VIVA
A comprehensive viva-voce examination will be conducted at the end of the fourth semester
by an internal examiner and external examiners appointed by the university to assess the
candidate‟s overall knowledge in the respective field of specialization.
40