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922
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 10, OCTOBER 2007
A CMOS Low-Dropout Regulator With Current-Mode
Feedback Buffer Amplifier
Wonseok Oh, Member, IEEE, and Bertan Bakkaloglu, Member, IEEE
Abstract—Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response,
low-dropout regulators (LDRs) are critical for supply regulation
of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO)
Hz, and
achieves an output noise spectral density of 67.7 nV
PSR of 38 dB, both at 100 kHz. In comparison to an equivalent
power consumption voltage feedback buffer LDO, the proposed
CFA-based LDO settles 60% faster, achieving 0.6- s settling time
for a 25-mA load step. The LDO with CFA buffer is designed and
fabricated on a 0.25- m CMOS process with five layers of metal,
occupying 0.23-mm2 silicon area.
Index Terms—Current feedback amplifier (CFA), low-dropout
regulators (LDRs), power supply rejection.
I. INTRODUCTION
A
S DEMAND for low power operation products increases,
power supply regulation circuitry starts playing a critical
role in battery operated applications. The low-dropout linear
regulator (LDR) is one of the most versatile power converters
widely used in integrated power management systems and is
also used as post regulators of switching converters. The main
drawback of linear regulators is their reduced power efficiency,
which is determined by dropout voltage of regulation FET.
LDRs provide low output noise and high power efficiency with
low dropout voltage of pass device, they shield sensitive blocks
from high frequency fluctuations on the power supply and they
offer high accuracy, fast response supply regulation [1]–[7].
There are several factors that have an effect on the response of
a low dropout (LDO) to a load transient, such as external compensation of the LDO, output capacitance, and the parasitics of
the output capacitor including electrical series resistance (ESR)
and electrical series inductance (ESL). As shown in Fig. 1, the
feedback loop of LDO, which consists of the output capacitor,
feedback network, error amplifier, and regulation field-effect
transistor (FET), determines the LDO’s frequency response.
The unity gain frequency (UGF), slew rate and stability of
the LDO circuit determine the overall transient response of
the LDO. The output capacitance and its associated parasitic
elements affect the transient response of the LDO circuit also.
Although larger output capacitors decrease the amplitude of
Manuscript received October 17, 2006; revised March 2, 2007. This work is
supported by Connection One Research Center, National Science Foundation
I/U CRC, and Texas Instruments Incorporated. This paper was recommended
by Associate Editor E. Alarcon.
W. Oh is with the RFMD Inc., Chandler, AZ 85266 USA (e-mail: wonseok.
[email protected]).
B. Bakkaloglu is with the Department of Electrical Engineering, Arizona
State University Tempe, AZ 85287 USA (e-mail: [email protected]).
Digital Object Identifier 10.1109/TCSII.2007.901621
Fig. 1. Block diagram of a typical LDO regulator.
the transient settling, they also tend to increase the settling
time. A typical LDO’s settling time is around 2–6 s. Recently
dual-loop feedback techniques are shown to improve transient
response [8].
Voltage operational amplifiers (VOAs) have a fixed gainbandwidth product and the amplifier slew rate is determined
by the ratio of a quiescent current to the compensation capacitor or load capacitor. In this work, a dual feedback structure is
adopted. A global voltage mode feedback achieves an accurate
steady-state operation, and a secondary current feedback amplifier (CFA) is utilized to achieve fast transient response and high
slew rate.
This brief is organized as follows. Overview of settling time
and stability of internally compensated LDO regulators under
low quiescent current conditions is described in Section II.
Section III presents the system and circuit level description
of the proposed fast transient response LDO architecture.
Section IV presents the silicon evaluation results.
II. OVERVIEW OF SETTLING-TIME AND STABILITY OF LOW
QUIESCENT CURRENT LDOS
Fig. 1 shows a block diagram of a typical LDO regulator,
which consists of an error amplifier, a pass device (regulation
FET), high resistance feedback network, and an output capacitor
. In order to achieve high efficiency, the error amplifier
current is usually required to be less than 1%–2% of the nominal
load current. This small quiescent current results in relatively
narrow bandwidth for the LDO.
Fig. 2 shows details of a typical LDO response to a load current step. The transient response time of an LDO to a load current step is a critical specification in analog and digital applications. The response of an LDO to a load current change is characterized in two sections; initial step response
and
, and
settling time
and
. The step response represented by
in Fig. 2 is a function of amplifier bandwidth and the large
1549-7747/$25.00 © 2007 IEEE
OH AND BAKKALOGLU: A CMOS LOW-DROPOUT REGULATOR WITH CURRENT-MODE FEEDBACK BUFFER AMPLIFIER
Fig. 2. Typical LDO transient response to load current step.
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Fig. 3. Frequency response of a typical LDO.
signal slew rate of the buffer amplifier driving the parasitic gate
capacitor
of the regulation FET.
is given by [3]
(1)
is the closed-loop bandwidth of the system,
is
where
the slew rate of the error amplifier,
is the voltage variation
at , and
is the slew rate current of the buffer stage between
, the rethe error amplifier and regulation FET. Similar to
sponse time to a load current drop
is also inversely proportional to the closed loop bandwidth of LDO. In order to minimize
and
, LDO requires a wide closed-loop bandwidth
and a higher slew rate current. Using a small output capacitor,
and
could also be minimized. Due to their extended
response time, the overall transient time of an LDO due to load
variation is determined by
and
rather than
and
. Output transient voltages
and
strongly depend on voltage drop across the electrical series resistor
and is defined by
. To improve the accuracy of an LDO during load variations, transient voltage errors
could be minimized by using small
.
Low quiescent current conditions might give rise to stability
problems. For ac analysis of an LDO, we can break the feedback
loop, as seen in Fig. 1, and calculate loop gain
as follows:
(2)
where
Fig. 4. Proposed LDO architecture using CFA based buffer amplifier.
ESR
and load capacitor
should be designed such that
overall LDO stability is guaranteed for all load and feedback
conditions. The unity-gain frequency of a typical LDO is limited by the parasitic pole generated by the output impedance of
the error amplifier and gate capacitance of the regulation FET.
This pole can be pushed to a higher frequency by using a low
output impedance voltage buffer between the error amplifier and
the regulation FET [12]. LDO with voltage buffer to push the
pole to higher frequencies can still take 2–6- s settling time
with full-load transients [9].
In summary, increasing the quiescent current of an LDO can
improve slew rate and achieve a wider bandwidth and faster settling time: however, LDO efficiency is reduced. On the other
hand, decreasing the quiescent current results in a larger output
capacitor and slow transient response; therefore, overcoming
speed versus efficiency tradeoff is one of the most challenging
LDO design problems.
III. WIDEBAND LDO DESIGN
(3)
where
and
represent the transconductance and output
resistance of the error amplifier and
and
represent
the transconductance and resistance of the regulation FET,
is the parasitic capacitor of the regulation FET,
is the output
capacitor and
is the ESR of the load capacitor.
As the amplifier quiescent current is reduced, the error amplifier transconductance
decreases with a square-root dependency, and the output impedance of the error amplifier
increases linearly with decreased quiescent current. Under low
quiescent current conditions,
moves closer to dc; however,
stays at its nominal value as seen in Fig. 3. To achieve a wider
bandwidth,
should also move toward lower frequencies in
order to reduce the effect of . The zero set by the capacitor
The proposed architecture utilizes a low ac impedance feedback path to achieve fast response while maintaining low quiescent power consumption. The low ac impedance feedback path
is constructed using a CFA based second-stage buffer. CFAs are
known to provide fast response with minimum slew-rate limiting [10]. As shown in Fig. 4, the proposed LDO is composed
of an OTA based voltage-feedback error amplifier (VFA) followed by a second-stage CFA, regulation FET and feedback network. The second-stage CFA minimizes the impact of slew rate,
limiting the output settling time while achieving low quiescent
current operation. A global voltage mode feedback is used for
steady state accuracy.
The Sections III-A and III-B provide details of the two
building blocks of the second-stage amplifier.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 10, OCTOBER 2007
The voltage mode loop gain of the secondary CFA is represented by
(5)
where
Fig. 5. Top level schematic of the LDO with CFA for fast transient operation.
A. VFB Error Amplifier and CFA Second Stage
Fig. 5 shows the schematic of the proposed LDO. A folded
cascode OTA is used as the first error amplifier. In order to minimize the impact of slew rate on settling time and improve the
transient response of the LDO, a second-stage CFA with an
asymmetrical input is used to drive the regulation FET [10],
at the output of the folded cascode
[11]. The error voltage
error amplifier is connected to the gate input of the CFA, and
is connected to the diode connected input
feedback voltage
transistor M14. This connection ensures that there is no dc current drawn from the primary folded cascode amplifier. The feedback current is set to a nominal value of 0.2 A. To understand
the transient behavior of the CFA, we can consider two critical
load transients.
drops.
In case of a load current increase, feedback voltage
Unlike a voltage feedback amplifier, the diode connected M14
preserves its gate-source voltage, moving the source voltage of
M13 lower. This reduction instantaneously increases the current through the common source amplifier formed by M13, responding with a fast decrease in node voltage . On the other
hand, when load current is reduced, the diode connected transistor M14 pulls the source of M13 higher, responding with a
fast increase in node voltage .
This ensures a fast response in both transient conditions with
minimum slew-rate limiting.
Fig. 6 shows the small-sginal operation of the second-stage
CFA. M14 acts as a level shifter and M13 is a source follower.
Due to symmetry, the gate-source voltage of M13 and M14 are
follows the voltage
equal; therefore, the feedback voltage
regardless of the feedback current . M15 and M16 act as a
. Impedance seen by the
current source ensuring
feedback signal
at the gate of the diode connected M14 is
.
Breaking the current feedback loop, the small-sginal gain
to
is close to unity and can be represented as
from
follows:
The dominant pole frequency of the CFA stage is
. The
is designed to cancel out with an left
second dominant pole
by using local feedback capacitor
half-plane (LHP) zero
. The right half-plane (RHP) zero
is located at higher frequency than unity gain frequency. To ensure stability of the dual
feedback system, the open-loop bandwidth of CFA is designed
to be wider than the error amplifier. For the CFA the lineup for
,.To achieve wider
the bandwidths are
bandwidth for the CFA, a smaller output capacitor
value
is utilized.
The bandwidth of the error amplifier is determined by the
transconductance of the input voltage mode amplifier and ca; therefore, it is not affected by the load current
pacitance
variation. If the stability of CFA is guaranteed in the worst case
no load current condition, the stability of overall LDO is guaranteed. Since the CFA operates as a buffer, the unity gain frequency of this buffer should be wider than the error amplifier.
The proposed LDO operates as a single pole system and always
has more than 60 degree phase margin. Fig. 7 shows the simulated open loop ac response of the proposed LDO for load conditions. The LDO achieves a phase margin of 72 at no load and
83 at full-load conditions. Finally, transistors MN1 and MP1
form a buffer stage to push the parasitic pole to high frequencies.
As discussed earlier, current-mode feedback connection from
to
enables fast transient response, and a wide CFA
node
bandwidth helps to achieve fast transient response.
(4)
(6)
B. Supply Ripple Subtraction Stage
In a conventional LDO design, the power supply ripple rejection
is improved by a loop transmission
.
is the error amplifier open-loop gain and is
term
the feedback factor
.
Power supply ripple to output voltage transfer function for a
conventional LDO can be approximated by [13]
OH AND BAKKALOGLU: A CMOS LOW-DROPOUT REGULATOR WITH CURRENT-MODE FEEDBACK BUFFER AMPLIFIER
925
Fig. 6. Equivalent small-sginal model of CFA and regulation FET.
where
is the gain from power supply
to the gate of the
in Fig. 4), is the gain from
to
regulation FET (node
the gate of regulation FET and
defines the self-gain of
the regulation FET.
As seen from (6), in order to improve PSR, gain-bandwidth of
the error amplifier and CFA should be increased. An alternative
technique to improve PSR is to design the error amplifier such
is close to unity for a wide frequency range. In this
that
design a supply ripple subtraction stage achieving close to unity
gain driving the gate of the regulation FET is designed. This
diode loaded buffer stage formed by MN1 and MP1 is inserted
between the pass element and the CFA of the LDO, as shown
Fig. 5.
This stage feeds the supply noise directly into the feedback
loop and modulates the pass element gate with respect to the
source terminal. This would reduce the drain current variation
from the pass PFET and allow the output node to be less sensitive to the supply noise.
The supply gain of this diode loaded amplifier is given by
Fig. 7. Simulated open loop ac response of error amplifier and CFA.
(7)
where
and
are the transconductance of MP1
and output conductance of MN1, respectively.
is higher than
, this amplifier yields a
Since
close to unity gain from its supply to output yielding a high PSR
(8)
Due to diode connected MP1, the quiescent current and speed
of this stage is set by the
(therefore load current) of the
regulation FET. As load current increases, the bandwidth of the
buffer amplifier increases, enabling improved PSRR at high load
currents [13].
IV. EXPERIMENTAL RESULTS
The LDO integrated circuit is designed and fabricated on a
0.25- m digital CMOS process with five layers of metal. A
voltage follower based LDO with an equivalent quiescent current is also designed in order to compare the performance of
both systems. The system was designed to source a nominal
Fig. 8. Measured PSR of the proposed LDO.
output current of 50 mA. The output noise spectral density is
measured to be 4.3 V Hz at 10 kHz and 67.7 nV Hz at
100 kHz. Integrated noise from 1 to 100 kHz is measured to be
122 V .
As shown in Fig. 8, the LDO achieves 43 dB PSR at 30-kHz
offset, using a 50-nF load capacitor. As seen in Fig. 9, LDO with
CFA stage achieves a settling time of 0.6 s, compared to a 2 s
achieved by an equivalent voltage follower LDO.
The proposed LDO has a load regulation of 2 mV/25 mA, as
shown in Fig. 10. Table I compares the proposed LDO regulator
with recently published linear regulators, and Fig. 11 shows the
micrograph of the designed LDO.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 10, OCTOBER 2007
TABLE I
PERFORMANCE COMPARISON WITH RECENT PRIOR WORK
V. CONCLUSION
A fast transient response LDO utilizing a CFA based buffer is
presented. The LDO achieves fast response under load transients
with small output capacitance. The CFA buffer amplifier also
has a supply ripple reduction stage, minimizing the impact of
reduced load capacitance.
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Fig. 9. Simulation result of load transient responses for LDO with CFA and
voltage buffer with a 25-mA load current changes with a 50-nF load capacitor
with 1-
ESR.
Fig. 10. Measured transient response of proposed LDO to 25-mA load changes
with a 50-nF load capacitor with 0.1-
ESR.
Fig. 11. Micrograph of the proposed LDO.
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