1. No category

UART: Clocking
Why Can't We Use One Clock?
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We have two different
clock domains in our
design
One of these clocks is
much slower than the
other
To solve this problem,
we're going to use clock
dividers
Fixed Clock Divider
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Used when we want a clock division by a power of 2
Implemented by chaining flip-flops together, each dividing the
last input clock by 2
Arbitrary Clock Divider
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Used when we want a clock division by a variable amount
Implemented by counting clock cycles
In our design, the “baud rate” from the bus interface is the
number of times to count before inverting the clock output
UART Clocking Problem
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Remember, only the baud rate is known between the UARTs
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Phase must be matched between two UARTs
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If the UARTs are out of phase, we'll get unexpected errors
Edge Detector
Clock
Signal
2 Bit Shift
Register
Not
delay <= signal after 3ns;
edge <= signal and not delay;
AND
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Many implementations, these might both be okay
What are the drawbacks and advantages of both?
Phase Matcher
4x
Clk
Baud
Clock
0 Deg
90 Deg
180 Deg
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Detects the clock edge
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Corrects the clocked output to match the phase
270 Deg
Phase Matching Circuit Hints
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We need to sample the actual Baud clock to determine phase
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Use a shift register to sample the baud clock
We need to sample the Baud clock at a faster rate (16x)
We need to pick one of the outputs from the shift register as
the phase matched clock
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Keep track of which bit in the shift register contains the
rising or falling edge of the Baud Clock
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When the RX line drops, (edge detection!) continue to
watch a single bit from the shift register
Baud Clock Generator
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Questions for Consideration:
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How should you attach the parts to get the Baud Clock?
What is the difference between the TX_clk and RX_clk?
What is the relation between the Baud_Sel_Code and the
actual Baud Clock rate?
What is the minimum clock division?