Analysis and Design of Ultra-Wideband Low-Noise
Amplifier With Input/Output Bandwidth
Optimization and Single-Ended/
Differential-Input Reconfigurability
Boyu Hu, Student Member, IEEE, Xiao Peng Yu, Member, IEEE,
Wei Meng Lim, and Kiat Seng Yeo, Senior Member, IEEE
Abstract—A CMOS low-noise amplifier (LNA) for ultrawideband universal radio is presented. Based on capacitive crosscoupled dual-gm -enhancement topology, the circuit topology
could be reconfigured as different versions for single-ended or
differential inputs. One possible input/output resonant scheme is
analyzed and may help the LNA to exhibit input matching, low
noise, and flat gain in an ultra-wide frequency band with relatively
low power consumption. Both a differential-input-differentialoutput and a single-ended-input-differential-output version are
fabricated in 0.18 μm CMOS technology. The differential-input
version achieves an 11–14 dB S21 , ≤ −9 dBS11 within 1.4–
11.4 GHz, and a minimum noise figure of 3.9 dB; the singleended-input version achieves a 5–8 dB S21 , ≤ −10 dBS11 among
2.4–11.7 GHz, and a minimum noise figure of 6.3 dB.
Index Terms—Low-noise amplifier (LNA), radio frequency integrated circuit (RFIC), ultra-wideband.
I. I NTRODUCTION
R
ADIO FREQUENCY integrated circuits (RFICs) are key
components in nowadays industrial applications. Among
all these applications, ultra-wideband transceiver is one of the
most challenging parts which offer high-speed and low-power
wireless link [1]–[3]. Many previous subsystem or building
blocks have been reported in CMOS technology, which offers
a high level of integration [4]–[9]. Recently, the blooming
development of universal radio-on-a-chip solutions, which suits
for soft-ware-defined radio or cognitive radios system requirements, calls for very wideband RF front-ends with application
flexibility [10], [11].
Placed in front of the whole receiver, a high performance
wideband low-noise amplifier (LNA) with certain flexibility to
the input signal is very critical. Hence, many high performance
Fig. 1. Reconfigurable wideband front-end in its different versions for singleended/differential inputs.
low noise amplifiers have been reported in recent years [12]–
[29]. In general, differential signal is highly preferred in a
system-on-chip environment due to its larger dynamic range
and higher common mode rejection ability. However, since the
received signal from antenna is usually single ended, certain
strategies should be adopted to convert this signal into differential mode. A single-ended LNA can be used together with a
single-to-differential converter to provide differential signal to
the mixer and the remaining receiver chain. A differential LNA
can also be used together with an external on-board balun to
convert the signal into differential before amplifying. However,
each of these two strategies has its own pros and cons. One
effective solution is to make the LNA flexible to either singleended or differential-input signals with differential output. As
shown in Fig. 1, if a front-end can be compatible with singleended/differential inputs by reconfiguring, the received signal
from antenna can either go directly into the LNA or convert into
differential signal using an on-board balun before going into
the LNA [12]. By doing so, much flexibility can be provided
while dealing with different standards. Combining this input reconfigurability within ultra-wideband LNA calls for intelligent
design techniques to maintain both input matching and voltage
gain flatness at a reasonable level with either its single-ended or
differential-input version.
This paper analyzes one ultra-wideband differential-output
LNA topology, the input of which could be either singleended or differential signals in its different versions. One
similar design employing the capacitive-cross-coupled dualgm -enhancement topology for differential/single-ended-input
compatibility has been reported for DVB-H tuner front-end
design, but only covers a limited frequency range from
0.15 GHz to 1 GHz due to its applications [12]. One possible
input/output resonant scheme, which may allow wideband input
Fig. 3. Input matching for single-ended/differential inputs [12].
needed. As shown in Fig. 3, without considering the frequency
characteristic, the input impedance of both single-ended and
differential mode can be estimated as
1
1
(1)
+
Zin ≈
2gm1,2
2gm1,2
where gm1,2 is is the transconductance of M1,2 . The voltage gain of both single-ended and differential mode from the
source/gate of input pair to the LNA’s output without considering frequency characteristic can be estimated as
Hout =
Fig. 2.
Reconfigurable ultra-wideband low-noise amplifier.
matching and output voltage gain flatness within a single stage
for power efficient design, is analyzed here. In addition, one
matlab-based optimization scheme is analyzed, which may help
the design at the initial stage.
Section II analyzes ultra-wideband LNA design techniques
and possible bandwidth optimization scheme, Section III discusses the experiment results, and Section IV concludes this
work.
II. U LTRA -W IDEBAND LNA A NALYSIS
A. Ultra-Wideband LNA Design Techniques
Fig. 2 shows the schematic of the LNA topology. Capacitor
C1 and C2 connect the source of M1 and M2 to the gate
of each other and form the first gm -enhanced pair. When
connecting two inductors Ld1 and Ld2 to the source of M1 and
M2 , this circuit is configured as a gm -enhanced common gate
differential LNA with a second-order LC-matching network in
front [12], [14]. The effective transconductance of both M1 and
M2 is doubled without any additional dc power consumption
due to the capacitive-cross-coupled opposite signal from each
other of the differential-input signal. When connecting only one
inductor Ls1 to the source of M1 , leaving the source of M2
short to ground, M1 and M2 work as a common gate input stage
and common source input stage, respectively. The LNA is then
configured as a single-ended-input differential output BalunLNA [12]. Ld1,2 /Ls1 could be placed on-board to provide full
reconfigurability, or they could be placed on-chip if the targeted
input version has been fixed and a higher integration level is
Zin
2gm1,2 R1,2
Rs + Zin
(2)
where R1,2 are the resistance loading at the output.
It can be seen from (1) and (2) and Fig. 3, due to the
capacitive cross-coupling at the input, the input impedance and
voltage gain of the LNA for both single-ended and differential
mode could be the same.
C3 and C4 connect the source of the cascade transistor M3
and M4 to each other’s gate, forming a second gm -enhanced
pair that balances both output differential signal and reduces
the noise contribution from M1 − M4 [12].
In this paper, an ultra-wideband LNA topology with certain input reconfigurability is targeted. Bandwidth optimization
technique needs to be properly chosen in order to broaden
the working frequency range of the existing single-ended/
differential-input ccompatible architecture. Using singleresonant tank for bandwidth optimization may not be enough in
ultra-wideband applications. Past literatures have reported some
ideas of using multiresonant instead of single-resonant tank.
As shown in Fig. 4(a), [13] proposed a parallel sourcedegenerated common source transistors to make a dual-resonant
input stage with two peakings at f1 and f2 . [15] proposed a
T-coil-based output load to make a dual-resonant output stage
with two peakings at f3 and f4 and use one-resonant tank at
input for staggered compensation, as shown in Fig. 4(b). However, both input/output bandwidth optimization may be more
expected for ultra-wideband LNA design instead of only input
or output bandwidth optimization under certain conditions. In
addition, bandwidth optimization should be kept within one
stage for power-efficiency consideration.
Thus, one possible single stage, input/output bandwidth
optimization scheme is analyzed in this work. The topology
is similar to some of the literature works [12], [22] and its
differential-input version topology was first reported in [26].
However, in this work, the architecture is explained in detail
with clearer input/output resonant concept and possible optimization scheme analysis together with silicon prototypes.
Fig. 5. Small-signal equivalent model for (a) input resonant network with
intrinsic feedback and (b) output resonant network with cascade feedforward.
Fig. 4. (a) Dual-resonant input matching proposed in [13]. (b) Dual-resonant
output loading proposed in [15]. (c) Input/output resonant scheme analyzed in
this work.
As shown in Fig. 2, load Inductor L3 and L4 , together with
resistor R1 and R2 , form the low quality factor 2nd -order shunt
peaking load, which extends the working frequency band of the
LNA. Interstage inductors L1 and L2 , together with parasitic
capacitance Cp1 at the drain of the input pair M1,2 and Cp2
at the source of the cascade pair M3,4 , form a 2nd -order πtype resonant tank. This interstage-peaking technique has been
used in previous ultra-wideband LNA design [22], but the main
purpose there is to eliminate the noise leakage of the cascade
stage at high frequency. Its impact on the LNA’s bandwidth
is not fully emphasized. In this paper, its possible usage for
bandwidth optimization is analyzed. As shown in Fig. 4(c),
this resonant tank has an effect of resonant feedback to the
input and resonant feedforward to the output. Together with the
original resonant tank located at input and output, multiresonant
at input/output may be expected under certain conditions, which
may enhance the input matching and gain performance of the
whole LNA within its working bandwidth.
Reconsider the input impedance among wide band frequency, it can be derived as
1
//sLd1
(3)
sCp1
1
sLd1
HZin (s) = //HZ1 (s) =
gm1,2
1 + (gm1,2 + sCp1 )sLd1
kZin QZ sωnZ
in
in
= s 2
(4)
+ QZ sωnZ + 1
ωnZ
HZ1 (s) =
in
1
gm1,2
ωnZin
kZin
in
in
ro1 + HZL (s)
=
(5)
1 + gm1,2 ro1
1
Cp1 ro1 + HZL (s)
=
QZin =
Ld1 Cp1
Ld1 1 + gm1,2 ro1
1
= (6)
gm1,2
where ro1 is the intrinsic output resistance of M1 , Cp1 −Cp3 are
the parasitic capacitance at the source and drain of M1 , and also
the source of M3 . ZL is the interstage load at the drain of M1,2 .
Generally, without considering ro1 ’s feedback effect, a common gate input LNA will have one resonant tank Z1 , which is
composed of Ld1 , Cp1 , and 1/gm1,2 . Its expression is shown in
(3) and (4). Equations (5) and (6) derive the natural frequency
and quality factor of this 2nd -order system. By properly placing
two complex poles, this 2nd -order bandpass resonant tank could
keep its impedance around targeted value within a certain
frequency band to meet the S11 requirement of the LNA. This
input-matching scheme is adopted in many of the previously
reported common-gate wideband LNA designs.
However, the feedback effect of ro1 may not be simply
ignored in wideband common-gate LNA design under some
conditions, which is mainly due to two reasons. First, as the
CMOS technology goes into deep-submicro, the intrinsic output impedance of the transistor decreases sharply. Second, the
input transistor of an LNA is usually biased at a relatively high
current-density level and configured as multifinger minimum
channel length transistors in parallel for high-performance design, which further brings the output impedance of the input
transistor down. As shown in Figs. 4(c) and 5(a), ro1 acts as
an intrinsic feedback resistor, which effectively couples the
impedance frequency response at the drain of the input stage
back to its source, thus affecting the input matching. From (6),
it can be seen that while the nature frequency remains the same,
this intrinsic feedback introduces a frequency variation term
HzL (s) into Qzin . Equation (5) also indicates that this loading
effect can be modeled as a series combination of 1/gm1,2 and
the interstage LC network with a scale ratio of 1/gm1,2 ro1 .
For conventional cascade common gate input stage, HzL (s) is
(s), which is a purely capacitive singleshown in (7) as HzL
pole rolling-off system. When being feedback, this capacitive
loading degrades the input bandwidth performance. Unlike the
1st -order capacitive load, interstage peaking introduces a 2nd order π-type resonant tank and it takes place of the capacitive
term, as expressed in (8). Putting (8) into (4) can get the
5th -order expression of the input impedance considering the
intrinsic feedback effect, the simplified expression as shown
in (9) and (10). As stated previously, the input impedance is
now affected by both Z1 and Z2 . If the parameters of these
two resonant tanks are properly arranged, e.g., by placing the
center resonant frequency of Z1 at relatively low frequency
Fig. 6. Simulated input impedance with and without intrinsic-feedback effect
based on LNA’s ideal small-signal equivalent model.
Fig. 7. Simulated gain with cascade-resonant effect based on LNA’s ideal
small-signal equivalent model.
and Z2 at relatively high frequency, a better in-band input
impedance matching with less variation may be expected under
certain conditions. Fig. 6 shows the simulated input impedance
with and without considering the intrinsic feedback effect of
interstage resonant tank Z2 based on the LNA topology’s equivalent ideal small-signal models for illustration. It is observed
that with this intrinsic feedback, multiresonant at input stage
may appear, and the magnitude of the input impedance may
be kept within a certain range around the targeted value for a
relatively wider frequency range comparing that with singleresonant under certain conditions. In other words, the input
impedance could be considered as being “boosted” at higher
frequency and thus a better matching performance may show
up within the targeted frequency range under certain conditions
folds: it should help to keep the wideband input matching together with the resonant tank Z1 at input by intrinsic feedback;
it should also help to broaden the output frequency range by
feedforward cascading with the resonant tank Z3 at output.
Equations (12) and (13) present the expression of Z2 and Z3 ’s
impact on the voltage gain of the LNA. Equation (14) states
the natural frequency and quality factor, as well as the zero of
this two cascaded 2nd -order systems. As shown in Fig. 7, if
the natural frequency and quality factor, as well as the zero of
Z2 and Z3 , could be properly optimized, such as placing Z3
at relatively low frequency and Z2 at higher frequency while
still keeping reasonable input-matching condition regarding the
placement of Z1 , a wideband output voltage gain with good
flatness could be expected
Zin (s)
1
−
Hout (s) =
Rs + Zin (s) (Rs + Zin (s)) Z1 (s)
(11)
× Hα (s)HZ3 (s)
1
Hα (s) =
s(Cp2 +Cp3 )
s2 L1 Cp2 +
+1
gm3,4
1
= s 2
(12)
s
ωnα + Qα ωnα + 1
1
sL3 + R1
//(sL3 + R1 ) = 2
HZ3 (s) =
sCp4
s L3 Cp4 + sR1 Cp4 + 1
k(s + ωz )
= s 2
(13)
s
ωnZ3 + QZ3 ωnZ3 + 1
gm3,4 L1 Cp2
1
, Qα =
ωnα = Cp2 + Cp3
L1 Cp2
1
ωnZ3 = L3 Cp4
1
R1
L3
Q Z3 =
, ωZ =
.
(14)
R1 Cp4
L3
HZ L (s) =
1
s(Cp2 + Cp3 )gm3,4
(7)
HZL (s)
s2 L1 Cp3 + 2sL1 gm3,4 + 1
2
1 Cp2 Cp3 + s L1 Cp2 gm3,4 + s(Cp2 + Cp3 ) + gm3,4
(8)
A4 s4 + A3 s3 + A2 s2 + A1 s
HZin (s) =
(9)
B5 s5 + B4 s4 + B3 s3 + B2 s2 + B1 s + B0
A4 = Cp2 Cp3 L1 Ld1 ro1
A3 = Cp3 L1 Ld1 + Cp2 L1 Ld1 gm3,4 ro1
A2 = L1 Ld1 gm3,4 + (Cp2 + Cp3 )Ld1 ro1
A1 = Ld1 (1 + gm3,4 ro1
B5 = Cp1 Cp2 Cp3 L1 Ld1 ro1
B4 = Cp1 Cp3 L1 Ld1 + Cp2 Cp3 L1 Ld1
+ (Cp1 Cp2 L1 Ld1 gm3,4 ro1
B3 = Cp1 L1 Ld1 gm3,4 + Cp2 L1 Ld1 gm3,4 + Cp2 Cp3 L1
+ (Cp1 + Cp2 + Cp3 )Ld1 + Cp2 L1 Ld1 gm1,2 gm3,4 ro1
B2 = Cp3 L1 + (Cp1 + Cp2 + Cp3 )Ld1
+ ((Cp2 + Cp3 )Ld1 gm1,2 + Cp1 Ld1 gm3,4 ) ro1
B1 = (L1 +Ld1 )gm3,4 +(Cp2 +Cp3 )ro1 +Ld1 gm1,2 gm3,4 ro1
B0 = gm3,4 ro1 + 1.
(10)
=
s3 L
The gain performance of the LNA is affected by all of the
three resonant tanks within the given single-stage architecture.
Equation (11) shows the voltage gain expression of the LNA.
The interstage resonant tank Z2 affects the voltage gain in two
B. Bandwidth Optimization Scheme
Equations (3)–(14) present the essential analytical expressions for input matching and voltage gain design of the ultrawideband LNA based on its ideal small-signal equivalent
model. Input/output bandwidth optimization calls for iterations
between the input and output network parameter tuning. Thus,
one possible matlab-based optimization scheme for estimation
at initial stage is analyzed here.
Fig. 9.
Fig. 8. (a) Sweeping proper Ld1,2 for input bandwidth optimization.
(b) Sweeping proper L1,2 for input bandwidth optimization. (c) Sweeping
proper L3,4 based on a qualified set of L1,2 and Ld1,2 for output gain
bandwidth optimization.
In addition to input/output bandwidth, the design of LNA
also requires noise, gain, and linearity considerations. All of
these considerations are related to the proper sizing and biasing
of the transistors, hence affecting the transconductance and
parasitic capacitors, which appear as the design parameters
in (3)–(14). One possible design scheme is to optimize the
transistor sizing and biasing first, according to the noise, gain,
and linearity performance during the initial iteration and then to
optimize the input/output bandwidth by using proper inductor
values of Ld1,2 , L1,2 , and L3,4 . Finally, verify whether the
initial iteration and the input/output bandwidth optimization fit
the system requirements. Perform a few iterations if the system
specification is not achieved during first trial.
By this scheme, after fixing the size and biasing condition
of all the transistors and fitting their other parameters such as
parasitic capacitance and output resistance by some preliminary
technology-related Spice simulations, the design parameters
in (3)–(14) may be reduced to Ld1,2 , L1,2 , and L3,4 only.
Thus, the input/output bandwidth optimization problem may be
considered as a linear programming problem stated in
T arget
fmax _out − fmin _out ≥ fbandwidth_out
fmax _in − fmin _in ≥ fbandwidth_in
Subject to
L1,2 , L3,4 , Ld1,2 ∈ (Lmin , Lmax )
|HZin (jf )| − |HZin0 |L1,2 ,Ld1,2 ≤ ΔHZin
f ∈ (fmin _in , fmax _in )
|Hout (jf )| − |Hout0 |L1,2 ,Ld1,2 ,L3,4 ≤ ΔHout
f ∈ (fmin _out , fmax _out ).
(15)
(16)
(17)
(18)
The target is to find the optimized input/output bandwidth,
(fmax _out − fmin _out ) and (fmax _in − fmin _in ) among all
the available L1,2 , Ld1,2 , and L3,4 values, as stated in (17)
and (18), and also being conceptually demonstrated in Fig. 8.
Certain constraints should be put upon this search. First, the
inductor value of L1,2 , L3,4 , and Ld1,2 should be kept within
a certain range for realistic on-chip implementation, as presented in (16). Second, as shown in Fig. 9(a) and (b), for a
(a) Output bandwidth optimization. (b) Input bandwidth optimization.
given ultra-wideband LNA design, the variation of both input
impedance and voltage gain should be kept within a certain
range around the target specifications, for example Hzin0 + /
−ΔHzin and Hout0 + / −ΔHout , in (17) and (18). For a set of
L1,2 , Ld1,2 , and L3,4 values that satisfy (17) and (18), they may
be selected as the optimum design parameter at the intial stage.
In more detail, the optimization procedure could be divided
into three basic steps.
Step 1: Do initial parameter estimation. As analyzed in the
above, the sizing and biasing of transistors could be optimized first according to the requirements of gain, noise,
linearity, and power consumption. Input stage transconductance gm1,2 could be set to meet input matching requirement in (1). Output resistor load R1,2 could then be set
for gain (2) and noise figure (19)–(21) requirements. Then,
the bias current density could be optimized for linearity
[27] and power consumption considerations. After these
initial deductions, the design parameters of Cp1,2 , Cp3,4 ,
gm1,2 , gm3,4 , R1,2 , and ro1,2 may be fixed as an initial start
point, leaving L1,2 , Ld1,2 , and L3,4 as the unknown design
parameters.
Step 2: Input/output bandwidth optimization. For an ultrawideband LNA design, an initial frequency boundary
(fmin , fmax ) for the input/output should be set as a
starting point for the optimization procedure. Then,
the targeted input impedance and voltage gain value
should be set as Hzin0 and Hout0 . In addition, the
variation tolerance among the bandwidth should be set
as ΔHzin and ΔHout . The value of L1,2 , Ld1,2 , and
L3,4 is chosen within a certain range (Lmin , Lmax ). For
input bandwidth optimization, twofold loop search of
Ld1,2 and L1,2 could be implemented, and a group of
qualified Ld1,2 and L1,2 values that satisfy the preset
input-bandwidth target fbandwidth_in could be saved.
After the input-bandwidth optimization, for each pair of
the qualified value of Ld1,2 and L1,2 , one loop search of
L3,4 could be implemented to further optimize the output
gain performance. For input bandwidth optimization, due
to its bandpass characteristic, for each pair of Ld1,2 and
L1,2 , the 1st positive cross of the transfer function over
the boundary of Hzin0 − ΔHzin could be set as fmin _zin
and the last negative cross of the transfer function over the
boundary of Hzin0 − ΔHzin could be set as fmax _zin .
Similarly, for output bandwidth optimization, due to
its bandpass characteristic, for each pair of qualified
Ld1,2 and L1,2 , which is obtained from input-bandwidth
optimization, L3,4 could be loop searched. And for each
For the differential-input version, as shown in Fig. 10(a), the
input stage transistors are capacitive-cross-coupled. Thus, the
well-known gm -boosting technique [14] forms here to reduce
the noise and power consumption. Physically remaining the
same value, the effective transconductance when looking into
the source of M1,2 doubles due to the opposite input signal fed
to the gate of M1,2 .
The noise factor expression for the proposed LNA under
input matching condition in differential-input mode can be
given as (19)
2
FDif f = 1 +
L3,4 , the 1st positive cross of the transfer function over
the boundary of Hout0 − ΔHout could be set as fmin _out
and the last negative cross of the transfer function over the
boundary of Hout0 − ΔHout could be set as fmax _out .
For each pair of (fmin _zin , fmax _zin ), if there is no
frequency f in between such that Hzin (f ) − Hzin0 ≥
ΔHzin , (Ld1,2 , L1,2 , fmin _zin , fmax _zin ) could be stored
as one cell of qualif ied_set_input. Based on the Ld1,2 ,
L1,2 in qualif ied_set_input, gain performance could
be further optimized by searching proper L3,4 . For each
pair of (fmin _out , fmax _out ) that satisfies the preset
output bandwidth fbandwidth_out , if there is no frequency
f in between such that Hout (f ) − Hout0 ≥ ΔHout ,
(L1,2, L3,4, Ld1,2, fmin _zin, fmax _zin, fmin _out , fmax _out )
could be stored as one cell of qualif ied_set_total.
Step 3: for each cell in qualif ied_set_total, calculate
input_bandwidth, output_bandwidth, centre_f req_in
and centre_f req_out. Then, to verify whether these meet
the LNA system specifications. If not, an iterative could be
adopted starting from the initial parameter estimation.
With appropriate initial parameter estimation, this bandwidth
optimization scheme may provide relatively reasonable range
estimation of Ld1,2 , L1,2 , and L3,4 values, which leads to optimized input and output bandwidth to the first order. It should be
noticed that since simplified inductor/capacitor/transistor models are adopted in the numerical calculation, the matlab-based
input/output optimized scheme may provide optimistic results comparing with real inductor/capacitor/transistor-included
circuit-level design in some cases. However, this optimization
procedure still offers initial estimation, which can be used as
a reasonable initial starting point for the transistor-level circuit
design at the later stage.
C. Noise Analysis
When being reconfigured for either differential input or
single-ended input, the circuit topology of the LNA changes
and thus the noise analysis need to be implemented separately.
Vn,M1out
FSE
2
Rs /2
2
4kT
Rs /2 Rs /2+1/2gm1,2 R1
2
γ
+
2 gm1,2 R1
= Vn,M1_path1 − Vn,M1_path2
Rs
= − 4kT γgm1,2
R1
1/gm1,2 + Rs
Rs /gm1,2
+ 4kT γgm1,2
R1
1/gm1,2 + Rs
=0
4kT γgm1,2 R1 2 + 8kT R1
=1 +
4kT Rs gm1,2 2 R1 2
2
=1 + γ +
.
gm1,2 R1
=1 +
Fig. 10. (a) gm -boosting for differential-input noise reducing. (b) Noise
cancelling for single-ended-input noise reducing.
Rs /2
4kT γgm1,2 Rs /2+1/2g
R1 2 + 4kT R1
m1,2
(19)
(20)
(21)
Due to the gm -boosting of the input differential pair, which
dominates the noise performance of the LNA, the noise contribution can be halved in theory, as shown in (19). In reality, the
feedforward gain for boosting may be less than 1, due to the
capacitive dividing effect between the cross-couple capacitor
and the parasitic capacitor at the gate of the input transistors.
Hence, the effective noise performance improvement should be
less than the theoretical estimation.
For the single-ended version, in Fig. 10(b), the gm -boosting
of the input stage no longer exists due to the lack of differentialinput signal. However, the LNA reconfigures as an active-balun
now. The noise current in M1 will appear at the differential
output through two paths. Path1 goes into the source of M1 ,
then go through M3 to Vout + as Vn_M 1_path1 . Path2 first
being converted to Vnin , then amplified by the common source
cascade M2 and M3 and appears at Vout − as Vn_M 1_path2 .
As shown in (20), due to the balanced output voltage gain,
the differential output noise generated by M1 exhibits the
same magnitude and polarity. Since these two output noise
are correlated, they can be cancelled out at the differential
output theoretically, which resembles the noise-cancelling technique [28]. (21) presents the noise factor expression for singleended version. Though lacking of gm -boosting at the input,
the employed noise-cancelling technique still partly reduces the
dominant noise contribution from the input stage, thus keeping
the total noise performance at a reasonable level [12].
It should be noticed that in both (19) and (21), the noise
estimation factor is inverse proportional to the voltage gain
of the LNA. This should be included in the design parameter
initial estimation of the input/output bandwidth optimization
procedure.
Fig. 11. Die photo of differential-input version.
Fig. 13. S21 and S11 performance of both single-ended/differential-input LNAs.
Fig. 12. Die photo of single-ended-input version.
III. E XPERIMENT R ESULTS
Both the differential-input and single-ended-input version of
the LNA are fabricated in Tower Jazz 0.18um SiGe technology,
of which only CMOS transistors are used for this design.
Figs. 11 and 12 show the chip photograph of the LNA in
both differential-input and single-ended-input versions. Output
buffers are included on-chip to drive the external 50 ohm load
of the measurement equipment. Input inductors are directly
implemented on-chip and on wafer measurement is performed
to characterize the LNA.
Fig. 13 shows the Scattering (S) parameters of both
differential-input and single-ended-input versions. The input
reflection coefficient S11 is less than −9 dB and the S21 is
among 11 dB-14 dB from 1.4-11.4 GHz in differential-input
mode; while the input reflection coefficient S11 is less than
−10 dB and the S21 is among 5 dB–8 dB from 2.5 to 11.7 GHz
in single-ended-input mode.
Fig. 14 shows the noise figure performance of the two LNAs.
For the differential-input LNA, external wideband baluns are
employed at both the input and output of the LNA to properly
connect it with the noise figure measurement equipement. For
the single-ended-input LNA, only one wideband balun is employed at the output. The insertion loss introduced degradation
due to the balun at LNA’s input has been de-embeded from the
result. In differential-input version, the noise figure is between
3.9 dB and 4.5 dB from 3 to 10 GHz; in single-ended version,
it is between 6.3 dB and 6.8 dB.
Fig. 14. Noise figure performance of both single-ended/differential-input LNAs.
Fig. 15.
P1dB performance of single-ended-input LNA.
TABLE I
C OMPARISON W ITH L ITERATURES
Due to the lack of multiple signal sources, the linearity
performance of the LNA is measured with 1 dB compression
point. As shown in Fig. 15, the P1dB performance is −11 dBm
in single-ended version, which is measured at 9 GHz. Based
on this, the equivalent IIP3 could be estimated as −1 dBm in
single-ended version.
The performance of the proposed LNA is summarized and
compared with previous works [12]–[25] in Table I.
IV. C ONCLUSION
An ultra-wideband LNA topology, which provides certain reconfigurability for differential/single-ended inputs, has
been presented. By adopting capacitive-cross-coupled dual-gmenhancement topology, the circuit topology could either be
configured as an ultra-wideband differential-input differentialoutput gm -enhanced LNA or a single-input differential-output
balun-LNA in its different versions. One possible input/output
resonant scheme by intrinsic feedback and cascade feedforward and its possible usage for the input impedance matching
and output voltage gain range optimization is analyzed. One
possible matlab-based optimization scheme, which may help
the design at the initial stage, is also analyzed here. This LNA
achieves an 11–14 dB S21 , ≤ −9 dBS11 among 1.4–11.4 GHz
with a minimum noise figure of 3.9 dB in its differential-input
version; a 5–8 dB S21 , ≤ −10 dBS11 among 2.5–11.7 GHz
with a minimum noise figure of 6.3 dB in its single-ended
version. The one-stage architecture makes it consume a relatively low power of 8 mW (estimated core circuit) excluding
the auxillary bias-circuits and on-chip buffers.
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Boyu Hu (S’13) received the B.Sc. degree in electronic and information engineering (Hons.) from
Chu-Ko-Chen Honors College, Zhejiang University,
Hangzhou, China, in 2008, and the M.S. degree in
circuits and systems from the Institute of Very Large
Scale Integration (VLSI) Design, Zhejiang University, Hangzhou, in 2011. Since 2011, he has been
working toward the Ph.D. degree at the University
of California, Los Angeles, CA, USA.
Between March and August 2011, he held the
position of RF/Mixed-Signal IC Designer at Marvell,
Shanghai, China, working on low-power wireless transceivers. Since June 2013,
he has held the position of Mixed-Signal IC design Intern at Broadcom, Irvine,
CA, working on high-precision mixed-signal audio products. His research interests include low-power high-speed data converters, all-digital frequency/clock
synthesizers, mm-wave/sub-mm-wave, and audio/power-management integrated circuit and system.
Xiao Peng Yu (M’06) received the B.Eng. degree
in optical engineering from Zhejiang University, Yu
Quan, Hangzhou, China, in 1998, and the Ph.D.
degree in radio-frequency integrated circuits design
from the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU),
Singapore, in 2006.
Before joining NTU as a Ph.D. candidate in 2002,
he was with MOTOROLA Global Telecom Solution
Sector, Hangzhou. He joined the College of Electrical Engineering, Zhejiang University, Hangzhou, on
September 2006, where he is currently an Associate Professor. Since January
2008, he has been with the Eindhoven University of Technology, Eindhoven,
The Netherlands, as a Visiting Scholar. Since August 2009, he has been a Marie
Curie Fellow (IIF) in TU/e (Co-hosted with Philips Research, Eindhoven).
His research interests include silicon-based radio frequency/millimeterwave integrated circuits design and phase-locked loops for high-speed data
communications.
Wei Meng Lim received the B.E. (Hons.) and M.E.
degrees in circuits and systems from Nanyang Technological University (NTU), Singapore, in 2002 and
2004, respectively.
Upon his graduation, he joined NTU as a member
of the Research Staff. His research interests include
RF circuit design, RF device characterization, and
modeling.
Kiat Seng Yeo (SM’09) received the B.Eng. (with
Honors) and the Ph.D. degrees in electrical engineering from Nanyang Technological University (NTU),
Singapore, in 1993 and 1996, respectively.
He is an Associate Chair (Research) of the School
of Electrical and Electronic Engineering, NTU, and
Board Member of the Singapore Semiconductor Industry Association. He was the Founding Director of
VIRTUS, a research center of excellence jointly set
up by NTU and the Economic Development Board.
He has published six books, three book chapters, and
320 international top-tier refereed journal and conference papers, and holds
25 patents.
Dr. Yeo serves on the editorial board of IEEE T RANSACTIONS ON M ICRO WAVE T HEORY AND T ECHNIQUES and holds/held key positions in many
international conferences as Advisor, General Chair, Co-General Chair, and
Technical Chair. He was awarded the Public Administration Medal (Bronze) on
National Day 2009 by the President of the Republic of Singapore, and was also
awarded the distinguished Nanyang Alumni Award in 2009 for his outstanding
contributions to the university and society.