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A 35-mW 30-dB Gain Control Range Current Mode
Linear-in-Decibel Programmable Gain Amplifier
With Bandwidth Enhancement
Thangarasu Bharatha Kumar, Student Member, IEEE, Kaixue Ma, Senior Member, IEEE,
Kiat Seng Yeo, Senior Member, IEEE, and Wanlan Yang
Abstract—This paper presents the design of a programmable
gain amplifier (PGA) that serves as an interface between the
receiver front-end and the baseband processor. The proposed
PGA design is fabricated in a commercial 0.18- m SiGe BiCMOS
process with a topology consisting of two digitally variable gain
amplifiers cascaded by a post amplifier and interconnected
by differential wideband matching networks that presents an
overall enhanced gain bandwidth product. By using the current
mode exponential gain control technique, the proposed design
achieves a broad 30-dB linear-in-decibel gain range, a gain-independent output 1-dB compression point better than 10 dBm,
input/output return loss better than 13 dB, a 0.75-dB gain
flatness over a multi-decade frequency range from 2.5 MHz to
1.17 GHz, a measured in-band group-delay variation of 30 ps, a
35-mW power consumption, and a 0.25-mm core die area.
Index Terms—Bandwidth enhancement technique, commonmode feedback (CMFB), current mode design, dB linearity, dc
offset cancellation (DCOC), digital gain control, digital variable
gain amplifier (DVGA), exponential current converter, interconnect network, linear-in-decibel gain control, linearizer, low power
design, programmable gain amplifier (PGA), SiGe BiCMOS,
variable gain amplifier (VGA).
I. INTRODUCTION
A
PROGRAMMABLE gain amplifier (PGA) is a key RF
frontend block in order to support mobile communication
capability of the wireless transceivers [1]–[14]. The PGA gain
control range determines the receiver input dynamic range that
can provide a regulated stable power level to the baseband section, as shown in Fig. 1(a). The drive for recent RF research is
focusing on high data-rate communication in the gigabit/second
range. Hence, the requirement of the PGA interfacing the baseband section is to provide a regulated stable power level and
Fig. 1. (a) RF frontend to baseband interface. (b) Block diagram of the proposed dB-linear PGA with DCOC.
also to support large bandwidth. As the state-of-the-art, the supported applications as well as the density of system integration of the microwave and the millimeter-wave transceivers are
gradually increasing towards system-on-chip (SoC) solutions
[2]. Additionally to support low power applications, the supply
voltage is also gradually down scaled. This limits the gain and
linearity performance of a single amplifier stage compelling to
move towards the cascaded multiple stage amplifier topology.
The conventional cascaded identical amplifier stages [15] provide the desired high gain, as shown in (1); however, the bandwidth also shrinks as the number of cascaded stages increases
given by (2) as follows:
(1)
(2)
where
and
are the gain and bandwidth of the overall
cascaded amplifier consisting of identical stages with
and
as the gain and bandwidth, respectively.
By sandwiching an all-pass-filter interconnect stage with
a gain peaking network, the bandwidth enhancement can
be achieved, and it was also shown that the bandwidth
enhancement can be achieved by implementing the resistor–inductor–capacitor (RLC) interstage network as a bandpass
network [16]. Initially, the interstage that enhanced the overall
bandwidth of the cascaded stages was implemented by using
peaking inductors in the interstage of wideband transimpedance
amplifiers [17] and also in wideband distributed amplifiers
[18]. This technique was also extended from inductors to
transformers [19], [20]. However, this elegant implementation
consumes more die area and the number of inductors increased
proportional to the number of cascaded stages. The inductive
peaking also affected the gain flatness by introducing ripples, which may also result in system instability. One of the
possibilities with smaller die area is to replace the inductors
with resistor–capacitor (RC) bandpass networks, which was
proposed in [21]. An active interconnect design by using
stagger-tuned amplifier stages based on this technique was
proposed in [22].
In this paper, a thorough design consideration of a PGA
used in a commercially feasible high data-rate RF transceiver
system based on the low-cost, long battery-life, good linearity,
and straightforward baseband interface is studied, proposed,
and developed. The topology and the design aspects of the
proposed PGA sub-blocks, namely the digitally variable gain
amplifier (DVGA) designed by the same authors [23], the
fixed gain post amplifier, along with the differential wideband
interconnect networks are theoretically analyzed and experimentally verified by on-wafer probing. By incorporating the
wideband interconnect network, an overall improved PGA’s
gain-bandwidth product (GBW) is achieved. With two DVGA
stages and a fixed high gain post amplifier, the proposed PGA
becomes a suitable choice for the RF receiver frontend to
interface with the baseband section by providing a nearly
gain-independent output gain compression point over a large
dynamic range. Additionally, the current mode gain control
improves the accuracy of proposed PGA’s dB-linear gain steps
and the current mode biasing limits the rail-to-rail dc current;
hence reducing the overall dc power consumption as compared
to the existing state-of-the-art.
In addition to the work described in [24], the main contributions of this paper include the illustration of its GBW enhancement that is realized by using the RC inter-stage network,
the detailed analysis of the nearly gain-independent output gain
compression point over a large dynamic range, and the detailed
investigation about the switching time, group delay, and high
data rate supported.
This paper is organized as follows. Section II describes the
proposed PGA topology. Section III provides a detailed circuit
analysis of the proposed PGA’s sub-blocks. Section IV provides
experimental results obtained by using on-wafer measurement
to verify the design capabilities. Finally, a conclusion is given
in Section V.
II. DESIGN TOPOLOGY
The proposed dB-linear PGA has a fully differential
three-stage cascaded topology with two identical DVGA cores,
a post fixed gain amplifier stage, and RC parallel interconnect
networks with a symmetric RF signal path, as shown in the
block diagram of Fig. 1(b). The DVGA core is a 6-bit dB-linear
low power digitally controlled 11 to 8-dB variable gain
amplifier (VGA) with on-chip dc offset cancellation (DCOC)
[23]. The corresponding gain control bits
of both the
DVGA cores are shorted in pairs to provide an overall 6-bit
programmable gain control. The post amplifier based on the
similar topology as a DVGA core provides a 16-dB fixed
gain with DCOC.
The sequence of the PGA sub-blocks are carefully chosen
taking into account the RF receiver frontend to baseband
interface requirement of providing a linear regulated power
level over a large receiver dynamic range. This application
requirement in terms of PGA linearity specification translates
into a gain-independent output 1-dB gain compression point
(
) over the entire gain control range and the gain
difference has to be reflected in the input 1-dB compression
point (
). For simplifying the analysis, we assume that
the nonlinearity contribution from the interconnect stages are
negligible and are later verified by the measurement results in
Section IV. The determination of the overall
is not a
straightforward process since the characteristic curve depends
on the amplifying devices moving from linear operation into
saturation. The overall
is dependent on the cascaded
stage with amplifying devices that transits earlier from linear
operation into saturation, and hence, we can estimate the overall
by converting back and forth between the input power
and
values with one stage at a time over the entire
cascaded chain.
The linearity analysis of the proposed PGA topology can be
illustrated from Fig. 2 by neglecting the interstage network.
The DVGA core design has a nearly gain-independent measured
(
12.5 to 11 dBm) for the entire DVGA gain
range denoted as
in Fig. 2(a) and the DVGA core gain difference is mainly reflected in its
as
and
[shown
in Fig. 2(a)]. We consider the
and
points of the
post amplifier as
and
, respectively, for illustration purposes. For the proposed PGA to be used in the RF receiver frontend, the post amplifier design has to ensure that
so
that the overall PGA’s
becomes gain-independent and
will be approximated to
of the post amplifier ( ), as
shown in Fig. 2(d). This will transform and limit the cascaded
DVGA characteristics from Fig. 2(a) to (b).
We perform the linearity analysis of the PGA for both the
maximum and minimum gain conditions as follows.
A. PGA Maximum Gain (B5~B0: 111111’b)
From the post amplifier transfer characteristics shown in
Fig. 2(c), the
of the overall PGA is determined by the
of the fixed gain post amplifier,
with its
value,
determining the maximum output power level that
the cascaded DVGA core can reach before the post amplifier
goes into saturation. By traversing back in the PGA chain, the
characteristics of the cascaded DVGA core shown in Fig. 2(b)
is limited by
with the overall PGA’s
set to
shown in Fig. 2(d).
Fig. 2. Linearity analysis of the proposed PGA suitable for receiver frontend to baseband interface.
B. PGA Minimum Gain (B5~B0: 000000’b)
From the cascaded DVGA core’s transfer characteristics
shown in Fig. 2(a) and (b), by ensuring that
, eventually the overall PGA
is determined by
of the
fixed gain post amplifier ( ) as in the previous condition and
the overall PGA’s
set to
, as shown in Fig. 2(d).
Hence, by ensuring
, the overall PGA’s nonlinearity, within the PGA gain control range, is reached due to
the early saturation of the post amplifier while the DVGA core
stages are still operating linearly.
In Section III, a detailed circuit analysis and design considerations for each of the PGA sub-blocks are discussed.
III. CIRCUIT DESIGN DESCRIPTION
The circuit schematics of the DVGA core and the post
amplifier that are used in the proposed PGA design have
different current biasing circuit (
), as shown in Fig. 3.
The schematic of either the DVGA core or the post amplifier
consists of three fully differential stages that are biased using
current mirrors (
) from a bandgap reference to obtain a
low power design. The intermediate stage is the core common
emitter (CE) amplifier stage (
) with a feed-forward DCOC
and its gain is determined by the
current source. The
input stage (
) with the transimpedance load (
) and
the output stage (
) are responsible for providing a differential wideband 100- impedance matching with fixed
common-mode dc voltages that are independent of the PGA
gain control [24].
A. DVGA Core and Digital Gain Control
For the DVGA core, the
current source consists of an
n-channel metal–oxide semiconductor (nMOS) transistor based
digital-to-analog current converter (
(
to ) to
),
and a bipolar junction transistor (BJT) based exponential current
converter (
to
) that is designed to provide a precise
linear-in-decibel gain control, as shown in the Fig. 3, from 11
to 8 dB.
The dB-linear gain of the DVGA core based on the digital
gain control
(
to ) is given as
dB
(3)
where
is the resistance used in the exponential current converter,
is the thermal voltage of the amplifying bipolar tranto ) are the constant coefficients
sistor pair
,
(
of the binary weighted estimation of the linear gain function,
(
to ) is the 6-bit digital gain control received from
is the dc current corresponding to
the digital baseband, and
are reset (“0”).
minimum gain when all digital control bits
B. Fixed High Gain Post Amplifier
The post fixed gain amplifier has a fixed current source
(
) providing a measured gain of 16 dB. The post amplifier presents a high
over the entire PGA gain tunable
range to meet the 150-mVpp signal level requirement from
the baseband. To verify the bandwidth enhancement by the
gain peaking technique, the post amplifier circuit along with
the parallel RC interstage network at the input is separately
measured by on-wafer probing. The measurement results are
discussed in Section IV to highlight the benefits of the proposed
interstage network such as the gain peaking response for the
bandwidth enhancement without affecting the wideband differential matching to 100- impedance and the
linearity
performance.
C. Interconnect Network Stage and Bandwidth Enhancement
The matching network is a crucial circuit that provides a good
impedance matching with low loss for cascading any two adjacent stages. In this proposed PGA design, the interstage RC
parallel network in Fig. 4(a) is used to interface between the
DVGA core stages as well as with the post amplifier stage. The
circuit operation of the interconnect network can be understood
by following the sequence indicated in Fig. 4(b).
1) At very low frequencies close to dc ( 0 Hz), the capacitor
acts as an open-circuit or a high-impedance shunt path,
Fig. 3. Circuit schematic of the dB-linear DVGA core and post amplifier.
Fig. 5. Frequency response of cascaded stages: (a) without and (b) with bandwidth enhancement interstage.
Fig. 4. (a) Interconnect stage and (b) circuit frequency response.
and hence the interstage network operates as a voltage divider leading to an RF signal loss shown in the Fig. 4(b).
2) As the frequency of operation increases, the impedance
offered by the capacitor decreases and a shunt RC network
introduces a zero at
frequency.
3) With further increase in frequency, the impedance of capacitor drops below the resistance , and depending on
the capacitor value, the network acts as a short circuit with
low signal loss beyond
frequency.
4) From
frequency onwards, the high-frequency parasitic
resistance
due to the skin effect of the metal traces
appears and results in a high-frequency pole.
This resulting frequency response shown in Fig. 4(b) is similar to a gain peaking response characteristics and the network
transfer function is given as
(4)
TABLE I
SUMMARY OF MEASURED PERFORMANCE OF THE PROPOSED PGA AGAINST SUB BLOCKS (DVGA CORE AND POST AMPLIFIER)
As discussed in Section I, from (1) and (2), a GBW improvement is key for the proposed PGA design operating with a large
gain control range in order to support the receiver’s dynamic
range, as well as a wide bandwidth to support high data rate.
To provide the improvement in the GBW, the cascaded amplifier stages of the proposed PGA provides the gain enhancement while the interconnect RC parallel network provides the
bandwidth enhancement. The bandwidth enhancement is obtained by the introduced zero at
frequency due to the interconnect stage (gain peaking) at high frequency cancels the
dominant pole of the amplifier stage that limits the upper cutoff
frequency of overall PGA bandwidth [22]. This is indicated by
Fig. 5(a) and (b). This technique is similar to the amplifier gain
predistortion technique in which the bandwidth is first enhanced
by using the gain peaking parallel RC interstage network before
cascading with the next amplifier stage. Thus, the overall PGA
bandwidth closer to the bandwidth of the DVGA core (which
is the bandwidth limiting stage) is achieved. This technique ensures that the gain is not affected much and also the overall cascaded bandwidth does not shrink, unlike the scenario shown in
Fig. 5(a) based on (2). This improves the overall PGA’s GBW
product, which is desirable in the receiver frontend.
This bandwidth enhancement technique provides an easy interface option for cascading several such DVGA core and post
amplifier stages with very low effect on the gain, matching, linearity, and interface dc performance. This technique is also validated by the measurement results shown in Table I.
Additionally the parallel RC interconnect stage provides a dc
coupling with an additional voltage drop that depends on the
biasing conditions of the output of the previous and input of
the next stage unlike the interconnect peaking inductors with
small voltage drop (determined by the inductor -factor) across
it. Thus, overcoming the loading effect that may also reduce
the bandwidth [17] and each stage can be optimized to have
different dc voltages.
To evaluate this analysis, a plot of simulated PGA’s output
power against the input power at 1-GHz frequency is shown in
Fig. 6. From the plot we find that the overall PGA’s
is
almost gain-independent (
7.1 dBm) for the proposed design. For the curves closer to the minimum gain condition, the
degradation of the PGA’s
is due to saturation of the
DVGA core in addition to the already saturated post amplifier.
This can be accounted for the condition that
(see Fig. 2) and is verified by observing the
performance
in Table I that summarize the performance of the proposed PGA
Fig. 6. Simulated
linearity plot of the proposed PGA design for the 64
gain steps at 1-GHz frequency.
against the sub-blocks, namely, the DVGA core and the post amplifier.
The proposed interstage RC network, consisting of a parallel resistor and a frequency-sensitive capacitor, is a cascaded
network which is external to the PGA’s sub-block amplifiers
(DVGA core and post amplifier). Hence, the RC interstage network does not form a part of the sub-block amplifiers’ feedback
loop and do not affect the stability criteria of the overall cascaded amplifier chain.
The component values of the interstage network ( and )
are to be carefully selected and a design guideline is provided
based on design tradeoffs among the performance parameters of
the overall proposed PGA design.
Factors Affected by the Resistor :
• The gain peaking and the resulting GBW enhancement is
achieved by choosing a smaller
(zero frequency) and
positioning it within the PGA’s passband
(5)
• Meanwhile, the group-delay variation increases as the gain
peaking is increased. In the proposed design, group-delay
variation is compromised by the GBW enhancement and a
detailed analysis is provided in Section IV.
• The resistor is along the RF signal path and consequently
a large value of increases the signal loss
Loss
(6)
• The interconnect RC network has very small influence on
the overall PGA’s input/output reflection coefficient. This
is mainly due to the input fixed gain stage of the first stage
DVGA core and output buffer stage of the post amplifier.
Hence, a small value of is preferred and the designed value
is chosen as 45 , which along with the shunt capacitor provides the GBW enhancement as well as mitigates the discussed
overall PGA’s performance degradations.
Factors Affected by the Capacitor :
• As a product with a small resistor , the capacitor
mainly determines the GBW enhancement based on (5).
• The
, which is frequency-dependent resistive loss due
to the skin effect, is determined by the quality factor of
and can be reduced by proper layout techniques such as
using short low-loss thick metal interconnect traces.
• The overall PGA’s upper cutoff pole frequency
increases as is decreased,
Fig. 7. Die microphotograph of post amplifier with interstage network at input
and bandgap reference for on-wafer measurement.
(7)
• A smaller
results in a reduced physical layout size
based on the capacitance of the parallel plate metal–insulator–metal (MIM) capacitor, which is given as
(8)
Hence, a small value of is also preferred. However, to meet
the desired gain peaking requirement based on (5) with reduced
effect on the overall PGA’s performance by a small resistor ,
the designed value is chosen as 5 pF.
D. Current Mode Gain Control With Improved Accuracy
The proposed variable gain control circuit shown in Fig. 3
provides a large PGA gain range with improved accuracy. This
accuracy is achieved by using long-channel nMOS transistors
in the cascode current mirrors with the digital nMOS switches
(
) stacked above the binary weighted nMOS current
mirrors, as shown in the DVGA core’s
block of Fig. 3.
By using the current mode gain control, the width and length
of the layout traces from the gain control block to the DVGA
stages as well as from the bandgap reference do not affect the
current flow. Hence, a fully differential topology with a symmetric layout and reduced dc offsets in the RF portion can be
drawn with the digital gain control portion placed at a distance
from the RF traces.
IV. EXPERIMENTAL RESULTS
The proposed post amplifier design with input interstage network and the overall proposed dB-linear PGA with DCOC design are realized by using a 0.18- m SiGe BiCMOS process
from Tower Jazz Semiconductors Inc., Newport Beach, CA,
USA. The microphotograph of the post amplifier with an input
interstage network and a standard bandgap reference is shown
Fig. 8. Die microphotograph of proposed PGA with bandgap reference.
in Fig. 7 and the microphotograph of the proposed PGA along
with the bandgap reference is shown in Fig. 8, which occupies a
core die area of 810 m 310 m excluding the measurement
probing pads. The PGA and the post amplifier performance are
experimentally verified by on-wafer probing by using the Agilent E8364B PNA network analyzer, RoHS SMBV 100A signal
generator, LeCroy Waverunner 6000A series high-speed oscilloscope, and Agilent E4407B ESA-E series spectrum analyzer.
A. Post Amplifier Design With Input RC Parallel Interstage
To verify the performance of the post fixed gain amplifier
used in the proposed PGA and also to validate the bandwidth
Fig. 9. Measured -parameters plot of the post amplifier with input interstage
used in the proposed PGA design.
Fig. 11. Measured PGA -parameters over the 64 gain steps.
Fig. 10. Measured
linearity plot of the post amplifier with input interstage used in the proposed PGA design at 1-GHz frequency.
enhancement achieved by using the interstage network, a standalone testable device-under-test (DUT), as shown in Fig. 7,
is measured by on-wafer probing. The measured -parameter
shown in Fig. 9 suggest that the interstage network does not
affect the input matching significantly and the return loss better
than 13 dB is achieved over the entire frequency range. The
gain plot in Fig. 9 suggests that there is gain peaking of less
than 1 dB observed at about 1-GHz frequency that increases
the bandwidth of the overall cascaded interstage and the post
amplifier to 2.45 GHz, as discussed in Fig. 5(b). Based on the
plot at 1 GHz frequency (Fig. 10), the post amplifier
can achieve
of 7.1 dBm and
of 22 dBm
consuming 9.8-mW dc power from a 1.8-V supply voltage.
B. Proposed PGA Design With Bandgap Reference
The overall PGA design shown in Fig. 8 consumes a dc current from 18 to 19.6 mA corresponding to gain variation from
minimum to maximum PGA gain, and during the power-down
mode it dissipates a dc current of 915 A from a single supply
voltage of 1.8 V.
The measured differential -parameters of the proposed PGA
against frequency for all 64 gain steps is shown in Fig. 11. The
plot suggests that the proposed design has almost gain-independent input/output matching, reverse isolation, gain flatness, and
3-dB bandwidth. The plot shows a uniform step size for the
gain emphasizing the dB-linear accuracy achieved in the proposed PGA design.
The
linearity measurement was performed under
maximum, mid, and minimum PGA gain conditions shown
in Fig. 12 and the results agrees well with the simulation
results shown in Fig. 6. The
degradation from 7.5 to
10 dBm is also observed for the minimum gain condition.
For low-power transceiver designs operating in the time division multiplexing scheme, the proposed PGA can be switched
to a low power mode (consuming leakage current of 910 A)
using the power down digital pin shown in the microphotograph
(Fig. 8). The turn ON and turn OFF time of the proposed PGA
has a significant contribution in determining the frequency of
switching the transceiver between transmitter and receiver. By
using a high-speed oscilloscope, a low-frequency square-wave
input to the power down pin and a single-ended sinewave input
of 1-GHz frequency, the turn ON and OFF times of the proposed
PGA are measured and the results are shown in Fig. 13. The
proposed PGA has 1.5- s turn ON (
V) time and
116 ns turn OFF (
V) time.
The measured low-frequency gain plot (Fig. 14) using a
signal generator and a spectrum analyzer shows a lower PGA
cutoff frequency of 3 MHz for both maximum and minimum
gain conditions and is mainly due to the DCOC HPF incorporated in each DVGA core and the post amplifier stages.
The measured group delay, as shown in Fig. 15 of the
proposed PGA, over the 64 gain steps, has a variation less
than 30 ps. While pulse-pattern [pseudorandom bit sequence
Fig. 14. Measured low-frequency gain plot for maximum and minimum PGA
gain condition.
Fig. 12. Measured
PGA gain at 1 GHz.
linearity plots for maximum, mid, and minimum
Fig. 15. Measured group delay of proposed PGA over the 64 gain steps.
Fig. 13. Measured PGA switching time based on the single-ended output
against the power down (PwrDwn/PD) digital input. (a) Turn ON ( 1.52 s)
and (b) Turn OFF ( 116 ns).
(PRBS)] generator equipment is currently unavailable in our
measurement laboratory facility, an eye diagram is extracted
from the measured amplifier -parameter data file using Agilent’s Advanced Design Systems 2009 (ADS 2009) EDA
software [22] for 1 and 2 Gb/s, as shown in Fig. 16.
From Fig. 15, the measured maximum variation of the group
delay for each gain step is more than 100 ps and it is due to
the group-delay peaking observed closer to the amplifier’s passband corner frequency. This group-delay variation can be mitigated by choosing suitable component values of the interstage
network at the expense of sacrificing the enhanced bandwidth
due to gain peaking. This can be shown by the simulation plot
(Fig. 17) of the proposed PGA’s gain and the group delay in frequency domain against the variation of the resistance ( ) used
in the interstage matching network from 20 to 50 (designed
value is 45 ). Hence, from Fig. 17, we can choose a suitable
value that compromises between the two conflicting design
tradeoffs, namely, the bandwidth and the group-delay variation
[19], [22].
The measured PGA gain characteristics against the digital
gain control code suggests an improved dB-linearity and also
the variation of noise figure, as shown in Fig. 18. The noisefigure performance is not very critical for the proposed PGA and
Fig. 18. Measured dB-linear gain and noise-figure characteristics at 1-GHz frequency of the proposed PGA.
Fig. 16. Extracted output differential eye diagrams from measured -parameter data of the proposed PGA for: (a) 1-Gb/s 2
1 PRBS input and (b) 2-Gb/s
PRBS input.
Fig. 17. Simulated gain and group-delay plots for maximum PGA gain against
the variation of the interstage matching networks’ resistance.
more design emphasis is on gain control range, output power
level, and linearity performance.
C. Performance Summary of the Proposed PGA Against Its
Sub-Blocks—DVGA Core and Post Amplifier
The proposed PGA is comprised of two cascaded DVGA core
stages and a post fixed gain amplifier that are interconnected by
using a parallel RC interstage network. Table I summarizes the
measured performance of the DVGA core, the post amplifier
with the input interstage, the actual measured performance of
the proposed PGA, and the estimated results based on the measured performance of the PGA’s sub-blocks. Based on this consolidated information, we can clearly observe the following.
1) A bandwidth enhancement is observed for the post amplifier as compared to the DVGA core due to the gain peaking
of the cascaded input interstage network included in the
DUT (Fig. 7).
2) A bandwidth enhancement in the actual proposed PGA performance when compared to the estimated performance
based on (2). Also the degradation of the actual gain based
on the gain estimation of the cascaded DVGA core stages
and the post amplifier measured gain based on (1) is about
1.4 dB, which can be accounted for the interconnect losses.
Hence, an overall GBW product improvement is observed
in the proposed PGA design along with a bandwidth of
1.7 GHz, which is closer to the 1.9-GHz bandwidth of the
DVGA core sub-block.
3) The
of the proposed PGA ( 7.5 dBm) is closer to
the post amplifier’s
measured result ( 7.1 dBm)
with the PGA’s gain difference reflected in its
(from 9 to 36 dBm), which is also the dynamic range.
Hence, the proposed PGA with the two cascaded DVGA
cores, post amplifier, and the interstage network has a small
gain and
degradation with a bandwidth enhancement
resulting in the overall GBW product improvement as compared to the conventional cascaded amplifier stages.
D. Performance Comparison With Existing State-of-the-Art
The overall performance of the proposed PGA is compared
with the existing state-of-the-art designs with comparable gain
control range in Table II. The works in [7], [11], [25], and [26]
operate in the voltage mode for biasing and gain control as compared to the proposed PGA design that uses current mode exponential gain control to enhance the accuracy of the dB-linear
performance and current mode biasing that reduces the overall
TABLE II
SUMMARY OF STATE-OF-THE-ART VGA WITH WIDE GAIN TUNABLE RANGE
dc power consumption by limiting the maximum rail-to-rail current to 19.4 mA from a 1.8-V supply. The work in [25], implemented in an advanced process technology with reduced power
supply voltage handling capability, has comparable gain range
and die area. However, the high output linearity in [25] comes
with an overhead of higher power consumption as compared to
the proposed work. Though the work in [23] has improved gain
control linearity (which is the same DVGA core sub-block design used in the proposed PGA) as compared to works in [7],
[11], and [26], the proposed PGA achieves better
linearity performance over a larger gain control range, which can
be observed from the small variation in the output voltage swing
over the complete gain control range. The dc power consumption and the die area in [11] and [26] and are less than the proposed design. However, for the purpose of measurement, an additional output buffer is necessary in the designs [11], [26]. Unlike the analog VGA [7], [11], the proposed PGA can be directly
interfaced with the digital baseband without the need for an additional digital-to-analog converter (DAC).
V. CONCLUSION
This paper has presented the design of a 6-bit PGA with a
large gain control range and a post fixed gain amplifier, which
is used as a sub-block in the proposed PGA. Both the designs are
fabricated in a 0.18- m SiGe BiCMOS process and measured
by using on-wafer probing. The proposed PGA design, without
significantly increasing the circuit complexity, simultaneously
achieves an enhanced GBW product and a better
linearity performance with a large dynamic range, which are desirable characteristics for the integration in the receiver RF frontend of low-cost low-power consumer applications requiring
good gain control precision.
ACKNOWLEDGMENT
The authors would like to take this opportunity to thank
Tower Jazz Semiconductors Inc., Newport Beach, CA, USA,
for providing the fabrication service of the design. The authors
would also like to thank L. W. Meng, Nanyang Technological
University, Singapore, for assisting in the on-wafer measurement of the design.
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Thangarasu Bharatha Kumar (S’12) received
the Bachelor of Engineering degree in electronics
and communication from the Ratreeya Vidyalaya
College of Engineering (RVCE) [affiliated with
Visvesvaraya Technological University (VTU)],
Bangalore, India, in 2002, the M.Sc. degree in
integrated circuit design from the German Institute
of Science and Technology, Singapore (a joint
degree program offered by Nanyang Technological
University (NTU), Singapore and Technische Universitaet Munchen (TUM), Germany), in 2010, and
is currently working toward the Ph.D. degree at NTU.
Since 2010, he has been a Research Associate with VIRTUS, Integrated
Circuit (IC) Design Centre for Excellence, Nanyang Technological University
(NTU). His research interests include RF and millimeter-wave integrated-circuit design and reconfigurable high-frequency amplifier design.
Kaixue Ma (M’05–SM’09) received the B.E. and
M.E. degrees from Northwestern Polytechnological
University (NWPU), Xi’an, China, and the Ph.D.
degree from Nanyang Technological University
(NTU), Singapore.
From August 1997 to December 2002, he was
with the China Academy of Space Technology,
Xi’an, China, where he became Group Leader
of the Millimeter-Wave Group for Space-Borne
Microwave and Millimeter-Wave Components And
Subsystem in Satellite Payload and VSAT Ground
Station. From September 2005 to September 2007, he was with MEDs Tech-
nologies, as a Research and Development Manager. From September 2007
to March 2010, he was with ST Electronics (Satcom & Sensor Systems) as
a Research and Development Manager, Project Leader, and a member of the
Technique Management Committee of ST Electronics. Since March 2010,
he has been with NTU, as a Senior Research Fellow and Millimeter-Wave
RFIC Team Leader for the 60-GHz Flagship Chipset Project. As a Principal
Investigator (PI)/Technique Leader, he has been involved with projects with
funds in excess of S$12 Million (excluding projects done in China). He has
authored/coauthored over 100 referable international journal and conference
papers. He is reviewer of several international journals. He has filed ten patents.
His research interests include satellite communication, software-defined radio,
and microwave/millimeter-wave circuits and systems using CMOS, microelectromechanical systems (MEMS), monolithic microwave integrated circuits
(MMICs), and low-temperature co-fired ceramic (LTCC).
Dr. Ma was the recipient of Best Paper Awards of IEEE SOCC2011, the IEEK
SOC Design Group Award, the Excellent Paper Award of the International Conference on HSCD2010, and the Chip Design Competition Bronze Award of
ISIC2011.
Kiat Seng Yeo (M’00–SM’09) received the
B.Eng. and Ph.D. degrees in electrical engineering
from Nanyang Technological University (NTU),
Nanyang, Singapore, in 1993 and 1996, respectively.
He is currently the Associate Provost (International Relations and Graduate Studies) with the
Singapore University of Technology and Design
(SUTD), Singpore. He is a widely known authority
in low-power RF/millimeter-wave integrated circuit
(IC) design and a recognized expert in CMOS
technology. He has secured over S$30M of research
funding from various funding agencies and industry over the last three years.
Before his new appointment with SUTD, he was Associate Chair (Research),
Head of Division of Circuits and Systems, and Founding Director of VIRTUS,
School of Electrical and Electronic Engineering, NTU. He has authored or
coauthored 6 books, 5 book chapters, and approximately 500 international
top-tier refereed journal and conference papers. He holds 35 patents.
Dr. Yeo is a member of the Board of Advisors of the Singapore Semiconductor Industry Association. He has served on the Editorial Board of the IEEE
TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He holds or has
held key positions in many international conferences as advisor, general chair,
co-general chair, and technical chair. He was the recipient of the Public Administration Medal (Bronze) on National Day 2009 by the President of the Republic
of Singapore and the Distinguished Nanyang Alumni Award in 2009 for his outstanding contributions to the university and society.
Wanlan Yang was born in Anhui Province, China,
in 1969. She received the B.Eng. degree from the
Harbin Institute of Technology, Harbin, China, in
1990, and the M.Sc. degree in integrated circuit
design from the German Institute of Science and
Technology-TUM Asia, Singapore, in 2011.
Since 2011, she has been a Research Associate
with VIRTUS, Integrated Circuit (IC) Design Centre
for Excellence, Nanyang Technological University
(NTU), Singapore. Her research interests include
SPICE compact model, SPICE modeling, on-wafer
measurements, millimeter-wave antenna design, and RF integrated-circuit
design.