1. technology and computing

IM4A.2.pdf
Advanced Photonics Congress © 2012 OSA
Photonic Integration in State-of-the-Art
Silicon Electronics Processes
Jason S. Orcutt
Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, Massachusetts 02139
Email: [email protected]
Abstract: Photonic integration within state-of-the-art CMOS and DRAM processes leverages the
existing electronic manufacturing infrastructure to minimize cost. Suitable design techniques
combined with in-foundry optimization or post-processing have enabled integration within several
advanced technologies.
!2012 Optical Society of America
OCIS codes: (250.5300) Photonic integrated circuits; (200.4650) Optical interconnects
1. Introduction
Although the majority of silicon photonic research is motivated by end applications where photonic devices could be
integrated alongside millions of transistors in a CMOS process, most research devices are fabricated in independent
photonics-only process flows. Free from the constraints of working within an existing process, fabrication steps and
layer geometries have been tailored to optimize the performance of individual devices. The short flow methodology
has enabled pioneering device research and proof-of-concept demonstrations by many academic and industrial
groups [1, 2]. The rapid progress in this work helped to lay the groundwork for the demonstration of a complete
electronic-photonic integrated circuit (EPIC) platform by modifying a 130 nm SOI-CMOS platform to accommodate
the required fabrication steps [3]. Today, however, prominent EPIC applications from multiprocessor interconnect
[4] to coherent-communication receivers [5] require photonic devices to be integrated alongside the dense, highperformance transistors only available within state-of-the-art electronic processes. The cost and barrier-to-entry of
drastically modifying these processes in a similar manner is too large to be practical for most applications. Instead,
we have demonstrated design and data preparation techniques [6-8], post-fabrication processing steps [7-9] and infoundry process optimizations [10] that enables photonic integration efforts to leverage the existing infrastructure.
Fig. 1. Monolithic electronic-photonic integration was demonstrated in the Texas Instruments 28 nm bulk-CMOS process
in which the (a) fabricated wafer consisted of a (b) multi-project stepped field including (c) our test die [8].
IM4A.2.pdf
Advanced Photonics Congress © 2012 OSA
Fig. 2. (a) Second-order ring resonator filter bank integrated in the 28nm bulk-CMOS process with 10 !m ring radii. (b)
Measured transmission function without the use of thermal tuning to match ring resonance frequencies. (c) Comparison of
measured and resonator characteristics used to extract resonant frequency and lithographic matching estimates [8].
2. Foundry CMOS Integration
To integrate with state-of-the-art CMOS processes, no in-foundry process modifications are permitted within the
standard foundry process model. This requirement is due to the fact that the integrated electronic-photonic design is
fabricated as part of a shared mask set that undergoes the standard wafer level processes of the existing electronics
as shown in Fig. 1. Since the front-end single-crystalline silicon or polysilicon layers that are leveraged to fabricate
the photonic devices are within 500 nm of the silicon handle substrate in these processes, either local removal of the
substrate or substrate transfer is required to provide sufficient low-index undercladding to the integrated waveguides
[8-9]. Integrated devices such as waveguides and ring resonator filters shown in Fig. 2(a) have been demonstrated
with zero in-foundry process changes using the existing electronic VLSI design submission data flows and masksharing infrastructure [8]. The measured ring transmission measurements were then fit to a transmission-matrix
model as shown in Fig. 2(c) to estimate the lithographic performance enabled by fabrication within the advanced
CMOS process. The advanced 1.35 numeric aperture, ArF 193 nm CMOS lithography was observed to enable an
average lithographic linewidth matching of 0.8 nm, which enables the high-performance fabrication of sensitive
nanophotonic devices [8].
3. DRAM Integration
Although high performance CMOS logic processes are fabricated on both silicon-on-insulator and bulk silicon
wafers, high-volume memory products such as DRAM are commercially produced only on bulk silicon wafers. This
constraint forbids the integration of standard single-crystalline silicon waveguides that have been previously
demonstrated to provide low loss. Instead, deposited silicon waveguides suitable for integration within DRAM
Fig. 3. (a) Cross section of the fabricated waveguide with the full dielectric cladding environment of the memory process.
(b) End-of-line propagation loss measurements as a function of waveguide width and test wavelength [10].
IM4A.2.pdf
Advanced Photonics Congress © 2012 OSA
memory processes to enable photonic interconnect from processors to memory within future computation systems
are being actively developed [10, 11]. Polycrystalline silicon waveguides are desirable in this role as propagation
losses below 10 dB/cm are achievable [12, 13] using materials already common in such processes. However,
previous demonstrations of low-loss poly-Si waveguides have utilized layer thicknesses of 200 nm or greater and
reduced index-contrast oxynitride claddings to achieve such results. Further, the low-loss performance was not
verified to withstand the high-temperature steps present in electronics processes. To address this need we developed
thin poly-Si waveguides fabricated in a complete 300 mm wafer process representative of state-of-the-art memory
processes with end-of-line waveguide losses below 10 dB/cm for the first time [10]. The waveguide core was first
deposited at low-temperature by LPCVD to form an amorphous film. Next, it was crystallized to form poly-Si with a
~950 !C anneal for 20 seconds in a nitrogen atmosphere. Since the shallow trench isolation that formed the
waveguide lower cladding was not sufficiently thick to isolate the optical mode from the substrate, die-level
substrate removal was performed in an academic cleanroom for this study. The end-of-line waveguide cross section
and resulting waveguide loss is shown in Fig. 3. The process was split between wafers that did or did not undergo
the thermal processing representative of the full electronics process. Although a ~30% increase in propagation loss
was observed during thermal processing, the waveguides that corresponded to the full process were measured to
have a loss that scaled with a 5.1 cm-1 polysilicon material loss [10]. The narrow waveguides, which have a
confinement factor of approximately 0.3, therefore enable long-distance, on-chip routing with 6.2 dB/cm loss [10].
4. Conclusions
Monolithic photonic integration platforms that leverage existing electronic manufacturing infrastructure provide
low-cost access to fabricate high-performance photonic devices alongside state-of-the-art CMOS transistors. The
target system application is primarily to integrate energy efficient and bandwidth dense photonic interconnect within
memory and microprocessor chips for future compute systems. The general-purpose nature of these foundry
platforms may further enable research into novel electro-optic systems-on-chip across the entire spectrum of VLSI
and photonic systems and applications.
5. Acknowledgments
The monolithic CMOS photonic integration effort referenced in this summary was funded in part by DARPA. The
work was performed under the direction of Profs. R. J. Ram and V. Stojanovi" at MIT. The author acknowledges the
contributions of M. A. Popovi" (University of Colorado at Boulder) and MIT collaborators A. Khilo, H. Li, J. Sun,
C. W. Holzwarth, B. Moss, M. Georgas, J. Leu and C. Sun to this work. Fabrication assistance was provided by T.
Bonifield and R. Hollingsworth of Texas Instruments as well as S. Tang and S. Kramer of Micron Technology.
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