Pulsic Limited Made-‐for-‐Analog Design Automation The Time Has Come ____________________
White Paper Mark Williams Co-‐Founder Pulsic
A Brief History of Analog Design Automation Since its inception, most of the efforts and great achievements of the electronic design automation (EDA) industry have been focused on the issues confronting designers of large-‐scale, standard-‐cell, digital integrated circuits (ICs). Quality of results (QOR) has always been important to the adoption of any automated solution, and in the context of digital design, quality has been measured in the relationship to gross design specifications such as critical-‐path speed, total area, and power consumption. For such digital designs, this is entirely appropriate. However, these same measures of quality do not translate directly to analog design. For analog designs, subtle differences in circuit topology can make a big difference in the performance of the finished circuit. For analog designs, the “smallest” or the “fastest” or the “lowest power” solution may not always be the “best” solution; the best solution is usually a carefully crafted circuit that takes into account not only these gross measures of quality but also complex constraints and topologies. Not surprisingly, when the EDA industry has previously offered “analog” design tools based on modified digital-‐design tools, many (if not most) analog designers have deemed the QOR produced to be insufficient. Subsequently, the typical analog design flow in use today is much the same as that used 20 years ago, with endless cycles from schematic through manual placement, manual routing, verification, and simulation. While there have been some useful point-‐tools introduced into the manual flow over time (e.g., better schematic editing capabilities, MODGENs for certain constructs, etc.), attempts at a truly automated design flow for analog designs have been largely unsuccessful. The bottom-‐line test for analog design automation is simple: can a skilled analog designer create a better circuit by hand in less time than it takes to use the automated flow (and the subsequent manual modifications to make the result acceptable)? Unfortunately, until now, the answer has been “yes.” The Turning Tide for Analog Design Automation Digital design automation was adopted widely with the introduction of sea-‐of-‐gates process technologies that enabled circuits comprising then-‐unheard-‐of tens of thousands of logic gates. Drawing such a circuit by hand was simply not feasible. Today, analog design has begun to encounter a set of technological advances that similarly challenge the practicality of manual analog design. The mobile communications market has become a major driving force for leading analog process technologies. This force is driving analog designs from 40nm to 28nm/20nm and now to 16nm/14nm processes and below, where companies can reap the benefits of new FinFET technologies, such as higher-‐gain circuits and lower power consumption. These processes will also require analog designers to juggle so many additional rules and constraints that designing in the usual way will become impossible. Already, the FinFET revolution is being acknowledged as a sea change in transistor-‐level design (for digital transistor-‐level circuits as well as analog). What is required is a sea change in the way these designs are implemented. With the FinFET age upon us, analog design automation is not just needed – it’s mandatory. However, what is required is a truly made-‐for-‐analog solution that not only supports all the latest rules and constraints (including those for FinFET), but also addresses all the drawbacks of previous attempts at automation. Why “Modified Digital” Doesn’t Work The goal of digital design automation flows is to find acceptable engineering solutions for the placement and routing of standard cells on a huge scale. Acceptability is generally defined in terms of critical-‐path speed, total area, and/or total power consumption and of course DRC/LVS. The approach taken by previous attempts at analog design automation – modifying made-‐for-‐
digital tools to “fit” analog design – has proved a failure because analog design has fundamentally different requirements. QOR for analog designs is determined on a cell-‐by-‐cell basis, often with several more metrics coming into play than the speed/area/power matrix used for standard-‐cell digital design. The analog design flow is also different from standard-‐cell digital design where a placement-‐
then-‐routing approach makes sense. However, to achieve optimal layout results for an analog circuit, the skilled analog designer needs to consider placement and routing simultaneously. This is a painstaking process that can consume up to 20% of the entire design cycle time. For digital designs, constraints can be set on a global or block-‐by-‐block basis. An analog circuit designer, however, might set constraints on each cell. Before layout, the circuit designer must hand off these complex constraints to the layout engineer, who must then manage these constraints as part of the layout process. Constraints-‐handling has been one of the weakest points for previous attempts at automating the analog design process; many “solutions” have featured constraints entry and hand-‐off systems that were so unwieldy that the manual “system” of Post-‐It Notes used by many teams to keep track of constraints was faster and easier to manage! For these reasons, the bottom-‐line evaluation criteria for any analog design automation solution – can we create a circuit as good or better in less time by hand? – has usually resulted in the design team sticking with a mostly manual flow. But now, automation is becoming an imperative. Analog design, particularly in the FinFET age, has become too complex for manual methods to succeed within targeted design cycle times. Advanced process technologies are more impacted by electrical issues such as layout-‐dependent effects (LDE), electro-‐migration (EM), voltage (IR) drop and noise coupling. Using PCells/PyCells in layouts without extracted parasitics is increasingly inaccurate, and so the wait for a high-‐
quality initial manual layout slows the entire design flow considerably. How Would a Made-‐for-‐Analog Solution Work? The most important measure for an analog design automation solution is QOR: it must produce manual-‐quality results (or as near as), in less time than hand design. Beyond this bottom-‐line, though, there are several other important factors for success. A successful made-‐for-‐analog solution should be easy and intuitive for an analog designer to use; it should “think” like an analog designer. Such a solution would need to read in industry-‐
standard schematic formats. Constraints-‐handling should be as streamlined as possible, ideally, the system would be able to derive constraints automatically from the circuit topology (as physical constraints may only exist in Post-‐It form if at all). In order to create manual-‐quality layout, placement and routing would have to be considered simultaneously. The constraints and layout would need to be editable by the layout engineer at each and every stage of the process. Finally, the resulting layout should be electrically correct and DRC/LVS clean – by construction, if possible. One key to making design automation pay dividends for analog design would be to accelerate the process of getting to an initial layout, as this is by far the most time-‐consuming part of the analog design process (see Figure 1). Not only would this shorten the design cycle, but also would afford analog design teams more time in which to explore alternative architectures – often an unaffordable luxury for analog teams using a manual layout process. Figure 1: Traditional analog layout timeline PolyMorphic Layout: New Approach to Analog Design Automation As outlined above, digital design automation flows take a place-‐then-‐route approach when it comes to the physical layout phase of the flow, leveraging automation technologies for both to greatly enhance both speed and accuracy. Previous attempts at analog design automation have adopted the same approach whereby they have tried to apply modified versions of digital design tools to these specific parts of the traditional analog flow (Figure 2). Figure 2: Traditional “Analog” Design Flows To address the need for a truly made-‐for-‐analog solution, a group of analog-‐design-‐automation specialists at Pulsic has developed a new approach called PolyMorphic Layout. In contrast to current analog solutions, that place and then route, the PolyMorphic Layout approach uses brand new, concurrent, multi-‐threaded automation technologies that consider all aspects of analog layout at once, just as an analog designer does during traditional manual layout. This approach creates DRC/LVS-‐clean layouts with QOR equal to, or better than, those a skilled analog designer could create by hand, but with full automation speed. Pulsic has incorporated its PolyMorphic Layout technology into Animate, a new made-‐for-‐analog layout automation solution (Figure 3). Animate reads the circuit description directly from an OpenAccess schematic, along with any electrical constraints and a subset of the technology/process information (those that may impact on possible layout topologies). The superimposition phase then uses the unique PolyMorphic Layout engine to generate literally thousands and thousands of abstract topological solutions, where many of these abstract solutions are discarded very early due to failure to meet various measures of quality. Once the superimposition engine has generated a quantum database of such solutions, these, along with the full detailed technology/process information, are fed through the realization engine to produce multiple final DRC/LVS correct layouts. The realization phase also considers all transistor sizing and m-‐factor options to produce the final optimum layout set. Figure 3. Pulsic Animate with PolyMorphic Layout The Animate Flow in Action Engineers simply launch Animate and read in OpenAccess-‐format schematics. Animate then automatically derives constraints, recognized from common and user-‐defined circuit topologies (see Figure 4). The automatically generated constraints can be edited or added to at any stage. The system leverages the automation technology to manage constraints throughout the layout process, updating layouts automatically as constraints are changed. Figure 4: Constraints are automatically recognized from common and user-‐defined topologies. Animate then employs the Pulsic PolyMorphic Layout technology to create multiple DRC/LVS-‐
clean layout options in minutes (Figure 5), from which the user can refine down the best variants for further consideration (Figure 6). Figure 5: Animate creates multiple DRC/LVS-‐clean layouts in minutes Figure 6: User refines down the best variants for further consideration enabling efficient exploration of alternative architectures This accelerates the initial layout process dramatically, enabling both the exploration of alternative architectures and the early generation of parasitics for accurate simulation. With these insights, the designer is able to update the constraints or the schematic based on real parasitic data (Figure 7). Layouts can then be re-‐generated in minutes, and the best variant chosen for use in the design hierarchy (Figure 8). Figure 7: Designers can update constraints or the schematics based on real parasitic data early in the design process Figure 8: Layouts are re-‐generated in minutes and the best variant can be chosen for use in the design hierarchy This novel process hugely accelerates the analog layout flow without any sacrifice of QOR. The initial design phase – the longest phase of the process, is at least 2X faster using Animate. The layout iteration phases are 10X faster. The entire layout timeline is cut in half (Figure 9). Figure 9: Animate cuts the entire layout timeline in half Conclusion Previous attempts at analog design automation have mostly resulted in modified versions of made-‐for-‐digital technologies and flows, that have fallen short in terms of usability and, more importantly, QOR. This is why most analog design teams still use mostly manual layout methodologies. However, the move to more and more advanced process technologies, including FinFETs, primarily driven by the mobile communications market, has created an urgent need for automation of analog layout that can really be used. A successful analog layout automation methodology must be a made-‐for-‐analog solution that produces QOR equal to or better than a skilled analog layout engineer. The PolyMorphic Layout technology at the heart of the Pulsic Animate automation solution works the way analog designers work, and produces manual-‐quality, DRC/LVS-‐clean layouts in minutes. This enables early parasitics and constraint and/or schematic changes using real data. Analog design timelines are cut in half, with no sacrifice of QOR in the final layouts. Global Offices United Kingdom (Headquarters) Pulsic Limited 2440 The Quadrant Aztec West, Bristol BS32 4AQ Telephone : +44 (0)117 325 5000 Fax : +44 (0)117 325 5005 Email : [email protected] USA Pulsic Inc Pulsic Inc 2025 Gateway Place, Suite 350 San Jose, CA, 95110 Telephone : (408) 969-‐0316 Fax : (408) 969-‐9923 Email : [email protected] Japan Pulsic Japan ONZE1852 7F, 2-‐14-‐6 Shintomi Chuo-‐ku, Tokyo 104-‐0041 Japan Telephone : +81(0)3-‐3553-‐3061 Fax : +81(0)3-‐3553-‐3063 Email : [email protected] © Pulsic Limited. All rights reserved. Pulsic, the Pulsic logo and Precision Design Automation, Custom Design Automation (CDA) are registered trademarks of Pulsic Limited. All others are properties of their holders.