Lecture 19
Differential Amplifiers – II
Advanced Concepts
In this lecture you will learn:
• Differential Amplifiers
• Use of Current Mirrors in Differential Amplifiers
• Small Signal and Large Signal Models with Current Mirrors
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Differential Amplifier: Double-Ended Output
The FET and BJT differential amplifiers considered in
the previous handout had a double-ended output
Avd
v i 1  v i 2   Avc  v i 1  v i 2 
2
2


v id
 Avd
 Avcv ic
2
v o1 
vi1
+
v o1
vi2
-
v o2
Difference-Mode Output:
Avd
v i 1  v i 2   Avc  v i 1  v i 2 
2
2


v id
  Avd
 Avcv ic
2
v o2  
Common-Mode Output:
v od  v o1  v o 2  Avd v id
v oc 
v o1  v o 2
 Avcv ic
2
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
1
Differential Amplifier: Double-Ended Output
Suppose one tries to connect a load to one of the outputs:
v o1
vi1
+
+
v out
RL
vi2
v out  v o1  Avd
-
-
v o2
v id
v
 Avcv ic  Avd id
2
2
We have lost half of the voltage
We can do better……….
Try another scheme:
v o1
vi1
+
+
RL
vi2
-
v out
-
v o2
v out  v od  v o1  v o 2  Avd v id  Avcv ic  Avd v id
We have recovered
the full signal but this
scheme is not always
practical
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Differential Amplifier: Single-Ended Output
VDD
VDD
R
VO1
ID1
VI 1
VO 2
RL
+
R
ID 2
+
This is an awkward way
to connect the load at the
output ………!
VI 2
- VGS 2
VGS1 -
Most of the time what one would really
like to have is a single-ended output
(without loosing the factor of 2):
IBIAS
v o  Avd v id  Avcv ic  Avd v id  Avd v i 1  v i 2   v out
vi1
+
vi2
-
vo
+
RL
v out
-
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
2
FET Differential Amplifier: Single-Ended Operation
VDD
VDD
R
R
IBIAS
2
IBIAS
2
M1
RL
M2
VIC
VIC
Assume a FET diff amp
IBIAS
A DC common-mode bias VIC is applied at
the input
Assume very large ro1, ro2, and R (compared
to RL) for simplicity
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
FET Differential Amplifier: Single-Ended Operation
VDD
VDD
R
R
iout  ?
IBIAS
 id 2
2
IBIAS
 id 1
2
M1
VIC 
v id
2
+
RL
VIC 
IBIAS
Small signal
ground
v out  ?
-
M2
v id
2
A small signal difference-mode input signal
vid is also applied
v id
2
v
  gm id
2
id 1  g m
id 2
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
3
FET Differential Amplifier: Single-Ended Operation
VDD
VDD
R
R
iout  ?
id 1
M1

+
id 2
RL
v out  ?
-
M2
v
 id
2
v id
2
Only showing the small signal currents and voltages…..
IBIAS
v id
2
v
  g m id
2
id 1  g m
Small signal
ground
id 2
(The DC voltages and currents are not shown)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
FET Differential Amplifier: Single-Ended Operation
VDD
VDD
R
R
iout  ?
v
gm id
2
v
gm id
2
M1

v id
2
+
RL

IBIAS
Small signal
ground
v out  ?
-
M2
v id
2
Since by assumption ro1, ro2, and R are very large
(compared to RL), the small signal current in the
right leg will flow entirely into RL
iout  g m
v id
2
(The DC voltages and currents are not shown)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
4
FET Differential Amplifier: Single-Ended Operation
VDD
VDD
R
R
iout  gm
gm
v id
2
gm
v id
2
M1

v id
2
+
RL
v out  gm RL
-
M2
v id
2
v
 id
2
v id
2
The output current is:
v id
2
This implies:
v
v out  gm RL id
2
v out gm RL
Avd 

2
v id
iout  gm
IBIAS
Small signal
ground
Note the factor 2
Q: How to fix it?!
(The DC voltages and currents are not shown)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
FET Differential Amplifier: Current Mirror Load
VDD
M3
VDD
M4
iout  ?
IBIAS
2
IBIAS
2
M1
+
RL
v out  ?
-
M2
VIC
VIC
IBIAS
The current mirror load will let us recover the factor
of two with a single-ended output!
Assume very large ro1, ro2, ro3 and ro4 (compared to
RL)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
5
FET Differential Amplifier: Current Mirror Load
VDD
VDD
M3
M4
iout  ?
gmn
v id
2
gmn
M1

+
v id
2
RL
v out  ?
-
M2
v
 id
2
v id
2
IBIAS
Now a small signal difference-mode input signal
vid is also applied
Approximate
small signal
ground
(The DC voltages and currents are not shown)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
FET Differential Amplifier: Current Mirror Load
VDD
M3
v
gmn id
2
v
gmn id
2
M4
v
gmn id
2
v
gmn id
2
M1

VDD
v id
2
iout  ?
+
RL
M2

v out  ?
-
v id
2
Now the output current is:
IBIAS
Approximate
small signal
ground
iout  2  gmn
v id
 gmnv id
2
(The DC voltages and currents are not shown)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
6
FET Differential Amplifier: Current Mirror Load
VDD
M3
v
gmn id
2
v
gmn id
2
M4
v
gmn id
2
v
gmn id
2
M1

VDD
iout  gmnv id
+
RL
M2
v out  gmnv id RL
-
v
 id
2
v id
2
Now the output current is:
iout  2  gmn
IBIAS
v id
 gmnv id
2
This implies:
Note the factor of
2 is gone!
v out  gmnv id RL
Approximate
small signal
ground
(The DC voltages and currents are not shown)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
FET Differential Amplifier with Current Mirror: Small Signal Analysis
VDD
M3
VDD
Need to make and analyze a small
circuit model and calculate:
M4
VO  v o
M1
VI 1  v i 1
Avd 
vo
v id
Difference-Mode Gain
Avc 
vo
v ic
Common-Mode Gain
M2
Vi 2  v i 2
IBIAS
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
7
FET Differential Amplifier with Current Mirror: Small Signal Analysis
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
FET Differential Amplifier with Current Mirror: Small Signal Analysis
Small signal circuit model
Note the lack of symmetry!!
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
8
Small Signal Analysis: Difference-Mode Input
There are three unknown internal voltage variables: v o1
vo2
vs
We therefore need three equations
Try KCL at three different nodes…………
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Small Signal Analysis: Difference-Mode Input
(1)
(1)
v

gmn  id  v s   gon v o1  v s   gmbv s  gmpv o1  0
 2


v
 gmn  id  v s   g mbv s  gmpv o1  0

 2
v

  gmbv s  gmpv o1   gmn  id  v s 
 2

ECE 315 – Spring 2007 – Farhan Rana – Cornell University
9
Small Signal Analysis: Difference-Mode Input
(2)
 v

(2) g mn   id  v s   gon v o 2  v s   g mbv s  g mpv o1  gopv o 2  0


2
 v

 gmn   id  v s   gon  gop v o 2  gmbv s  g mpv o1  0
 2


v

 v
 gmn   id  v s   gon  gop v o 2  gmn  id  v s   0

 2

 2
v
gmn
Avd  o  gmn ron || rop 
 vo  vo2 
v id  gmn ron || rop v id
v id
gon  gop
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Small Signal Analysis: Difference-Mode Input
(2)
One can also get the correct results by assuming a-priori that the in the differencemode the voltage vs is approximately zero (i.e. the node is a small signal ground)
If vs is assumed to be approximately zero then:
v o1  
gmn v id
gmp 2
v 

v o 2    gmpv o1  gmn id  gon  gop   gmn gon  gop v id
2 

 gmn ron || rop v id  v o
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
10
Small Signal Analysis: Common-Mode Input
One good way to think about the amplifier in common-mode operation:
If the output conductance of M4 is ignored (assumed to be zero), then the current
mirror, as the name suggests will ensure that the drain currents of M1 and M2 are
identical (both equal to –gmpvo1).
Since the input voltages, vic are also the same, the circuit has complete left-right
symmetry in common-mode operation
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Small Signal Analysis: Common-Mode Input
So one can assume that the in the common-mode, even with the current mirror, no
current flows in the bottom most horizontal wire (i.e. it is a small signal open)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
11
Small Signal Analysis: Common-Mode Input
(1)
Doing KCL at (1) gives:
v o1  
g mn
ron
g mp
ron 
1
gmp
 2roc  g mn  gmb ron 2roc 
v ic
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Small Signal Analysis: Common-Mode Input
(2)
Using the left-right symmetry gives:
v o  v o 2  v o1
Avc 
vo

v ic
r
on
g mn
ron
g mp

1
 2roc  g mn  g mb ron 2roc 
g mp
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
12
Small Signal Analysis: Output Resistance
it
Rout  ron || rop
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Two-Port Model of a FET Differential Amplifier with Current Mirror
vi1
Rout
+
vo
Avd v i 1  v i 2 
vi2
 v  vi2 
 Avc  i 1

2


-
Avd  gmn ron || rop 
Avc 
vo

v ic
g mn
ron
g mp
ron 
1
 2roc  g mn  g mb ron 2roc 
g mp
g mn
g mp

1
2roc
 g mn  g mb 2roc 
ron
Rout  ron || rop
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
13
FET Cascode Differential Amplifier with Cascode Current Mirror
VDD
VDD
M7
M8
M5
M6
M3
M4
M1
VI 1  v i 1
Rout  gmn ron ron  || gmp rop rop 
VO  v o
Avd  gmn Rout


Avd  gmn gmn ron ron  || gmp rop rop 
M2
Vi 2  v i 2
IBIAS
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
14