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Application Note
AN31: How to use the Peak Detector Voltage to
Compensate for the Amplifier’s Output Voltage
Change due to Temperature
Purpose
This document covers the basic application usage of the Centellax driver amplifier’s peak
detector voltage to compensate for the amplifier’s output voltage change due to temperature.
Introduction
Centellax designs and manufactures driver amplifiers, many of which have an on-chip
differential peak diode detector. This feature can be used with either an external op amp circuit
or DSP with a look-up table to enable real time output voltage detection and feedback, to
compensate for the output voltage/power change due to temperature.
This application note assumes that all the amplifier bias voltages are set at room temperature
and the system is operating as intended.
Output Peak Detector Basics
The block diagram of the on-chip peak detector is shown in Figure 1. The circuitry consists of
two diodes, one with RF signal and DC offset (Vdet), and the other with only DC offset (Vref).
This topology allows for common mode cancellation of the diode temperature drift. Vdet is the
RF detector’s output voltage used to detect the amplifier’s output voltage level, plus the drift of
the diode detector due to temperature. The Vref is the DC reference detector’s output voltage; it
measures the drift of the diode detector due to temperature.
Most Centellax driver amplifiers feature this peak detector, but since the nominal DC bias of
each amplifier varies, the DC offset voltage will be slightly different from family to family. This
application note outline will work for all Centellax driver amplifiers.
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Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Figure 1: Simplified on-chip peak detectors
Measurements of the Peak Detector
Figure 2 is an example of the OA3HVQDSL peak detector output measurement plot (Vref and
Vdet). In this example, the Vref (blue trace) and Vdet (red trace) output voltages are ranging
from 4.7 volt to 6.6 volt. This corresponds to the amplifier’s output voltage from 2.2 Vpp to 8
Vpp, respectively, at one temperature (e.g., room temperature).
After obtaining the peak detector output measurements, calculate the difference between Vdet
and Vref [i.e., (Vdet – Vref), external calculation by the user], the result is called the calculated
peak detector voltage. This calculated peak detector voltage corresponds to the amplifier’s
output voltage level, as shown in the graph, Figure 2. In this example, the calculated peak
detector voltage (light green trace) ranges from 0.3 V to 1.7 V, corresponding to the amplifier’s
output voltage from 2.2 Vpp to 8 Vpp.
Centellax • www.centellax.com • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Figure 2: Example of OA3HVQDSL peak detector output voltages and the calculated (Vdet-Vref) peak
detector voltage
The next step is to look at the calculated peak detector voltage (Vdet-Vref) versus temperature.
This will give the end user an indication on how the amplifier output voltage responds versus
temperature.
Figure 3 is an example showing the change in the calculated peak detector voltage
(corresponding to the change in the amplifier’s output voltage) due to temperature. The desired
output voltage is 5 Vpp at room temperature. (In this example, this is equivalent to the
amplifier’s package temperature of 40oC).
Centellax • www.centellax.com • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Figure 3: Example of OA3HVQDSL calculated peak detector output voltage versus temperature
The graph in Figure 3 shows the OA3HVQDSL amplifier output voltage has a negative
temperature coefficient. The temperature coefficient is -0.0025 Vpk_detector/oC.
Example, temperature coefficient (change from 40oC to 60oC) =
=
= -0.0025 Vpk_detector/oC
Application Usage of the Peak Detector Signals
By knowing the relationship characteristics of the calculated peak detector voltage versus the
amplifier’s output voltage (Figure 2), the temperature coefficient of the amplifier’s output (Figure
3, knowing the direction of the output voltage change versus temperature), then one can design
a close-loop system (e.g., DSP control with a look-up table) to compensate for the change in the
output voltage of the amplifier due to temperature. See the block diagram example in Figure 4
for a digital feedback control system. This application note will also briefly discuss the analog
feedback control circuitry.
Centellax • www.centellax.com • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Figure 4: Example of output voltage compensation digital feedback control loop block diagram
In linear operation mode, there are two options:
a) Amplifier that has a gain control (VGC) bias feature:
When the amplifier’s output voltage is dropped due to temperature change, refer to
the block diagram in figure 4, by measuring the Vref and Vdet diode output voltages,
and calculate their difference (i.e., calculated peak detector voltage = Vdet - Vref) by
the DSP. Then, from a look-up table (see example in the appendix section), the DSP
of the compensation circuitry can adjust the voltage driving the VGC bias pin, which
might be a digital DAC or it might be an analog voltage. By increasing the VGC (gain
control) bias voltage, which increases the gain of the amplifier, keeping the
equivalent desired output voltage level. See Ffigure 5 for an example of amplifier
small signal gain (S21) versus gain control voltage (VGC) plot. The control loop will
continue to operate and adjust the VGC voltage until the peak detector voltage
reaches the equivalent corresponding desired output voltage level.
Note keep the VGC bias voltage within the amplifier specification limit.
Centellax • www.centellax.com • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Figure 5: Example of amplifier small signal gain vs. VGC bias control
b) Amplifier that has no built-in gain control (VGC) bias feature, only VB2 bias control:
When the amplifier’s output voltage is dropped due to temperature change, refer to
the block diagram in Figure 4, by measuring the Vref and Vdet diode output voltages,
then calculate their difference (i.e., calculated peak detector voltage = Vdet - Vref) by
the DSP. Then, from a look-up table, the DSP of the compensation circuitry can
adjust the voltage driving the VB2 bias pin, which might be a digital DAC or it might
be an analog voltage. By increasing (i.e., higher positive voltage) the VB2 bias
voltage to increase the gain of the amplifier, keeping the equivalent desired output
voltage level, (VB2 = gain-amplitude adjust, the 2nd gate bias on the last stage of
amplifier). The control loop will continue to operate and adjust the VB2 voltage until
the peak detector voltage reaches the equivalent corresponding desired output
voltage level.
Note keep the VB2 bias voltage within the amplifier specification limit. For additional
information on VB2 gain-amplitude (a.k.a., dynamic gain) control feature, see
Centellax Application Note 03.
In limiting operation mode:
Assumed VGC is set to maximum gain (if this function is available). When the amplifier’s output
voltage is dropped due to temperature change, the control loop operation is similar to the linear
mode as stated in above, except the DSP of the compensation circuitry will adjust the voltage
driving the VD2 bias (drain bias) or VB2 bias (gain-amplitude control bias) to increase the gain
to the equivalent desired corresponding output voltage level. (VD2 = drain bias on the last
stage of amplifier, for peak-amplitude adjust, and VB2 = gain-amplitude adjust on the last stage
of the amplifier).
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Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Note keep the VGC (if available), VD2, and VB2 bias voltages within the amplifier specification
limits.
Alternative Feedback Loop Control Circuit
Another method to compensate for the output voltage change of the amplifier due to
temperature is to use an analog feedback loop control circuit, (see the block diagram in Figure
6). It uses an op amp to measure the delta of the peak detector output voltages, (i.e., VdetVref), and a PID controller circuit (PID = Proportional, Integral, and Derivative) to perform the
adjustment feedback to the driver amplifier relative to the “amplitude set” value inside the control
circuit loop, (i.e., to adjust the VGC bias voltage (if VGC feature is available) or VB2 bias
voltage, in linear operation mode; or VD2 or VB2 bias voltage in limiting operation mode).
Figure 6: Example of output voltage compensation analog feedback loop block diagram
Notes:
The peak detector outputs are used to detect the change in the output voltage of the driver
amplifier due to temperature. The detector outputs have high response bandwidth (BW), (e.g.,
in the MHz range). Using a shunt capacitor in the peak detector signal path will lower the BW of
the feedback loop to below the amplifier operating frequency. This will help ensure the
feedback control loop works properly. Example, if the low-end operating frequency is 100 KHz,
then design the feedback control loop bandwidth to be 10 KHz. If the feedback control loop BW
is within the amplifier operating frequency, the control loop may start to modulate/react at the
amplifier operating frequency rate.
Centellax • www.centellax.com • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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Application Note
Summary
This application note outlined two methods (digital feedback control loop and analog feedback
control loop) for using the amplifier’s peak detector voltages to compensate for the output
voltage level change of the driver amplifier due to temperature. Which method to use will
depends on the application, or it can be a combination of digital and analog circuitries (i.e., a
hybrid) to provide the feedback loop control.
Appendix
Example of Look-up Table for Output Voltage versus Calculated Peak Detector Voltage
Table 1 is an example of a look-up table for the output voltage (Vout) with its corresponding
calculated peak detector voltage value (Vdet – Vref). This information can be obtained from the
amplifier datasheet, or for better accuracy and resolution, by performing a calibration
measurement on the amplifier’s output voltage versus “Vdet” and “Vref” output voltages (i.e.,
calculated peak detector voltage) based on the transceiver setup configuration.
Table 1: Example of a look-up table for Vout vs. calculated Peak Detector voltage
Vout
(Vpp)
2.24
4.36
5.96
7.09
7.62
7.79
7.95
Calculated Peak Detector
(Vdet - Vref, V)
0.31
0.78
1.18
1.47
1.62
1.67
1.73
References
1. Centellax Application Note, AN02, Centellax MMIC Amplifiers with On-Chip Power
Detectors.
2. Centellax Application Note, AN03, Centellax MMIC Amplifiers with Dynamic Gain Control
3. Centellax Application Note, AN16, DC Biasing for Centellax Modulator Drivers
For more information on Centellax’s products, applications, or services, please contact
Centellax or Centellax’s representatives. The complete list is available at:
http://www.centellax.com/component-representatives.
The information contained herein is believed to be accurate and is provided “AS IS, WHERE IS”, with all faults and the entire risk associated with its use being
entirely with the user. Centellax makes no representation with respect to the merchantability of the products or their suitability or fitness for any particular purpose
of use. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other
intellectual property rights, whether with regard to such information itself or anything described by such information. The information contained herein is
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Agreement between Centellax and the user and it is then to be treated accordingly
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Specifications subject to change without notice. © 2014 Centellax, Inc. 16 June 2014. SmD-00247 Rev A.
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