How-to-Program with Griffy-C - Griffy-C syntax Ing. Claudio Mucci ARCES University of Bologna Data Flow Graph A B C D E F + - G | H I + & L M + C-Described Data Flow Graph features: – Node functionality is described by a C-level operators (e.g. +, -, >>, <<, &, |, …) – Each edge is described by a Single Assignment Variables OUT = ((A+B)+(C-D)) + ((C-D) & (E|F)); ARCES University of Bologna C-Described DFG A B C D E + F - Inputs: A,B,C,D,E,F Output: OUT | Manually-Dismantled Code: G H I + & L M + OUT = ((A+B)+(C-D)) + ((C-D) & (E|F)); G = A + B; H = C - D; I = E | F; L = G + H; M = I & H; OUT = L + M; ARCES University of Bologna Manual Dismantling Bad dismantling Good dismantling ARCES University of Bologna PiCoGAop Description #pragma fpga NAME OPCODE DELAY NOUTS NINS OUTS INS { // Local variables declaration: [static] unsigned/signed int/short int/char <vars>; // Local attribute declaration: #pragma attrib <vars> [SIZE=<dim>, SAT] [function description] } #pragma end ARCES University of Bologna Griffy-C Description – Supported operators Function description: – Add, Sub (+, -) – Shift (<<, >>) – Bitwise and, Bitwise or, Bitwise xor, Bitwise not (&, |, ^, ~) – Compare (==, !=, >, <, >=, <=) – Conditional assignment (cond ? if_true : if_false ) – Concatenation (dest = src1 # src2 ;) – LUT programming (dest = src @ 0x[LUT] ;) Example: and6i = input @ 0x1; ARCES University of Bologna Griffy-C Variable Attributes #pragma attrib: – SIZE=nbits (nbits < original size) – SAT var_name = data1 [+/-] data2; var_name(overflow) Æ if var_name is signed var_name(carryout) Æ if var_name is unsigned Variable resizing: – resized_var = original_var; – resized_var = original_var >> step; ARCES University of Bologna Example #pragma fpga absolute_difference 0x11 4 1 2 dataout datain1 datain2 { unsigned char diff1, diff2; char cond; #pragma attrib cond SIZE=1 diff1 = datain1 - datain2; diff2 = datain2 - datain1; - - cond = diff1 < 0; dataout = cond ? diff2 : diff1; } #pragma end MUX ARCES University of Bologna How-to-Program with Griffy-C - Griffy-C environment - ARCES University of Bologna Algorithm Implementation Flow on the PiCoGA Griffy-C DFG description Assembly-like code Single-Assignment variables Bit-level setting of variable size Intermediate Representation for Advanced C-Compiler Pipelined DFG Library-based C-operands mapping Routing-only operations detection Library-based Synthesis ARCES University of Bologna Place & Route Placement – Pipeline stages fitting into one or more rows – Regular placement based on C-driven library elements Routing – Based on the opensource VPR-router (University of Toronto) ARCES University of Bologna XiRouter Global inputs (from Register File) Syntax: xipr_opt function_name Global outputs (to Register File) ARCES University of Bologna Griffy-C Æ PiCoGA Syntax: FastGriffy [options] filename.c Main options: [-v2] – Verbose mode [-noplace] – Disable placement (only first-tentative placement) [-ps] – Provide the PostScript-file of the pipelined DFG Other options: type FastGriffy without arguments Emulation Function Griffy-C Description FastGriffy Filename_fpga.[ch] Configuration Bits ARCES University of Bologna XiRisc Algorithm Development Environment ARCES University of Bologna XiRisc C-compiler GNU GCC toolchain retargeted for XiRisc Tools: – Compiler: build [options] filename.c Main options: +debug, +64 HELP Æ build Output in test.exe/test.gdb Disassembled executable: test.read – Debugger: ddd test.gdb & ARCES University of Bologna XiRisc-DDD Debugger ARCES University of Bologna XiRisc Profiler Single Datapath Profiler: – SingleProf_fast <filename> (without .c extension) XiRisc Profiler: – DoubleProf_fast <filename> (without .c extension) Outputs: filename[_double].profas filename[_double].profc ARCES University of Bologna C-code with PiCoGAop PGAOP instance: – pga_name (args list); PGALOAD instance: – pga_load_df_<pga_name> (); PGAFREE instance: – pga_free_<pga_name> (); ARCES University of Bologna Esercitazione Laboratorio emacs/vi Æ Scrittura codice C & Griffy-C xhost + ssh/rsh griffy (192.168.1.130) setenv DISPLAY cad<xx>:0.0 source ~griffy/griffy.tcsh FastGriffy –ps –v2 <filename.c> build +debug <filename_fpga.c> ddd test.gdb & DoubleProf_fast <filename_fpga> – xipr_opt <func_name> Æ Place & Route – gv <func_name> Æ Pipelined DFG – target sim – load test.gdb ARCES University of Bologna Esercizio Realizzazione di un sommatore di 8 elementi, ciascuno rappresentato da 8 bit, sull'architettura riconfigurabile XiRisc. • Scrivere il codice C relativo all'implementazione tradizionale (puramente software) •Effettuare mapping su PiCoGA del sommatore, stimando la latenza • Riscrivere il codice C con l'opportuno inserimento delle pgaop • Fornire una stima dello speed-up ottenibile Ipotesi semplificativa: Non considerare l'overflow sui risultati intermedi ARCES University of Bologna Account Laboratorio CAD Per ricevere l’account per l’accesso alla saletta CAD occorre riempire il form all’indirizzo: http://tori.ing.unibo.it/l3l/guerrieri.php Per oggi account temporanei ARCES University of Bologna
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