1. science
2. mathematics
3. arithmetic

CHAPTER-1: Introduction
PROGRAM:
A sequence of instructions describing how to perform a certain task is called a program.
MACHINE LANGUAGE:
The computer instructions form a language which makes possible for people to
communicate with the computer. Such a language is called Machine Language.
STRUCTURED COMPUTER ORGANIZATION:
People want to do x1 but computers can only do y. This complexity can be mastered
and computer systems can be designed in a systematic way. This approach is called structured
computer organization.
LANGUAGES, LEVELS AND VIRTUAL MACHINES:
People use a set of instructions to form a language (say L1) and the built in instructions
forms a language (say L0). So, the technique of translation is required for executing a program
written into L1 language. The other technique that can be used for executing a program written
into L1 language is interpretation.
In translation, the entire program written in L1 language is first replaced by an equivalent
sequence of instructions in L0 language. The resulting program then constitutes entirely of L0
instructions and the computer then executes the L0 program instead of old L1 program. In
interpretation, each L1 instruction is examined and decoded, and carried out for execution
immediately.
Let us imagine a hypothetical computer or virtual machine whose machine language is
L1 (and let us cal the virtual machine corresponding to L0, M0). If such a machine could be
constructed, people could simply write their programs in L1 and have the computer execute
them directly.
A multilevel machine in shown below. A computer with n levels can be regarded as
different virtual machines, each with a different machine language only. Programs written in
language L0 can be directly carried out by electronic circuits without the need for translation or
interpretation. Programs written in L1, L2… Ln must either be interpreted or translated to
another lower level. Most programs using a n-level machine are only interpreted in the top level.
Virtual machine Mn with machine language Ln
Level n<- programs in Ln are either interpreted running on lower
the machine language of a
Lower machine.
Virtual machine M3 with ML L3
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machine or are translated to
Level 3
Virtual machine M2 with machine language L2
Level2
<- Programs in L2 are either interpreted by interpreters running on M1 or M0 or are translated
to L1 or L0
Virtual machine M1 with machine language L1
Level1
<-Programs in L1 are either interpreted by an
Interpreter running on M0 or are translated to
L0.
Virtual machine Mn with machine language Ln
Level0
<- Programs in L0 can be directly executed by
the electronic circuits.
Fig: A multilevel machine
CONTEMPORARY MULTILEVEL MACHINE:
Most computers consist of two or more levels. Machines with six levels may exist. A sixlevel computer is shown below:
Problem oriented language level
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level 5
Assembly language level
Translation(compiler)
Operating system machine level
level4
level 3
Partial interpretation(os)
Partial InterpretationInstruction set
Architecture level
(os)
level 2
Interpretation (microprogram) or direct execution
Micro architecture level
level1
hardware
Digital logic level
level0
Fig: A six level computer
1.Digital logic level (level 0):
It is the lowest level. This level consists of gates. Gates are combined to form a
memory.
2. Micro-architecture level (level 1);
This level consists of collection of Registers (8 to 32) that forms a local memory and a
circuit called ALU (Arithmetic Logic Unit). ALU is capable of performing simple Arithmetic
and logical operations.
3. Instruction set Architecture(ISA) level (level2):
It describes the machine’s instruction set and describes how the instructions are carried
out by micro-program or hardware execution circuits. Usually, a manual for each of the
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computer is published by the manufacturer.
4. Operating system machine level( level3):
Some of the level3 instructions are interpreted directly by the micro-program. The new
facilities added to level 3 are carried out by an interpreter running at level2.
5. Assembly language level (level4):
Level4 and above are intended for application programmer with a problem to solve.
Level 4 and above are always translated rather than the lower level 2 and 3 are always
interpreted. Level 4 is a symbolic form for one of the underlying languages. Programs in
Assembly language are first translated to level 1,2 or 3 language and then interpreted by
the actual machine.
6. Program-oriented language level (level5)
It usually consists of languages designed to be used by applications programmers.
Such languages are often called high level languages. Programmes written in these
languages are first converted into level 3 or 4 by compilers.
CHAPTER-2 COMPUTER SYSTEM ORGANIZATION
CPU Organization:
The internal of a von Neumann CPU is shown in figure below. It consists of ALU
and several buses connecting the various components.
A and B are the Registers fed into ALU. These Register holds ALU input while
the ALU is computing. After calculation, the output of ALU is stored in output Register. These
outputs then can be written on memory later on.
There are different types of instructions in a computer. They may be Registermemory or Register-register. Register-Memory instructions allow memory words to be fetched
into Registers.
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Fig: Internal organization of Von Neumann Machine.
The organization of a simple compter with one CPU and two I/O devices is shown below:
2nd pic
DESIGN PRINCIPLES OF MODERN COPUTERS
There are various considerations to be taken while designing modern computers. The major
ones are discussed below.
All instructions are directly executed by hardware
Common instructions are directly executed by hardware which eliminates a level of
interpretation. Hence, it provides high speed for most instructions.
i.
Maximize the rate at which instructions are issued.
In order to maximize the performance of modern computers, nowadays computers issue as
many instructions per second as possible. It suggests that parallelism can play a major role
in improving performance.
ii.
iii. Instructions should be easy to Decode:
Decoding of instructions determine what resources they need. So, the instructions should be
made regular, fixed length and with a small number of fields.
iv. Only loads and stores should reference memory:
Access to memory can take a long time, and the delay is unpredictable. These instructions
can best be overlapped with other instructions if they do nothing but move operands
between registers and memory. It shows that only load and store instructions should
reference memory.
Provide Plenty of Registers:
Since accessing memory is relatively slow, many registers need to be provided. Once
v.
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the word is fetched, it can be kept in registers until it is no longer needed. If registers are
increased, the access time required for processor is lesser than that of memory.
INSTRUCTIONS-LEVEL PARALLELISM (ILP)
It is a technique to get even more performance for a given clock speed. It helps to do two or
more things at once. i.e. Parallelism
ILP helps to get more instructions/sec. Pipelining technique is employed for instruction level
parallelism.
The principle of pipelining is discussed below:
Pipelining:
In pipelining technique, the instruction execution is divided into many parts and each
part is handled by dedicated piece of hardware, all of which runs in parallel.
In figure below, a pipelining consisting of five stages is shown; They are fetch unit which
is stage 1(s1), decode unit (s2), operand fetch (s3), execution unit(s4) and writeback unit(s5).
The fetch unit fetches the instructions from memory and places it into a Register(buffer).
The decode unit decodes the instructions and determine its types and what operands is
needed. The operand fetch unit fetches the operands either from Registers or from memory.
The execution unit actually does the work of carrying out the instruction. Finally, the writeback
unit writes the result back to proper Register.
Fig:A
Fig: A five stage pipeline
The operation of a pipeline as a function of time is shown below;
Fig:B
During cycle 1, stage s1 (fetch unit) is working on instruction 1. During cycle 2, stage 2 (Decode
unit) decodes instruction 1 and stage 1(fetch unit) fetches instruction 2. During cycle 3, stage s1
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is fetching instruction 3, stage s2 is decoding instruction 2 and stage 3 is calculating operands
for instruction 1. Similarly, during clock cycle 4, stage 1 is working on instruction 4, stage 2 is
decoding instruction 3, stage 2 is working on instruction 2 and stage 1 is executing instruction
1. During the clock cycle 5, the fetch unit (stage 1) fetches instruction 5, decode unit (stage 2)
decodes instruction 4 and so on.
Hence, we can see that 5 cycles are required to get output of a single instruction. But because
of pipeline 5 instructions are completed in 9 cycles instead of 25 clock cycles. So, pipelining
increases the performance of a processor.
In some architectures, multiple pipelines are used which further increases the performance of a
processor. An example of dual five stage pipeline with common instruction fetch unit is shown
below:
Fig: C
Super Scalar Architecture:
In super scalar architecture the fourth stage (execution stage consists of multiple
functional units. The stage3 (s3) or operands fetch unit can issue instructions faster than S4
stage. Hence, because of multiple functional units, multiple instructions would be executed
parallel.
Fig: super scalar Architecture
Processor Level Parallelism:
To get larger gain or better performance, computers with multiple CPU's or processor are
designed. Processor level parallelism can be designed by various methods as follows:
1. Array Processor:
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It consists of large number of identical processors that perform the same
sequence of instructions on different sets of data. Each processor used
its own data from its own memory.
eg. ILLIACIV
Fig: An array of Processor
2. Vector Processor:
Like an array processor, it is very efficient at executing a sequence of
operationson pairs of data elements. But unlike an array processor, all
of the addition operations are performed in a single heavily pipelined
adder. It consists of vector unit rather than larger number of hardware as
required by array processor.
3. Multiprocessor(Independent CPUs):
It is a system with more than one CPUs sharing a common memory.
Each processing elements are independent with each other. One of the
implementation of multiprocessor system is shown below:
Fig: Multiprocessor system
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Chapter 3:
SEQUENTIAL CIRCUITS
Sequential Circuit:
A sequential circuit is an interconnection of flip-flops and gates. The block
diagram of sequential circuit is shown below. The o/p of a sequential circuit is not only
dependent upon the previous state of flip-flop.
Fig: block diagram of sequential circuit
An example of seq. circuit is shown below:
Fig(a): example of sequential circuit
The i/p equation connected to D input of flip-flops A is given by:
DA= Ax + Bx
The i/p eqn connected to D input of flip flop B is given by,
DB= A'x
The external o/p of the sequential circuit is given as;
Y=Ax' + bx'
STATE TABLE:
The state table relates o/p and next states as a function of inputs and present
states. The state table for the circuit of fig (a) is shown below:
Fig(b): state table of circuit shown in fig(a)
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STATE DIAGRAM:
It is a graphical representation of state table. A state is represented by a circle
and the transition between states is indicated by directed lines connecting the circuits.
Fig:
state diagram for state table of fig(b)
Design procedure for sequential Circuit:
●
●
●
●
●
●
The behaciour of the circuit is formulated in a state diagram.
The number of flip-flops needed for circuit is determined from the number of bits listed
within the state diagram.
Then assign letters to designate all flipflops, input and output variables.
The state table is then obtained.
BY inspecting the state table, the flipflop input equation is obtained.
The logical diagram is made (or sequential circuit)
Design Example:
Design a clocked sequential circuit that goes through a sequence of repeated binary states
00,01,10,11 when an external input x is equal to 1, the state of the circuit remains unchanged
when x=0;
Solution:
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Fig: state diagram
Fig: state table:
Now, the input equations for the flip-flops is found as follows:
JA=B.x
KA=B.x
JB=x
KB=x
Now the sequential circuit is shown below:
Fig:2 bit binary counter
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CHAPTER 4: REGISTER TRANSFER AND MICROOPERATIONS
Micro-operations:
The operations executed on data stored in Registers are called micro-operations. Microoperations is performed on informations stored in one or more Registers. Examples of
microoperations are shift , count, clear and load.
Register Transfer Lnaguage:
The symbolic notation used to describe the microoperation transfer among Registers is
called a Register Transfer Language.
Register Transfer:
There are different types of types of Register for different functions. For eg. MAR, PC,
IR, DR are the various Registers that are used for different purposed by the computer
(processor).
Information transfer from one Register to another is designated in symbolic form by
means of a replacement operator.
For. Eg. R2 R1 denotes a transfer of content of Register R1 into Register R2. The
content of source Register R1 doesn't change after the transfer.
Some times we need to transfer only under a predetermined control condition as shown
below.
If (p=1) then (R2
R1)
In the above example, P is a control signal generated in the control section. It can be
weitten symbolically as follows:
P:R2
R1
Sometimes two or more operations are executed at same time. Then a comma is used
to separate two or more operations as shown below:
T:R2
R1, R1
<- R2
The basic symbols used for Register Transfer are shown below:
Symbol
Letters(and numbers)
Parentheses
()
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Description
Denotes a Register
Denotes a part of Register
Examples
MAR,R2
R2(0-7), R2(L)
Arrow
Comma
,
Denotes a transfer of
information
Separates two microoperations
R2
R2
R1
R1, R1
R2
Fig: Basic symbols for Register Transfers
BUS AND MEMORY TRANSFER:
An efficient scheme for transferring information between registers in a multiple-register
configuration is a common Bus System. A bus structure consists of a set of common lines, one
for each bit of a register, through which binary signals determine which register is selected by
the bus during each particular Register transfer.
The construction of common bus system for four registers is shown below. Each
Register has four bits. The bus consists of 4*1 multiplexers having four data inputs 0 to 3 and
two selection inputs s1 and s0. In the figure, Bits in each Register are connected to the data
inputs of one multiplexer to form one line of the bus. The mux 0 multiplexes the four 0 bits of the
Registers, mux 1 multiplexes the four 1 bits of the Registers and so on.
The selection line s1 and s0 are connected to all four multiplexers.The selection line
shoose the four bits of one Registers and transfer them into four-line common bus. The table
below shows which Register is selected.
S1
0
0
1
1
S0
0
1
0
1
Register Selected
A
B
C
D
For example, we need to transfer the content of Register C and load this content to R1. Then
we can symbolize it by following statement.
Bus<-C, R1<-Bus
If the bus is known to the system, then it can be written as follows:
R1<-C
In this statement, the designer knows which control signals must be activated to produce the
transfer through Bus.
Fig: Common Bus system for four registers.
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THREE STATE BUS BUFFERS:
A bus can also be constructed by using three state gates instead of multiplexers. The three
states are logic 1, logic 0, and high impedance state. The high impedance state behaves like
open circuit.
The bus system using three state buffers is shown below. The outputs of four buffers are
connected together to form a single bus line for normal inputs will communicate with bus line.
Only one buffer is active at any given time.
Fig.L
Memory Transfer:
The memory transfer involves two operators – Read operation and write operation
The transfer of information form a memory word to the outside environment is called a
Read Operation. The Read operation can be stated as follows:DR<-M [AR]
This statement causes a transfer of information into Data Register (DR) form the
memory word M selected by the address in AR (Address Register).
The transfer of new information to be stored into the memory is called a write operation.
The write operation can be stated as follows:
M [AR] <-R1
This statement causes a transfer of content of data Register to a memory word M
selected by the address in AR.
Arithmetic Microoperations:
Arithmetic microoperations perform arithmetic operations on numeric data stored in
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Registers. The basic Arithmetic operations are addition, subtraction, multiplication, division,
increment, decrement etc. The difference types of arithmetic microoperations are shown below:
Symbolic designation
Description
R3<- R1+R2
contents of R1 and R2 are added and transferred to R3.
R2<-R1-R2
Contents of R2 is subtracted form content of
R1 and the result
is transferred to R3
R2<R2complement
Complement the contents of R2(1's complement).
R2<-R2 complement +1
2's complement the contents of R2
R1<R1+1
Increment the contents of R1 by one
R1<-R1-1
Decrement the contents of R1 by one
Table: Arithmetic microoperations
Logic micro operations:
Logic microoperations perform bit manipulation operations on non new numeric data stored in
Registers. The general logical microoperations include AND, OR, NOT, NAND, XOR, XNOR,
clear, set etc.
For example:
R1=1010
R2=1100
The OR operation is to be performed and result to be stored in R1 Register. What would be the
content of R1 after OR operation?
R1=1010
R2=1100
After OR operation, the content of R1=1110
i.e. R1=1110
symbolically, the OR operation can be stated as follows:
R1<-R1 v R2
The different types of logic microoperations are shown below:
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Fig: Table 1
Shift Microoperations:
These microoperations are used for serial transfer of data. The contents of a Register
can be shifted to the left or right. The different types of shift operations are logical shift left ,
logical shift right, circular shift left, circular shift right, Arithmetic shift left and Arithmetic Shift
Right.
i.
Logical Shift:
A logical shift is one that transfers 0 through the serial input. Shl is used for logical
shift left and shr is used for logical shift right.
For eg. R1<-shl R1
R2<-shr R2
Fig:111
After logical shift right, the content of the Right register becomes as follows:
Fig:112
Let us consider the content of Register R2 as shown below:
Fig:113
After logical shift left, the content of Register R2 becomes as follows:
Fig114
II. Circular Shift:
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It is also known as rotate operation. It circulates the bits of the register around the two
ends without the loss of information. Cil is used for circular shift left and cir is used for circular
shift fight.
For eg:
R1<-cil R1
R2<-cirR2
Let us consider the content of Register R1 as follows:
Fig:115
After circular shift left, the content of Register R1 is as follows:
Fig:116
Let us consider the content of Register R2 as follows:
Fig:117
The content of Register R2 after circular shift right is as follows:
Fig:118
III. Arithmetic Shift:
It is a shift micro operation that shifts a signed binary number to the left or right.
Symbolically, it is written as:
R1<-ashl R1
R2<- ashl R2
In arithmetic shift micro operations, the sign bit is left unchanged.
For eg:
Let us consider the content of Register R1 as follows:
Fig:119
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After Arithmetic shift left, the content of Register R2 is as follows:
Fig:120
Let us consider the content of R2 as follows:
Fig: 121
After Arithmetic shift right, the content of Register is as follows:
Fig:122
Arithmetic Logic Shift Unit:
Computer systems employ a number of storage Registers connected to a common
operational unit called an ALU. The ALU perform all micro operations and the result is then
transferred to a description Register. In ALU, the entire operation is performed during one clock
pulse period. The shift micro operations are often performed in a separate unit but sometimes
the shift unit is made part of the overall ALU.
The figure below shows one stage of Arithmetic logic shift unit. Inputs Ai and Bi are
applied to both arithmetic and logic units. A particular micro operation is selected with inputs s1
and s0. A 4x1 mux at the output chooses between an arithmetic output in E1 and a logic output
in Hi. The data in the MUX are selected with inputs S3 and S2. The two inputs in MUX i.e. Ai-1 is
used for shift right operation and Ai+1 for shift left operation. For n bit ALU, the following circuit
must be separated n times. The output carries Ci+1 is connected to the input carry ci of the next
stage in sequence.
The given circuit in this example performs eight arithmetic operations, four logic
operations and two shift operations. The arithmetic operations are selected with S3 and S2 =00.
The logic operations are selected with s3 s2=01. The input carry has no effect during logic
operations and is marked with don’t care X's. The shift left operations is selected with S3S2 = 11
and shift right operation is selected with S3S2 =10
Fig:123 One stage of Arithmetic logic Shift Unit
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Table:124 Function table for Arithmetic ligic shift unit
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CHAPTER-5: BASIC COMPUTER ORGANIZATION AND DESIGN
Program:
A program is a set of instructions that specify the operations, operands, and the
sequence by which processing has to occur.
Instruction Code:
It is a binary code that instructs the computer to perform a specific operation. The
instruction code consists of two main parts- opcode (operation code) and operand. The opcode
defines the operation such as add, subtract, multiply etc. The operand provides the address or
data or which the operation is to be performed.
STORED PROGRAMMED ORGANISATION:
This concept employs that instructions and data are all stored in memory. The control
reads a instruction form the memory. Then it reads the address part of the instruction to obtain
operand from memory and executes the operation specified by the operation code.
Fig: stored program organization
Direct Address and Indirect Address:
When the operand part of an instruction code specifies an opcode, the instruction is said
to have an immediate operand.
When the operand part of an instruction specifies the address of an operand, the
instruction is said to have direct address.
When the operand part of instruction specifies the address of memory word in which the
address of operand is found, it is said to have indirect address.
One bit of the instruction code is used to distinguish between direct and indirect address.
The bit 0 is used for direct address and bit 1 for indirect address.
Fig:
An example of direct addressing and indirect addressing is shown below:
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Fig:
Computer Registers:
There are different types of Registers in a basic computer that have their own functions.
The different types of Registers and their functions are listed below:
Register Name
Register Symbol
No. of Bits
Function
Data Register
OR
16
Holds memory operand
Address Register
AR
12
Holds address for memory
Accumulator
AC
16
Processor Register
Instruction Register
IR
16
Holds Instruction code
Program counter
PC
12
Holds address of Instructions
Temporary register
TR
16
Holds temporary data
Input Register
INPR
8
Holds input character
Output Register
OUTR
8
Holds output character
COMMON BUS SYSTEM:
The most efficient scheme for transferring information in a system with many Registers
is to use a common BUS. The connection of Registers and memory of the basic computer to a
common bus system shown in figure below:
The Registers DR, AC, IR and TR have 16 bits each Two Registers AR and PC have 12
bits each. The INPR and OUTR are 8 bits each and communicate with the eight least significant
bits in the bus. There is no transfer of OUTR to any of the other Registers.
The 16 lines of the common Bus receive information from six Registers and the memory
units. The input data and output data of the memory are connected to the common Bus but the
memory address is connected to AR.
The 16 inputs of AC come from Adder and logic circuit. Ac consists of input from DR,
INPR and the output of AC. The specific output selected for the bus line is determined from the
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selection variables S2, S1 and S0.
Fig: vvv
Timing and control:
The timing for all Registers in the basic computer is controlled by a master clock
generator. The clock pulses are applied to all flip-flops and Registers in the system. The clock
pulse do not change the state of a Register unless the Register is enabled by a control signal.
The control signals are generated in the control unit.
Control Unit:
There are two types of control unit. They are hardwired control unit and
microprogrammed control unit. The hardwired CU is implemented with gates, flip-flops,
decoders and other digital circuits. The advantage of hardwired CU is that it produces a fast
mode of operation. The microprogrammed control unit (CU) consists of a control memory in
which the control information called as microinstructions are stored. These micro instructions
are executed to generate the required control signal.
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A hardwired control unit for a basic computer is shown below:
Fig: Iiiiiiiii
In the figure above, a hardwired CU is shown which consists of two decoders, a sequence
counter, and a number of control logic gates. An instruction read from memory is placed in
Instruction Register. The instruction is divided into three parts- the I bit, the opcode, and
operand bits 0 through 11. The opcode in bits 12 through 14 are decoded with a 3x8 decoder.
The outputs of decoder is designated as D 0. Through D 7 .Bit 15 is sent to the flip-flop I. Bits 0
through 11 are applied to control logic gates. The outputs of the 4 bit counter are decoded into
16 timing signals T0 to T15. All these decoded outputs, output of flip-flop and the bits 0 through
11 of instruction Register are sent to control logic gates that generates the required control
signal output.
Computer Instructions:
The basic computer has three instruction code formats. They are as follows:
i.
Memory-reference instructions:
The memory-reference instructions uses 12 bits to specify an address and one
bit to specify the addressing mode I. I is 0 for direct address and 1 for indirect
address. The opcode part contains 3 bits.
Fig: wer
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ii.
Register-reference instructions:
It specifies an operation on Register. The leftmost four bits are used to satisfy
opcode and Remaining 12 bits are used to specify register. The leftmost bit is
always 0.
Fig: Register-reference instructions
iii.
Input-Output Instructions:
An input-output instructions does not need a reference to memory and is
recognized by the operation code 111 with a 1 in the leftmost bit of the
instruction. The remaining 12 bits are used to specify the type of input-output
operation to be performed.
Fig:iuo
Instruction Cycle:
The program is executed in the computer by going through a cycle for each instruction.
Each instruction cycle is subdivided into a sequence of subcycles or phases. The instruction
cycle of a basic computer consists of following phases:
Fetch the instruction from memory
Decode the instruction
Read the effective address from memory if the instruction has an indirect
address.
Execute the instruction
iv.
After the completion of step(iv) the control goes back to fetch, decode, and so on. The process
continues unless a HALT instruction is encountered.
i.
ii.
iii.
i.
Fetch Stage:
The process fetches the instruction shown by the program counter(PC). In this
stage, the AR(Address Register) is loaded with the content of PC. Then, Instruction
Register(IR) is loaded with the content of memory location shown by AR. Then PC is
incremented by 1. The micro operations involved in fetch stage are shown below:
AR<- PC
IR<- M[AR], PC<-PC+1
ii.
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Decode Stage:
In this stage, the content of IR is decoded to determine the opcode, operand and
Addressing mode.
D0 ………D7 <- Decode IR(12-24), AR<- IR(0-11), I<- IR(15)
iii. Determine the type of Instruction
In this stage, the control unit determines the type of instruction that was just read
from memory. The instruction may be of Register Reference instruction, memory-reference
instruction and I/o instruction.
iv. Execution stage:
In this stage, the processor performs the actual operation and produces the Result.
After completion of this stage, the processor again fetches the next instruction as
shown by PC and undergoes through all these stages. The processor continues this
process until a HALT instruction is encountered.
1. Memory Reference Instruction:
The different types of memory-reference instructions are listed below:
Symbol:
Symbolic Description
AND
AC<- AC ^ M[AR]
ADD
AC<-AC+ M[AR], E<-Cout
LDA
AC<- M[AR]
STA
M[AR]<-AC
BUN
PC<- AR
BSA
M[AR] <- PC, PC<- AR+1
ISZ
M[AR]<- M[AR]+1, if M[AR]+1 =0 then PC<- PC+1
1. AND to AC:
It performs the AND operation on the contents in AC and the memory
word specified by the effective address.
The micro-operations that execute the instruction are :
DR<- M[AR]
AC <- AC ^ DR, SC <- 0
2. ADD to DC:
This instruction adds the content of memory word specified by the
effective address to the value of AC. The sum is transferred into AC and carry to E flipflop.
DR <- M[AR]
AC<- AC+DR, E<- Cout, SC<-0
3. LDA (load to Accumulator):
the effective address to AC:
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This instruction transfer the memory word specified by
DR <- M[AR]
AC <- DR, SC <- 0
4. STA (store AC):
This instruction stores the content of AC into the memory word
specified by the effective address.
M[AR] <- AC, SC<- 0
5. BUN (Branch Unconditionally):
This instruction transfer the program to the instruction specified by the effective address.
PC <- AR, SC <-0
6. BSA ( Branch and Save Return Address): This instruction is useful for branching to
a portion of the program called subroutine or procedure. When executed, the BSA
instruction stores the address of the next instruction in sequence( Available in PC) into
a memory location specified by the effective address. The effective address plus one is
transferred to PC to serve as address of the first instruction in subroutine.
M[AR] <- PC, PC <- AR +1
Example of BSA:
The BSA instruction is at memory address 20. The I bit is 0 and the
address part of instruction I s135. The PC contains 21 which is the address of next
instruction in program AR holds the effective address 135. The BSA instruction then
performs the following operation.
M[AR] <- 21, PC<- 135 + 1=136
The return address 21 is stored in 135 and control continues with
subroutine starting from 136.
The return to the original program is accomplished by means of BUN
instruction. When this BUN instruction is executed, the control goes to read the location
135 where it finds previously saved address 21. Then, this address 21 is transferred to
PC.
Fig: Example of BSA instruction execution
M[AR] <- PC
AR <- AR+1
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After the completion of subroutine, the following micro-operation is performed.
PC <- AR, SC<-0
7. ISZ ( Incremented and Skip if Zero): to skip one instruction in between
This instruction increments the word by the effective address and if the
incremented value is equal to 0, PC is incremented by 1.
DR <- M[AR]
DR <- DR + 1
M[AR]<- DR, if (DR=0) then (PC <- PC +1), SC<- 0
FLOWCHART FOR MEMORY REFERENCE INSTRUTION:
A complete flowchart showing all micro-operations for the execution of seven memory
reference instructions are shown below:
Fig: Flowchart for memory reference instruction
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Input-Output Configuration:
This terminal sends and receives information. The serial information from the
keyboard is shifted into the input register INPR. The serial information for the printer is stored in
the o/p register OUTR. These two registers (INPR and OUTR) communicates with a
communication interface serially and with the AC(Accumulator) in parallel. The input-output
configuration is shown in figure below:
The transmitter interface receives serial information from the keyboard and
transmits it to the INPR. The receiver interface receives information form OUTR and sends it to
the printer serially.
Fig: Input-output configuration
The FGI is a 1 bit input flag. The flag bit is set to 1 when new information is available in
the input device and is cleared to zero when information is accepted by the compiler.
The OUTR works similarly but the direction of information flow is reversed. The output
flaf is set to 1. If FGO is 0, the output device accepts the information, and prints the output and
when operation is completed, FGO is set to 1.
INTERRUPT:
When a processed is executing an instruction( or a program) and a user controls the
processor to execute another I/O instruction(or program), it is said to be interrupt. When the
interrupt is enabled, the processor stop its program and starts to handle the interrupt provided
by the user.
Interrupt is a disturbance to the processor
Interrupts are handled in interrupt cycle
INTERRUPT CYCLE:
●
●
The interrupt cycle is a hardware implementation of a branch and save return address
operation. The return address available in PC is stored in specific location where it can be found
later when the program returns to the instruction at which it was interrupted. The flowchart for
interrupt cycle is show below:
Fig: flowchart for interrupt
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When interrupt flip-flop(R) is equal to 0, the computer goes through instruction cycle.
During execution phase of instruction cycle, the control checks the IEN flag. If IEN is 0, then the
control continues with next instruction. If IEN is 1, then flip-flop R is set to 1 and the control goes
to interrupt cycle instead of instruction cycle.
The content of PC is stored in specific location ‘0’. The control then inserts the
address ‘1’ of the interrupt (new program) into PC. The control clears the IEN and R to 0 so that
no more interruption occur. After the completion of the interrupt, the processor then continues
with the program that was under execution before interrupt.
Example to demonstrate what happens during Interrupt cycle:
Suppose the interrupt occurs while processor is executing instruction at 255. At this time,
the PC has address of 256. The programmer has previously placed an input-output service
program in memory starting from 1120 and a BUN 1120 instruction at address 1.
When the interrupt is enabled, the content of PC(256) is stored in address 0. Then the
content of PC is incremented by 1. i.e. PC=1. The branch instruction at address 1 causes the
program to address 1120. Once the interrupt is processed, the program returns to the location
where it was interrupted.
Fig(a): Before Interrrupt Cycle
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Fig(b): After interrupt cycle
DESIGN OF BASIC COMPUTER:
The basic computer consists of the following hardware components.
A memory unit with 4096 words of 16 bits each.
Seven flip-flops: I, S, E, R ,IEN, FGI, FGO
Nine Registers AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Two decoders: 3x8 operation decoder and 4x16 timing decoder
A 16 bit common bus
Control Logic Gates
Adder and logic circuit connected to the input of AC
The functional clock diagram of a simple basic computer is shown below:
●
●
●
●
●
●
●
Fig: functional block diagram of basic computer
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Design of Accumulator Logic:
Fig: circuit of Associated with Accumulator
The accumulator logic circuit consists of Adder and logic circuits which has three set of inputs.
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One set of 16 inputs comes from the data Register DR, and another set of 16 inputs comes form
input register INPR. The outputs of adder and logic circuit provide the data inputs for registers.
The control logic LD, INR and CLR are used for controlling the operation of Adder and logic
circuit.
CHAPTER-6 Microprogrammed Control Unit
A microprogrammed control unit consitsts of a control memory in which micro instructions are
stord in it. The block diagram of micro programmed control unit is shown below:
Fi: micro programmed control organization
The control memory is usually a ROM within which all control information is
permanently stored. The control Address Register (CAR) specifies the address of the micro
instruction, and the control data Register holds the micro instruction read from memory. The
micro instruction contains a control word that specifies one or more micro operations for the
data processor. Once these operations are executed, the control must determine the next
address for this reason, some bits of the present micro instruction is used for the generation of
next address. The next address is generated by address generator circuit and then transferred
into control Address Register (CAR) to read the next micro instruction.
The next address generator is also called as micro program sequencer as it
determines the address sequence that is required from control memory.
For understanding :fig:kkkk
Control Memory:
A micro programmed control unit consists of two memory- main memory and
control memory. The main memory is available for storing user programs. The control memory
holds a fixed micro program that cannot be altered by the occasional user.
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Address sequencing:
Address sequencing circuit must be capable of sequencing the micro instructions
within a routine and must be able to brach from one routine to another. The capabilities that an
address sequencing must have as follows:
Incrementing of the control address register (CAR)
Unconditional or conditional branch, depending on status bit conditions
A mapping process from the bits of the instructions to address for control
memory
● A facility for subroutine call and return
The figure below shows a block diagram of a address sequencer and the various
operations included in address sequencing are discussed in detail as follows:
●
●
●
Fig: Selection of address for control memory
The operation of Address sequencer for selection of address for control memory is
discussed below:
Incrementing:
The micro-instruction in control memory contains a set of bits to initiate
micro-operation. The incrementer increments the content of the CAR (Control
Address Register) by one to select the next micro instruction in sequence.
Branching:
Branching may be conditional and unconditional branching. The status
bits together with the field in the micro instruction that specifies a branch address,
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controls the conditional branch decisions generated in the branch logic.
An unconditional branch instructions can be implemented by loading the
branch address from the control memory into the CAR.
Mapping of instructions:
The bits of the instruction specify the address of a mapping ROM. The
content of the mapping ROM gives the bits for the CAR. Because of mapping, the
microprogram routine that executes the instruction can be placed in any desired
location in control memory.
Fig: mapping of instruction code to micro instruction address
Subroutines:
Subroutines are program that are used by other routines to accomplish a
particular task. Microprograms that use subroutines must have a provision for storing
the return address during a subroutine call and restoring the address during a
subroutine return.
MICROPROGRAM EXMPLE:
The code generation technique for the control memory is called micro
programming. It is similar to machine language programming. The format of a micro
instruction is shown below:
Fig: microinstruction code format
The fields F1, F2, and F3 specify micro operations for the computer. Each field
consists of three bits. This gives a total of 21 microoperations. The BR field
specifies the type or branch to be used. The AD field contains branch address. The
CD(condition) field consitsts of three bits which are encoded to specify four status
bits conditions. When this condition is used in conjuction with BR, it provides an
unconditional branch operations.
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F1
Microoperations
Symbol
000
None
NOP
001
AC<-AC+DR
AR
010
AC<-0
CLR AC
011
AC<-AC+1
INC AC
100
AC<-DR
DRT AC
101
AR<-DR(0-10)
DRT AR
110
AR<-PC
PCT AR
111
M[AR]<-DR
WRITE
Table: symbol and code for arithmetic microoperation
Design Of Control Unit:
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The input logic circuit has three inputs I0, I1, T and three outputs s0, s1 and L. s1 and
s0 selects one of the source address for CAR. L enables the load inputs in SBR. The
binary values of two selection variables determines the path in the multiplexer.
The truth table can be obtained as follows:
Input
MUX 1
Load SBR
BR
I1
I0
T
S1
S0
L
This truth table can be used to obtain the simple Boolean function for the logic circuit.
S1 = I1
S0= I1I0 +I1’ T
L= I1’ I0 T
Chapter-7
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Central Processing Unit
General Register Organization:
Processor consists of mainly two types of Registers”
User-visible Registers
Control & status Registers
1. User – visible Registers:
User-Visible registers can be referenced by means of the machine language that the
processor executes. The different user-visible Registers are discussed below:
●
●
I.Genereal Purpose Register:
These registers can be assigned to a variety of functions by the
programmer. Eg> B, C, D, E,H, L are general purpose registers in 8085
II. Data Register:
Data Registers are used to hold data and cannot be employed in the calculation
of an operand Address.
iii. Address Registers:
Address Registers are denoted to a particular addressing mode. Examples of
address register are:
a. Segment Register: It holds the address of the base of the segment.
b. Index Register: This Register is used for indexed addressing and may be
autoindexed.
c. Stack point(SP): This register points the top of the stack
d. Condition Codes Registers: Condition codes Registers hold the condition
codes set by the processor as the result of operation. For eg. Zero,
overflower
2. Control and Status Registers:
These Registers are used to control the operation of the processor. Examples of
these registers are:
i. Program counter(PC): It contains the address of the instructions to be
fetched.
ii. Instruction Register(IR): It contains the instruction of most recently
fetched.
Memory Address Register(MAR):It contains the address of a
iii.
location in memory.
Memory Buffer Register(MBR): It contains a word of data to be
iv.
written to memory or the word most recently used.
Most processors include a Register known as PSW(program status word)
that contains condition codes and other status information. For examplesign, zero, carry, overflow, interrupt enable/disable etc.
STACK ORGANISATION:
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A stack is a storage device that stores information such that the item stored last
is the first item retrieved. So, a stack is a last-in-first-out(LIFO) list. The two operations of a
stack are PUSH and POP. A PUSH operation appends one new item to the top of the stack.
APOP operation removes (or deletes) the top item from the stack. The operation which requires
two operand (eg. ADD, MULTIPLY, DIVIDE etc.) use the two stack items as operands, POP
both items and push the result back into the stack. Operations which requires only one operand
use the item on the top of the stack.
STACK POINTER(SP): It contains the address of the top of the stack.
STACK BASE: It contains the address of buttom location. If the POP operation is used when the
base is empty, an error is occurred.
STACK LIMIT: It contains the address of the other end. If PUSH operation is used when the
block is fully utilized, an error is reported.
#Evaluate f=(a-b)/c +(d*e) using stack oriented instruction OR Wap in assembly language for
evaluating f=(a-b)/ c+(d*e) using stack oriented instructions.
Infix Notation: The operator is written between the operand. Eg. A+B
Prefix Notation: It is also reffered as POLISH NOTATION. The operator is placed before the
operands. Eg. +AB
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Postfix Notation: It is also preffered as reverse polish notation. The operator is placed after the
operands. Eg. AB+
CONVERSION OF INFIX NOTATION TO REVERSE POLISH NOTATION (POSTFIX
NOTATION):
The steps for converting infix into postfix notation is listed below:
a.
b.
c.
d.
Examine the next elements in the input
If it is operand, output it
If it is an opening parenthesis (bracket), push it onto the stack
If it is an operator , then
-if the top of stack is an opening parenthesis, then push the operator
-if it has a higher priority than the top of the stack, then push the operator
-else pop operation from stack to output and repeat step(d)
e. If it is closing parenthesis, pop operations to output until an opening parenthesis is
encountered POP and discard the opening parenthesis.
f. If there is no more input, unstuck the remaining operands
#convert A+B*C+(D+E)*F into reverse polish notation.
Instruction Formats:
A computer will always have a variety of instruction formats. The most common field found in
instruction format are:
a. An operation code (opcode) that specifies the operation to be performed.
b. An address field that designates a memory address or a processor register.
c. A mode field that specifies the way the operand or the effective address is determined.
Three Address Instruction:
ADD R1, A,B
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R1->A+B(COMMENTS)
ADD R2, C, D
R2-> C+D
MUL X, R1, R2
X->R1*R2
Two Address Instruction:
MOV R1, A
ADD R1, B
MOV R2, C
ADD R2, D
MUL R1, R2
MOV X, R1
One Address Instruction:
LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X
Zero Address Instruction:
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X
# Evaluate the arithmetic statement X= (A+B) *(C+D) using three address, two address, one
address, and Zero-Address instructions.
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Addressing Mode:
The use of addressing Mode gives the programmer flexibility for writing programs that
are more efficient with respect to the no. of instructions and execution time. The different types
of addressing modes are discussed below:
a. Implied Mode:
In this mode, the operands are specified implicitly in the definition of the
instruction. For eg. Complement accumulator is and implied mode instruction.
ii.
Immediate mode:
In this mode, the operand is specified in the instruction itself . The operand field
contains the actual operand value to be used.
Eg. Add 02H, 03H
iii. Register mode/Register Direct Mode:
In this mode, the operands are in Register that resides within the CPU.
(R1+R2)
iv. Register Indirect Mode:
In this mode the instruction specifies a Register in CPU whose content give the
address of the operand in memory. The selected Register contains the address of
operand rather than operand itself.
v.
Auto Increment or Auto Decrement Mode:
It is similar to indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory.
The address field of an operand is used to obtain operand from memory. The
effective address is defined to be memory address is defined to be memory address
obtained from the computation dictated by the given address mode.
vi.
Direct Addressing Mode:
In this mode, the effective address is equal to the address part of instruction. The
operand’s address is given directly by the address field of instruction.
vii. Indirect addressing Mode:
In this mode, the addess field of instruction gives the address where the effective
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address is stored in memory.
viii. Relative address mode:
In this mode, the content of program counter(PC) is added to the address part of
the instruction in order to obtain the effective address.
ix. Indexed addressing Mode:
In this mode the content of an index Register is added to the address part of
instruction to obtain the effective address.
x.
Base Register Addressing Mode:
In this mode, the contents of Base Register is added to the address part of the
instruction to obtain the effective address.
DATA TRANSFER MANIPULATION:
Data Instruction can be classified into three main categories. They are:
i. Data Transfer Instruction
ii. Data Manipulation Instruction
iii. Program control Instruction
i. Data Transfer Instruction:
Data transfer instruction move data from one place in the computer to
another without changing the data content. The most common transfer are between memory
and processor Register I/o. The example of data transfer instruction are Load, Store, Move,
input.
Data Manipulation Instruction:
Data manipulation instruction perform operations on data and provide the
computerized capabilities for the computer. The data manipulation instruction are divided into
various types as follows:
ii.
a. Arithmetic Instruction: The arithemetic instruction perform the arithmetic
operations like addition, substraction, multiplication and division.
b. Logical and bit manipulation instruction : Logical and bit manipulation instruction
perform the logical operations on strings of bits stored in Register. They are
useful for manipulating individual bits or group of bits that represent binary coded
information. The example of logical operations are AND, OR, XOR etc.
c. Shift Instruction: Shift instruction shift the content of the operands in several
variations. In shift operations, the bits are shifted to the left or right. The example
of left, right, arithmetic shift left, arithmetic right shift, rotate left, rotate right etc.
III. Program control Instruction:
Program control instruction control the operations of processor. Program
control instructions specify condition for altering the content of the program
counter. The example of program control instruction are branch, skip, procedure
call and Return etc.
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RISC AND CISC:
A computer with a large number of instructions is classified as a compled instruction set
computer(CISC).
A computer that uses few instruction with simple constructs is classified as Reduced
Instruction Set Computer(RISC).
CHARACTERISTIC OF CISC:
A large no. of instructions (100 to 250).
Some instructions perform specialized tables and are used infrequently.
A large variety of addressing modes.
Variable length instruction format
Instruction that manipulates operands in Memory
Microprogrammed control unit
CHARACTERISTIC OF RISC:
I.
II.
III.
IV.
V.
VI.
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
ix.
x.
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Relatively few instructions
Relatively few addressing modes
Memory access limited to Load and store instruction
All operations done within the Registers of CPU.
Fixed length easily decoded instruction format.
Single cycle instruction execution
Hardwired Control unit
Relatively large no. of Registers in CPU
Efficient Instruction pipeline
Compiler support for efficient translation of high level language program into
machine language program.