How to Read the Voltage and Frequency on SCC
How to Read the Voltage and Frequency on SCC Table of Contents 1 Introduction.............................................................................................................................. 1 2 Telnet into the BMC to Read Voltages .................................................................................... 1 3 Use the sccGui to Obtain SCC Voltages .................................................................................. 3 4 Use the sccGUI to Read Frequency ......................................................................................... 4 5 Read the Tile Frequency with an SCC Program ...................................................................... 6 1 Introduction The SCC platform provides two methods for obtaining the voltages and frequencies of the SCC cores. The first involves telnetting into the SCC’s board management controller (BMC). The second uses the sccGui. 2 Telnet into the BMC to Read Voltages You can obtain voltage information about the SCC board from the Management Console. From a prompt on the Management Console, type the command telnet <name of your SCC Platform> 5010 The name of your SCC platform is assigned to the platform when you receive it. There is no command you can use to get that name. You can also use the IP address of the board management controller (BMC) located on the SCC board. The IP address is listed in the file systemSettings.ini in /opt/sccKit. Do not edit this file. Both the name and IP address are also written on a sticker attached to the BMC. YourUserName@MCPCname:/opt/sccKit$ cat systemSettings.ini [General] CRBServer=ip_address:5010 memorySize=8 platform=RockyLake tekubasx@mrllab1003:/opt/sccKit$ YourUserName@MCPCname:~$ telnet ip_address 5010 Trying ip_address... Connected to ip_address. Escape character is '^]'. *********************************************************************** Thursday, June 10, 2010 Page 1 of 7 Intel Labs ____ ____ ____ _ _ _ _ |__/ | | | |_/ \_/ | \ |__| |___ | \_ | ____ [__ ___] ____ | |___ ____ | |___ _ | |___ _ ____ _ _ ____ | |__| |_/ |___ |___ | | | \_ |___ ___ ____ ____ ____ ___ |__] | | |__| |__/ | \ |__] |__| | | | \ |__/ ____ ____ _ _ _ ____ _ ____ ____ | __ [__ | |\ | | __ | |___ __ | |___ ___] | | \| |__] |___ |___ |___ ____ _ _ ___ ____ ____ _ _ ___ _ _ ___ _ | | | | | \ | | | |\/| |__] | | | | |__| |__| |__/ |___ |__| | | | |__| | | _ _ |__| | | _ _ |\ | | \| _ ___ | |__] | | ____ | __ |__] *********************************************************************** © Copyright 2010 by Intel Corporation Intel Labs - Germany Microprocessor Lab Software: CPLD: HW-ID: POWR1220: DDR3 modules: 0.12 Build: 1120 Apr 8 2010 13:50:27 1.07 0x00 0xC0000001 (master), 0x40000001 (slave) Present: 0 1 2 3 4 5 6 7 Welcome to the BMC server of bwlsccrlb05! You are participant #1 ]> ]>status Power Status = 0xCF3F, ON Standby supplies: 5V0PWR: 4.980 V (Primary) 1V8SB: 1.802 V (Secondary) 3V3PWR: 3.256 V -"Primary supplies: 3V3IN: 3.360 V 5V0IN: 5.054 V 12V0R1: 11.933 V 12V0R2: 11.933 V Secondary supplies: 1V0: 1.022 V 1V1VCCA: 1.106 V 1V1VCCT: 1.100 V 1V5: 1.524 V 1V65: 1.696 V 1V65ADJ: 1.652 V 1V8PHY: 1.804 V 2V5: 2.480 V 3V3: 3.328 V 3V3SCC: 3.292 V Tertiary supplies: OPVR VCC0: 1.1109 OPVR VCC1: 1.1117 OPVR VCC2: 1.1136 OPVR VCC3: 1.1169 OPVR VCC4: 1.1099 OPVR VCC5: 1.1106 OPVR VCC7: 1.1106 1.380 2.250 3.219 7.713 A A A A 1.470 A 10.495 A V V V V V V V Temperatures: Board: 36 °C FPGA: 35 °C Fan speed: FPGA: SCC: 1 RPM (Needs real conversion to RPM!) 255 RPM Misc.: FPGA status: 0xC7 Thursday, June 10, 2010 Page 2 of 7 Intel Labs Lane Good LED is off L0: normal operation CPLD status: 0x47 PLL is locked. PLL lock lost is cleared. ]> The SCC has eight voltage domains. These are listed under Tertiary supplies. The voltage domains are listed as VCC0 through VCC7. Note that in the status output there is no VCC6. This is because VCC2 and VCC6 are the same. These two domains include the entire mesh and the system interface. The other six voltage domains represent 2x2 tile arrays. V0 is the voltage domain in the upper left. The voltage domain increments as you move to the right, skipping V2. The voltage domains in the upper row are V0, V1, V3. The voltage domains in the lower row are V4, V5, and V7. Note that V6 is skipped The numbering of the voltage domains shown here is the hardware numbering. It is not the same numbering used by RCCE software. 3 Use the sccGui to Obtain SCC Voltages On the MCPC, invoke the sccGui as sccGUI&. Then select BMCGet board status. The sccGui then displays the same information as the BMC status command. Figure 1 shows how to select Get board status, and Figure 2 shows the result of that operation. Figure 1: Selecting BMC Get board status Thursday, June 10, 2010 Page 3 of 7 Intel Labs Figure 2: Result of Selecting BMC Get board status 4 Use the sccGUI to Read Frequency On the MCPC, invoke the sccGui as sccGUI&. Then select WidgetsFlit widget (NC reads and writes). Figure 3 shows how to select Flit Widget, and Figure 4 shows the result of that operation. To read the frequency of a tile, select the tile’s (x,y) coordinates from the Route info dropdown box. Then, select CBR for the configuration registers and then GCBCFG for global clocking configuration. Click on the Read button. Click on Done to exit the Send Flit via SystemIF window. Figure 3: Selecting Widgets Flit widget Thursday, June 10, 2010 Page 4 of 7 Intel Labs Figure 4: Result of Selecting Flit Widget There is a GCBCFG register for each tile. You can set the frequency of each tile independently. Note that RCCE software sets the frequency for all the tiles in a voltage domain simultaneously and does not currently provide the ability to set the frequency for an individual tile. The example shows a result of a8e2f0. These are the bits in the tile’s GCBCFG register. The register is 26 bits; leading zeros are not shown. The bits you are interested in are bits 25:08 and they are shown in Table 1 and Table 2. The router clock is initially set at either 800MHz or 1.6GHz. You chose a value when you booted Linux on the cores with either sccGui or sccBoot. When the router frequency is 800MHz, the default tile frequency is 533MHz. When the router frequency is 1.6GHz, the default tile frequency is 800MHz. Table 1 lists the possible tile frequencies when the router clock is 800MHz. Table 2 lists the possible tile frequencies when the router clock is 1.6GHz. The hex value a8e2f0 is binary 1010 1000 1110 0010 1111 0000, and corresponds to a router frequency of 800 MHz and a tile frequency of 533 MHz. Thursday, June 10, 2010 Page 5 of 7 Intel Labs Tile Frequency (MHz) GCU Config Setting [25:08] 00 0111 0000 1110 0001 800 00 1010 1000 1110 0010 533 00 1110 0000 1110 0011 400 01 0001 1000 1110 0100 320 01 0101 0000 1110 0101 266 01 10001 000 1110 0110 228 01 11000 000 1110 0111 200 01 11111 000 1110 1000 178 10 00110 000 1110 1001 160 10 01101 000 1110 1010 145 10 10100 000 1110 1011 133 10 11011 000 1110 1100 123 11 00010 000 1110 1101 114 11 01001 000 1110 1110 106 11 10000 000 1110 1111 100 Table 1: Tile Frequency Settings for Router Clock of 800 MHz Tile Frequency (MHz) GCU Config Setting [25:08] 00 0111 0000 0111 0001 800 00 1010 1000 0111 0010 533 00 1110 0000 0111 0011 400 01 0001 1000 0111 0100 320 01 0101 0000 0111 0101 266 01 1000 1000 0111 0110 228 01 1100 0000 0111 0111 200 01 1111 1000 0111 1000 178 10 0011 0000 0111 1001 160 10 0110 1000 0111 1010 145 10 1010 0000 0111 1011 133 10 1101 1000 0111 1100 123 11 0001 0000 0111 1101 114 11 0100 1000 0111 1110 106 11 1000 0000 0111 1111 100 Table 2: Tile Frequency Settings for Router Clock of 1.6GHz 5 Read the Tile Frequency with an SCC Program You can read the GCBCFG register for a tile from within a program that runs on the cores. A core can read its own GCBCFG register as well as the GCBCFG registers of other cores. Do this with memory-mapped I/O. The address you use depends on the settings in the SCC lookup Thursday, June 10, 2010 Page 6 of 7 Intel Labs tables (LUTs). The SCC External Architecture Specification lists the default values of the lookup tables. A tile’s LUT determines a base address for a tile’s configuration registers. You select an individual register by adding an offset to this base address. The SCC Programmer’s Guide lists a sample program that reads the TileID register. Both the SCC External Architecture Specification and the SCC Programmer’s Guide are available for download from the following website. http://communities.intel.com/index.jspa Click on Many-core Applications Research Community in the left navigation pane. Thursday, June 10, 2010 Page 7 of 7 Intel Labs
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