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1
Appendix 1
What is a Phase Locked Loop?
A phase locked loop is a circuit that synchronizes the signal from an oscillator
with a second input signal, called the reference, so that they operate at the same
frequency. The synchronized oscillator is commonly a Voltage Controlled Oscillator
(VCO). The loop synchronizes the VCO with the reference by comparing their phases
and controlling the VCO in a manner that tends to maintain a constant phase
relationship between the two. In some types of Phase Locked Loops this phase
relationship is held constant. In other types it is allowed to vary somewhat. But the
frequency is always synchronized. Otherwise the loop is said to be “out of lock.”
a. The basic control loop
A block diagram of the basic PLL is shown in Fig. 2-30. While the synchronized
oscillator is usually a VCO, one whose frequency changes in response to a control
voltage, u2, it is also possible that u2 could be a current and the synchronized oscillator
would thus be a current-controlled oscillator (ICO).
ω out
u1 = K p ( φ in − φ out − Θ )
φ in +
Phase
Detector
-
Figure 2-30
Loop
Filter
φ out
u2
VCO
s-1
Basic Phase Locked Loop.
However, we will consider it a VCO - the transition between the two is easily
understood.
The Phase Detector compares the reference to the VCO’s output and produces a
signal u1 which varies in proportion to the difference in their phases. This is processed
2
by the loop filter to provide the oscillator control signal u2. The loop filter can be as
simple as a conductor (u1=u2) or a wideband amplifier (u2=KLFu1), but it is usually
designed to provide some advantageous response characteristic. If the output frequency
ω out =
dφout
dφ
ω in = in
dt , should be greater then the reference frequency
dt , then
u 1 ∝ (φ in − φ out − Θ ) would necessarily decrease with time, causing u2 to decrease,
which, in turn, would cause
ω out to decrease, bringing ω out down toward ω in . Thus
the PLL provides the negative feedback to keep the output frequency
reference frequency
ω out equal to the
ω in . The output amplitude Ao is constant and independent of the
input amplitude Ai.
b. PLL components.
b.1 Phase detector.
Two broad categories of Phase Detectors (PDs) can be distinguished: multiplier
circuits, and sequential circuits. The multiplier circuit generates a useful DC error
output as the average product of the input signal waveform times the local oscillator
waveform.
A sequential phase detector generates an output voltage which is a function of
the time interval between a zero crossing on the VCO waveform and a zero crossing on
the signal. Other details of the waveform do not contribute to the output.
Sequential PDs are usually built up from digital circuits (flip-flops, gates) and
operate with binary, rectangular input waveforms. Accordingly they are often called
"digital" phase detectors and the loops with such PDs are called "digital" phase locked
3
loops. This terminology is incorrect: the output of a sequential PD is an analog quantity
and the loops are analog loops.
b.1.1 Multipliers
If both inputs to an ideal multiplier are sinusoidal, the useful DC output is
proportional to the product of the amplitudes of the two inputs and two cosines* of the
phase difference between them. The multiplier produces the scalar product of the two
input phasors.
A sin (φ )B sin (φ + θ ) =
AB
AB
cos(θ ) +
cos(2φ + θ )
2
2
(2-
68)
In addition, there is an unwanted, sinusoidal ripple at double frequency and with
amplitude equal to the maximum available DC output level. Ripple must be suppressed
to prevent unwanted sidebands from appearing on the VCO.
Multiplication can be implemented physically by means of a four-quadrant
analog multiplier. Such devices are available as monolithic ICs or as encapsulated
packages or can be built from discrete devices.
Good performance can be obtained, although usable operating frequencies tend
to be low and cost tends to be high.
A true multiplier provides a useful analytical model for a phase detector, but it is
rarely found in actual equipment.
Instead, a switching phase detector is far more popular. (Fig.2-31, Fig. 2-32.)
* The phase difference is 90° when the phase is zero.
4
Signal
Input
SW
out
Drive
Figure 2-31
The switching phase detector.
Figure 2-32
Input and output waveform of the switching Phase Detector.
b.1.2 Sequential phase detectors.
This important class of circuits operates on the zero crossings of the signal and
local oscillator; any other characteristics of the waveforms are ignored. For reliable
operation of the circuits, the waveforms are usually clipped to a rectangular shape.
Average output is proportional to the time interval between a level transition of
the signal and a transition of the VCO waveform. The circuit must have some memory
to measure the time difference.
The simplest sequential PD is an ordinary RS flip-flop. Negative transitions on
one unit set the flip-flop to a true state and negative transitions on the other input reset it
to the false state. Typical waveforms are shown in Fig. 2-33.
5
Θd = π
Θd = 0
Θd =
Θd =
Figure 2-33
π
2
3π
2
Output of the RS flip-flop phase detector - the phase
difference between the input signal and VCO output.
The average voltage DC output:
VH
Figure 2-34
VH
2
The average DC output of RS flip-flop versus Phase
difference.
o
The linear range is centered at Θ d = 180 , rather that at 90 as found in
o
multiplier PDs.
o
Equilibrium tracking is ordinarily centered on 180 , so the DC offset of VH/2
must be canceled out with an appropriate bias circuit.
b.1.3. Exclusive OR gate phase detector
6
A
C
B
Figure 2-35
Exclusive OR logic gate.
A
B
Out
Figure 2-36
EXOR waveforms: A, B are input waves of Phase Detector,
Out-output wave.
The EXOR phase detector is the simplest phase detector or Type I (digital),
which is simply an exclusive-OR gate. With lowpass filtering, the graph of the output
voltage versus phase difference is as shown on Fig. 2-37, for input square waves of 50%
duty cycle.
Vavg
π
0
Figure 2-37
π
2
Average Output voltage of XOR phase detector versus phase
difference of the input square waves with 50% duty cycle.
7
b.1.4. Phase-frequency detector (PFD)
The Phase-frequency detector is another type of the phase detector. Its name
means that this phase detector also provides an indication of frequency error when the
loop is out of lock.
UB
“1”
D
U
Q
P
FF
Cp
u1
CD
ud
CD
D
D
Q
N
FF
u2’
Cp
Three-state
Figure 2-38
Schematic diagram of the Phase-frequency detector.
The PDF has two output terminals, labeled U and D. Both U and D can be
“Low” simultaneously, but not “high”. Whenever both flip-flops are in the 1-state, a
logic “high”-level appears at their CD (“Clear Direct”) inputs which resets both flipflops. Consequently the devise acts as tristable device (“triflop”). Let us assign the
symbols -1, 0, and 1 to these three states:
U
D
ud
0
0
0
0
1
-1
1
0
1
Table 2-2
Triflop states.
To see how the PFD works in a real DPLL system, consider the waveforms in
Fig. 2-39. Figure. 2-39(a) shows the (rather theoretical) case where the phase error is
zero. It is assumed that the PFD has been in the “0” state initially. Signals u1 and u2 are
8
“exactly” in phase here; both positive edges of u1 and u2 occur “at the same time”;
hence their effects will cancel. The PFD will then stay in the “0” state forever.
u1
u2
PFD
State
+1
u2
-1
(a)
u1
u2
+1
PFD
State
(b)
9
u1
u2
(c)
PFD
State
-1
Figure 2-39
Operation modes of PFD: (a) Θ e = 0 , (b)
Θe = −
Θe =
π
3 , and (c)
π
3.
Figure. 2-39 (b) shows the case where u1 leads u2. The PFD now toggles
between the states “0” and “+1”. If u1 lags u2 as shown in Fig. 2-39 (c), the PFD toggles
between the states “0” and “-1”. A comparison of PFD characteristics (Fig.2-39(c)) with
the characteristics of the flip-flop phase detector (Fig.2-33) does not yet reveal any
exciting properties. To recognize the bonus offered by the PFD, assume that the DPLL
is unlocked initially. Furthermore make assumption that the reference frequency
higher than the output frequency
ω1 is
ω 2 . The signal u1 then generates more positive transi-
tions per unit of time than the signal u2. Looking at Figure 2-39, one sees that the PFD
can toggle only between the states “0” and “+1” under this condition, but never will go
into the “-1” state. If
ω1 is much higher than ω 2 furthermore, the PFD will be in the
“+1” state most of the time. When
ω1 is smaller than ω 2 , however, the PFD will toggle
10
between the states “-1” and “0”. When
ω1 is much lower than ω 2 , the PDF will be in
the “-1” state most of the time. It is concluded therefore that the average output signal ud
of the PFD varies monotonically with the frequency error Δω = ω1 − ω 2 , when the
DPLL is out of lock. This leads to the term Phase Frequency Detector.
a
− 2π 0
− 2π 0
b
− 2π 0
c
Figure 2-40
2π
Θd
2π
Θd
2π
Θd
Plot of the average PFD output signal ud versus phase error
Θd.
ud does not depend on the duty cycle of u1 and u2. (a)
ω1 >> ω 2 , (b) ω1 << ω 2 , (c)
ω1 ≈ ω 2 .
It is possible to calculate the duty cycle of the ud signal as a function of the
ω1
frequency ratio
ω 2 ; the result of this analysis is shown in Fig. 2-41. For the case
ω1 < ω 2 the duty cycle δ is defined by the average fraction of time the PFD is in the
“+1” state; for ω1 > ω 2 , δ is by definition minus the average fraction of time the PFD
is in the “-1” state. As expected, δ approaches “-1” when ω 1 << ω 2 and “+1” when
ω1 >> ω 2 . Furthermore, the δ is nearly 0.5 when ω1 is greater then ω 2 , but both
11
frequencies are close together, and δ is nearly -0.5 when ω1 is lower then ω 2 , but both
frequencies are close together. This property will greatly simplify the determination of
the pull-in range.
1
0.5
1
2
ω1
ω2
-0.5
-1
Figure 2-41
Plot of average duty cycle of the PFD. PFD output signal ud
ω1
versus frequency ratio
ω2 .
This curve depicts the behavior of the PFD in the unlocked state of DPLL.
b.2 Voltage-controlled oscillator (VCO).
The VCO is essential part of every PLL. It operates like a regular oscillator but
its output frequency is a function of the input DC voltage. The amplitude of the output
signal remains constant. There are many requirements placed on VCOs in different
applications. These requirements are usually in conflict with one another, and therefore
a compromise is needed. Some of the more important requirements include the
following:
• Phase stability (Spectral purity).
• Large electrical tuning range.
• Linearity of frequency versus control voltage.
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• Large Gain factor.
• Low cost.
The requirement of phase stability is in direct opposition to the other four
requirements. To obtain any of the wideband features we must inevitably sacrifice phase
stability.
It is not a goal of this work to list all types of VCO and the general principles of
their operation. It is sufficient to remark that it exists in many different types. The VCO
may, in fact, be a current controlled oscillator, an ICO, but in this work attention will be
concentrated on the PLL with a VCO.
Some PLL-ICs include a VCO (e.g. the linear 565 and the CMOS 4046). And
there are separate VCO chips, such as the 4024 (a companion chip to the 4044 TTL
phase detector) and many others.
The main interest here is to present the transfer function of each element of the
PLL. This is especially important when trying to find the close-loop PLL transfer
function.
The real VCO can not be absolutely linear. There is an approximate method
commonly used for linearisation of the output frequency versus control signal function,
as in Fig. 2-42:
13
ω out
Hold-in
range
Frequency
Slope is average
KV over hold-in
range
KLF*PDrange
min u1
Figure 2-42
max u1
Typical VCO tuning curve with the average slope over the
hold in range.
So:
KVCO =
Fmax − Fmin ⎡ 1 ⎤
,
K LF ⋅ PDrange ⎢⎣ sec⋅V ⎥⎦
(2-69)
b.3 Loop filter.
There are two general types of the loop filters:
• Passive loop filter.
• Active loop filter.
The passive loop filter consists of passive elements (R, L, C) and can be of the
first (the case of only one resistor), second or higher order. The loop filter of the first
order is a primitive case. We will consider the filters that give us more flexibility in
controlling the characteristics of the PLL. A general form of the passive filter that we
will discuss is shown in Fig. 2-43.
14
u1
u2
R1
R2
C
Figure 2-43
Passive lag-lead loop filter.
The transfer function of such filter is:
1+
R2 + 1
u (s )
1 + R 2 Cs
1+τ 2s
sC =
F (s ) = 2
=
=
=
u1 (s ) R1 + R2 + 1
1 + (R1 + R2 )Cs 1 + τ 1 s 1 +
sC
s
ωz
s
ωp
where :
τ = 1
1
ω p = (R1 + R 2 ) ⋅ C
and
τ 2 = 1ω = R2 ⋅ C.
z
(2-70)
The gain and phase of F(ω ) are shown in Fig. 2-44.
F( jω )
1
− 20 db dec
ωp
ωz
ωp
ωz
f
0
∠F( jω )
-45°
-90o
Figure 2-44
Gain and phase of the passive loop filter versus frequency,
with tangential gain approximation shown.
If R2->0, this becomes a low-pass (Fig. 2-45) filter with transfer function:
15
F (s) =
1
1
=
1 + R1Cs 1 + s
=
ωp
1
;
1 + τ 1s
where :
τ 1 = 1ω = R1C ;
p
(2-71)
R1
u1
u2
C
Figure 2-45
Low-pass filter.
Its response is as shown in Fig. 2-46.
F( jω )
1
− 20 db dec
ωp =
1
τ1
f
0
∠F( jω )
-45°
-90o
Figure 2-46
Gain and phase of the low-pass loop filter versus frequency,
with tangential gain approximation shown.
The active loop filter can also be of the first, second and higher order. In general
case it can implement equation (2-70), but a wider range of values for ω p and ω z can
be more easily obtained.
Types of active filters:
16
ZFB
u1
Figure 2-47
u2
Ga
R1
General topology of an active filter.
ZBF
KLF*F(s)
NAME
1
R 1Cs
Integrator
C
s
1 1 + ωz
⋅
R 1C
s
ωz ≡ τ2 = R 2C
⎛Rp ⎞
⎜ R ⎟ Z ′FB
⎝
1⎠
⎛Rp ⎞
⎜ R ⎟ R 1 + Z ′FB
⎝
1⎠
Z’FB
Rp
K LF ⋅
C
1
;
1 + sω
p
K LF =
Rp
Rp
R1 ;
ω p = τ 1 = R p C;
1
K LF ⋅
R2
C
filter
1
C
R2
Integrator-and-lead
1+ s
1+ s
K LF =
Control of
Frequency (DC) Gain
Lag (Low-Pass)
filter
ω p ⎞ s + ωz
⎛
⎟
;
= ⎜⎜ K LF
ω z ⎟⎠ s + ω p
⎝
ωp
ωz
Rp
R1
;
(
)
ω p = τ 1 = R p + R2 C;
Lag-lead
1
Rp
ω z = τ 2 = R2C ;
1
Zero-
filter
17
K LF ⋅
C
K LF
R2s
R2p
1 + sω
ωp ⎞ s + ωz
⎛
z
= ⎜ K LF ⎟
;
ωz ⎠ s + ωp
⎝
1+ s
(R
=
ωp
2s
+ R 2p
)
Lag-lead
R1 ;
ωp = τ1 = R 2 pC;
1
R 2s R 2 p
ωz = τ 2 = R + R ⋅ C;
2s
2p
1
Table 2-3
Active filter components.
filter