CECS 201
Computer Logic Design
© 2013 R. W. Allison
Name ______________________________
Verilog Lab #2 ‐‐ Spring 2013 General Statement: You are to create a behavioral verilog module for a “hex-to-seven-segment” decoder module
Verilog HDL language. This will require you to use the Xilinx HDL editor to create the Verilog text file. The file
will define a Verilog module that implements the 7-segment decoder. Once compiled, use the Logic Simulator to
provide stimulus to the inputs and display the outputs to test (verify the validity) of the decoder. The contents of the
file that you are to type in are listed below. Verification of the logic is done via simulation, as in all previous labs.
/**************************************************************
* Name: R. W. Allison
* Date: March 21, 2013
* File: hex_to_7seg.v
*
* Description: Behavioral model of a hex to 7-segment decoder
*
with active-low outputs.
**************************************************************/
//*********************************************************
module hex_to_7seg(hex, a, b, c, d, e, f, g, anodes);
//*********************************************************
input
output
reg
output
wire
[3:0] hex;
a, b, c, d, e, f, g;
a, b, c, d, e, f, g;
[3:0] anodes;
[3:0] anodes;
always @( hex ) begin
case ( hex )
4’b0000: {a,b,c,d,e,f,g}
4’b0001: {a,b,c,d,e,f,g}
:
:
:
:
:
:
4’b1111: {a,b,c,d,e,f,g}
default: {a,b,c,d,e,f,g}
endcase
end
// end of always
assign anodes = 4’b1110;
= 7’b0000001;
= 7’b1001111;
// 7 segment code for 0
// 7 segment code for 1
Fill in the rest of the logic
= 7’b0111000;
= 7’b1111111;
// 7 segment code for F
// 7 segment code for “blank”
//anodes “artificially” coming from this module
endmodule
Deliverables: Create a Test Bench Waveform for simulation, verifying the correctness for all possible 16 combinations for
inputs hex [3:0] (00002 to 11112). Inputs hex[3:0] are to be connected to the FPGA board’s slide switches SW3 to SW0,
respectively; outputs a, b, c, d, e, f, g are to be connected to FPGA led’s CA,CB,CC,CD,CE,CF,CG and outputs
anodes[3:0] are to be connected to FPGA anodes AN3, AN2, AN1, AN0, respectively.
You are to turn in (1) this cover sheet, (2) a printout of the Verilog file and (3) a printout of the simulation.
Due Date:
Tuesday, March 26, 2013
{Tues. of week 10}
Verilog Lab # 2 – Page 1