XIP-5340, XIP-5341 Simultaneous Sample and Hold Analog Input

XIP-5340, XIP-5341
Simultaneous
Sample and Hold
Analog Input
FEATURES
§ Sixteen differential inputs (±10V DC input range)
§ Eight 12 or 14-bit A/D converters with
simultaneous sample and hold capability
§ 8µS conversion time (125KHz) for
8-channel bank
§ FIFO buffer with 512 sample memory
§ Programmable conversion timer
§ Programmable channel conversion control
§ External trigger input or output
§ Continuous and single-cycle conversion
modes
§ Interrupt generation for FIFO threshold
conditions
§ Precision calibration voltages stored
on-board
BENEFITS
§ Simultaneous channel conversion and
on-board memory enable megahertz
throughput rates.
§ Programmable interrupts simplify data
acquisition by providing greater control.
DS-75340(A). 5-00.
XIP-5340 and XIP-5341 Industrial I/O Pack (IP)
modules provide fast, high-resolution, simultaneous
A/D conversion of up to eight channels.
These modules have sixteen analog inputs that
are sampled as two eight-channel banks. Eight A/D
converters (ADCs) permit simultaneous conversion
of all eight channels in a bank. A FIFO buffer holds
the first bank's data while the second bank is converted. Conversion of each bank requires only 8µS,
and all 16 channels can be sampled in just 16µs.
Flexible configuration options give you extensive
control over the conversion process. The channels
or bank to be converted, timing, scan mode, and
other parameters are user-programmable. Interrupt
support adds further control to flag a FIFO that is
full or filled to a user-defined threshold level.
PRODUCT SPECIFICATIONS AND RATINGS
Environmental
Operating
Nonoperating
Thermal
0 to 70°C
-40 to 85°C
Humidity
5% to 95% RH, noncondensing
5% to 95% RH, noncondensing
Isolation
Nonisolated
Nonisolated
RFI resistance
Error <±0.25% of full scale range effect
Designed to comply with IEC1000-4-3 Level 3 and EN50082-1
EMI resistance
Error <±0.5% of full scale range effect
Hardware
IP Compliance (ANSI/VITA 4)
Power
• +5V: 65mA
• +12V from P1: 7mA
• -12V from P1: -6mA
§ Meets IP specifications per ANSI/VITA 4-1995
Input channels
Sixteen differential
Input ranges
±10V
Access times (8MHz clock)
Overvoltage
protection
• VSS -37V to VDD 52V with power on
• -40V to 55V power off
§ ID space read: 0 wait states (250ns cycle)
§ IP data transfer cycle types supported: input/output (IOSel*), ID read (IDSel*), interrupt
select (INTSel*)
Source resistance • 1.0M ohms, minimum (8 chan. only).
• 2.2K ohms, minimum (16 channels at 16µS
conv. rate).
Rejection Ratio
• Common mode (60 Hz): 96dB
• Channel-to-channel (60 Hz): 96dB
A/D Resolution
• 12 bits (XIP-5340)
• 14 bits (XIP-5341)
Data format
Binary two's complement
System accuracy
• 1.6 LSB (XIP-5340)
• 2.4 LSB (XIP-5341)
No missing codes • 12 bits ADC (XIP-5340)
• 14 bits ADC (XIP-5341)
A/D integral
linearity error
Settling time
• ±1 LSB (XIP-5340)
• -1 to 1.5 LSB (XIP-5341)
7µs to 0.01% of FSR for 10V step.
A/D triggers
Internal timer, external, and software
External trigger
(input)
Negative edge triggered, 5V TTL
External trigger
(output)
5V TTL, 500nS low pulse
Input noise
• 0.5 LSB rms (XIP-5340)
• 1 LSB rms (XIP-5341)
Maximum
throughput rate
• One channel: 125KHz (8µS/conversion)
• Eight channels (same bank): 1 MHz (8µS/8
channels)
• Sixteen channels (high & low banks): 1 MHz
(16µS/16 ch. at 2.2K ohm input resistance)
Xycom Automation, Inc.
734-429-4971 • Fax: 734-429-1010
http://www.xycom.com
§ FIFO buffer read: 2 wait states maximum
(500nS), 1 wait state typical (375nS)
§ Registers read/write: 0 wait states (250ns cycle)
§ Interrupt read/write: 0 wait states (250ns cycle)
I/O Pin Connections
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
a
Description
+CH00
-CH00
Common
+CH01
-CH01
Common
+CH02
-CH02
Common
+CH03
-CH03
Common
+CH04
-CH04
Common
+CH05
-CH05
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Description
Common
+CH06
-CH06
Common
+CH07
-CH07
Common
+CH08
-CH08
Common
+CH09
-CH09
Common
+CH10
-CH10
Common
+CH11
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Description
-CH11
Common
+CH12
-CH12
Common
+CH13
-CH13
Common
+CH14
-CH14
Common
+CH15
-CH15
Common
Ext Trigger a
Shield
Indicates an active-low signal.
ORDERING INFORMATION
Order Number
Description
XIP-5340-000
12-bit A/D
XIP-5341-000
14-bit A/D
Canada Sales: 905-607-3400
Northern Europe Sales: +44-1604-790-767
Southern Europe Sales: +39-011-770-53-11
© 2000 Xycom Automation, Inc. All rights reserved. Printed in US. All brand or product names are the property of their respective owners.
Specifications may change without notice.