IEICE TRANS. ELECTRON., VOL.E85–C, NO.1 JANUARY 2002
1
PAPER
A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold
Amplifier
Cheng-Chung HSU†∗ and Jieh-Tsorng WU† , Nonmembers
1.
Vin
SHA
fs
N-Bit A/D (2)
MUX
N-Bit A/D (1)
DEMUX
SUMMARY
A high-speed high-resolution sample-and-hold
ampliﬁer (SHA) is designed for time-interleaved analog-to-digital
converter applications. Using the techniques of precharging and
output capacitor coupling can mitigate the stringent performance
requirements for the opamp, resulting in low power dissipation.
Implemented in a standard 0.25 µm CMOS technology, the SHA
achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp
output at 100 MHz Nyquist sampling rate. The SHA occupies a
die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V
supply.
key words: sample-and-hold circuits, switched-capacitor circuits, time-interleaved analog-to-digital converter.
Do
N-Bit A/D (M)
fs / M
Fig. 1
Single-SHA time-interleaved ADC system.
INTRODUCTION
In multi-carrier wireless communication systems such
as software-deﬁned radios or base station receivers, the
analog-to-digital converter (ADC) is placed as closed as
possible toward the antenna, so that more processing
on the received signal can be performed in the digital
domain [1] [2]. The resulting systems are more ﬂexible and reliable at lower total costs. For accurate detection of weak signals under strong interferences, the
required ADCs need to have high dynamic range, and
particularly high spurious-free dynamic range (SFDR),
while operating at high sampling rate [3]. Typical ADC
speciﬁcations are 25 MHz input bandwidth, more than
100 MHz sampling rate, 12 to 14-bit resolution, and
larger than 80 dB in-band SFDR.
The time-interleaved conﬁguration shown in Fig. 1
is suitable for implementing the ADCs with the above
stringent requirements. The ADC uses M identical Nbit ADCs operating in parallel at fs /M clock rate to
achieve an equivalent fs sampling rate and N-bit resolution. A single input sample-and-hold ampliﬁer (SHA)
is preferred to avoid the potential sampling phase oﬀset if M distributed SHAs are used instead [4] [5]. The
design of the input SHA is crucial, since it operates at
fs sampling rate and needs to have N-bit resolution.
High-speed SHAs usually operate in open-loop
conﬁguration. The resolution of the SHAs is limited to
8–10 bits due to the non-ideal eﬀects of switches such
as charge injection and clock feedthrough [6] [7]. On
Manuscript received May 22, 2003.
Manuscript revised June 22, 2003.
†
The authors are with Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan,
300, R.O.C.
∗
E-mail: [email protected]
the other hand, high-resolution SHAs usually operate
in closed-loop conﬁguration. The sampling rate of the
SHAs is then limited by the transient behavior of the
opamps used [2] [8]. The opamps are designed based
on the requirements of dc gain, bandwidth, slew rate,
output voltage swing, noises, and under the constraint
of supply voltage.
This paper describes the design of a SHA that
takes advantage of the parallelism of the timeinterleaved conﬁguration to achieve high-speed and
high-resolution performance while reducing power dissipation. The paper is organized as follows. The conventional ﬂip-around SHA is reviewed in Section 2. The
proposed SHA is described and analyzed in Section 3.
The circuit design of SHA and the opamp’s eﬀect on
the SHA’s settling time are discussed in Section 4. The
experimental results are shown in Section 5. Finally,
the conclusions are given in Section 6.
2.
Flip-Around SHA
The ﬂip-around SHA shown in Fig. 2 is often used in
high-speed high-resolution applications [2] [9]. When
φ1 = 1, the SHA is in the sample mode, and the input is sampled on the Cs1 and Cs2 capacitors. When
φ2 = 1, the SHA is in the hold mode, and the sampling capacitors are connected to the outputs of the
opamp. The opamp and the two sampling capacitors
form a feedback loop to drive the CL1 and CL2 capacitive loads.
In the sample mode, the input sampling network
consists of two input buﬀers B1 and B2, two sampling
capacitors Cs1 and Cs2 , and MOSFET analog switches
S1–S4. The speed requirement for sampling network
can be expressed as [10]:
IEICE TRANS. ELECTRON., VOL.E85–C, NO.1 JANUARY 2002
2
φ2
φ1
Vi1
B1
S1
φ1a S3
s1
S5
S4
φ1
B2
φ1
φ1a
φ2
S2
C
C
B1
S1
φ1a
L1
Vo1
φ1a
VCMI
Vi2
C
φ1
Vi1
s2 φ2
C
B2
L2
C
S3
o1
φ3
C
L1
S11 φ
4
L3
S13
Vo1
φ1
S4
φ1
Vo2
C
s1
φ1a
VCMI
Vi2
C
C
S0 C
s2
o2
φ3
S12
C
S2
φ4
L2
Vo2
S14
C
L4
φ1
S6
φ1a
φ3
Fig. 2
τs ≤
φ4
The conventional ﬂip-around SHA.
1
2fs (N + 1)ln2
(1)
where τs is RC time constant of the sampling network,
N is the resolution in terms of number of bits, and fs
is the clock frequency. For 100 MHz sampling rate, the
required τs is approximately 0.55 nsec, and it is equivalent to f−3db = 287 MHz to achieve 12-bit resolution.
The fully diﬀerential bottom-plate sampling technique,
in which switches S3 and S4 are turned oﬀ before S1
and S2, reduces aperture jitter and switching errors due
to switches’s charge injection and clock feedthrough.
In the hold mode, the opamp together with the
feedback of Cs1 and Cs2 exhibits a settling time constant that can be expressed as:
τa =
[CL + (Cs Cp,i )] + Cp,o Cs + Cp,i
·
Gm
Cs
Fig. 3
ADC.
The precharged SHA for a 2-path time-interleaved
voltage variation of the inputs.
Thermal noise sampled at the SHA’s output is
an important consideration when high resolution is required. In the sample mode, the noise power stored on
the capacitor Cs is
2 =
Vn,s
To achieve N -bit accuracy, the deviation of Vo from Vi
should be less than 1/2N +1 of Vi . And the opamp’s
input capacitance Cp,i demands an increase in A. For
example, with Cs = 4 pF and Cp,i = 0.25 pF, A should
be at least 79 dB to achieve 12-bit accuracy.
During the sample mode, the opamp’s outputs are
usually forced to return to the designated commonmode voltage, VCMO . Thus, the opamp may experience large output voltage swing during the hold mode,
and need to have high slew rate for fast settling. In
addition, the opamp’s input common-mode range has
to be large enough to accommodate the common-mode
(4)
where k is the Boltzmann’s constant and T is the
absolute temperature. In the hold mode, the output noise power is determined by the opamp’s inputreferred noise density, transfer function, and the noise
bandwidth, and can be expressed as
(2)
where Cs = Cs1,s2 , CL = CL1,L2 , Gm is the transconductance of the opamp, Cp,i and Cp,o are the parasitic
capacitances at the opamp’s input and output nodes,
respectively. The unity-gain feedback of Cs1 and Cs2
makes the opamp achieve its fastest possible speed.
Due to the opamp’s ﬁnite dc gain, A, the steadystate output of the SHA in the hold mode is
1
Cp,i
Vo ≈ Vi 1 −
(3)
1+
A
Cs
kT
Cs
2 =
Vn,h
4kT (Cs + Cp,i )
· (1 + ne )
3Cs [CL + (Cs Cp,i )]
(5)
where ne is the noise contribution factor of the opamp
due to the other noise sources except the input transistors, and it depends on the architecture of the opamp.
The total input-referred noise power is the sum of the
noise contributions in both modes divided by the unity
2 = V 2 + V 2 . The input-referred
signal gain, i.e., Vn,i
n,s
n,h
noise is determined primarily by the input sampling
capacitors and the output capacitive loads.
3.
The Proposed Precharged SHA
Fig. 3 shows the proposed SHA circuit architecture for
a 2-path time-interleaved ADC. Analog switches S11–
S14 and additional clock phases φ3 and φ4 represent
the input demultiplexer of a time-interleaved ADC system. During the channel-1 sample mode, φ1 = 1 and
φ3 = 1, the input buﬀers B1 and B2 not only drive the
Cs1 and Cs2 sampling capacitors but also precharge the
opamp’s output nodes including CL1 and CL2 . When
switching to the hold mode (φ1 = 0), the opamp’s outputs can settle to their ﬁnal values in a much shorter
HSU and WU: A CMOS 33-MW 100-MHZ 80-DB SFDR SAMPLE-AND-HOLD AMPLIFIER
3
φ4
Vi1
C
o1
Vo1
φ3
Cf1
φ3
φ3
Vi2
SHA
Vr ( Dj )
φ4
A1
Cg1
φ3
φ4
Cf3
φ4
φ4
Vr ( Dj )
Fig. 4
SHA.
φ3
A2
Cg3
A 2-path time-interleaved ADC using the precharged
time period without slewing due to the precharging.
During the channel-2 sample mode, φ1 = 1 and φ4 = 1,
the channel-2 capacitive loads of CL3 and CL4 are
precharged alternately. The S0 switch is added to
equalize the opamp’s outputs during the sample mode.
Fig. 4 shows a 2-path time-interleaved ADC using this precharged SHA. Both A1 and A2 are the ﬁrst
stages of two separate pipelined ADCs, operating on
clocks φ3 and φ4 . The capacitive load CL1 in Fig. 3
represents the summation of Cf 1 , Cg1 , and input capacitance of the comparator banks not shown in Fig. 4,
while CL3 is the summation of Cf 3 and Cg3 . The eﬀects
of the gain and oﬀset mismatches between two pipelined
ADCs can be eliminated using background calibration
[11].
The two output coupling capacitors, Co1 and Co2 ,
are added to reduce the switching errors of S1 and S2
[12]. The combination of output capacitor coupling and
precharging also reduces the opamp’s the dc gain and
output voltage swing requirements, so that higher speed
can be achieved.
The SHA enters the hold mode by turning oﬀ S3
and S4 ﬁrst and then turning oﬀ S1 and S2 a moment
later. Due to the continuous variation of the inputs, the
voltage sampled in Cs will be diﬀerent from those in CL
and Co , depending on the phase diﬀerence between φ1a
and φ1 . When φ1 = 0, the output can be expressed as:
1 CL Vcl
1 Vco
−1 +
− 1 (6)
Vo ≈ Vi 1 +
A Vi
A Co Vi
where Vi is the voltage stored on Cs when φ1a is low,
Vco and Vcl are the voltages stored on Co and CL , respectively, when φ1 is low. The output voltage error
depends on the ratios of Vco /Vi and Vcl /Vi , which are
close to one for slow varying input. Comparing to Eq. 3,
the dc gain requirement for the opamp in a precharged
SHA is relieved. For example, with CL = 3Co and
Vco = Vcl = 0.98Vi , the opamp needs only 56 dB dc
gain to suppress the gain error term for 12-bit resolution.
When the SHA is changed from the sample mode
to the hold mode, the voltage changes at the opamp’s
outputs can be expressed as:
CL
(Vi − Vcl )
(7)
∆Vo,op = (Vi − Vco ) +
Co
The value of ∆Vo,op can be reduced by minimizing the
voltage diﬀerences of Vi − Vco and Vi − Vcl . Increasing
Co can reduce ∆Vo,op , but also increase the capacitive
loads of the B1 and B2 input buﬀers during the sample
mode.
During the hold mode, the settling time constant
of the feedback ampliﬁer is given by
[CL + (Cs Cp,i )](1 + Cp,o /Co ) + Cp,o
Gm
Cs + Cp,i
·
(8)
Cs
where Co = Co1 = Co2 . Comparing Eq. 8 with Eq. 2,
it shows that the speed penalty due to the output coupling capacitors, Co1 and Co2 , can be reduced by increasing their values, Co . But increasing Co also increases the associated parasitic capacitors, which are
added to CL and Cp,o .
During the sample mode, the input is sampled on
Cs , Co , and CL in parallel, and the noise power stored
on the capacitors is
kT
2 =
Vn,s
(9)
Cs + Co + CL
In the hold mode, it can be shown that the opamp’s
noise contribution is the same for both the ﬂip-around
SHA and the precharged SHA, and can be described by
Eq. 5.
τa =
4.
Circuit Design
The precharged SHA of Fig. 3 is designed to operate
under a single 2.5 V supply voltage using a standard
0.25 µm CMOS technology. The minimum values of the
capacitors, including Cs , Co , and CL , are determined
by Eq. 9. A total capacitance of more than 4 pF is required to achieve 12-bit resolution with a 2 Vpp diﬀerential input [13]. In this design, CL = 4 pF, Cs = 1 pF
and Co = 1.5 pF are chosen. The B1 and B2 input
buﬀers are then required to drive total capacitive loads
of 6.5 pF. As a comparison, the ﬂip-around SHA requires Cs = 4 pF and CL = 4 pF, and its input buﬀers
need to drive 4 pF capacitive loads. Therefore, the total
capacitor area of the precharged SHA is smaller than
that of the ﬂip-around SHA.
The input buﬀers B1 and B2 are pMOST source
followers with ﬂoating wells tied to the outputs. Each
buﬀer consumes 10.2 mW of power and has a −3 dB
bandwidth of 340 MHz, while driving a 6.5 pF capacitive load. Simulations show that the SHA’s major distortion comes from the input buﬀers driving the sampling switched-capacitor network.
IEICE TRANS. ELECTRON., VOL.E85–C, NO.1 JANUARY 2002
4
S4
CK
S3
S2
S1
CK
S5
Vo
Vi
(a)
M2
M12
CK
CK
VDD
VDD
CK
M11
M1
M13 M5
Vi
VSS
CK
Cb
M3
VSS
VSS
CK
M4
Cb
VSS
VDD
Vo
(b)
Switch
Switch
Fig. 5 Bootstrapped analog switch. (a) Conceptual schematic.
(b) Detail circuit implementation.
Settling Time Constant (ns)
VDD
CK
0.6
0.5
0.4
Precharged SHA
0.3
Flip-Around SHA
with Dynamic CMFB
0.2
0.1
0
0
Flip-Around SHA
1
VB3
MC6
M8
M7
M5
φ1
M6
M10
2
4
3
5
6
CL (pF)
VDD
Fig. 7
Opamp’s settling time constant in the hold mode.
MC5
VB3
Vo
4
Vo
M3
M4
VB2
Vi
M1
M2
Vi
VB1
MC1
MC2
VCMO
MC7
M9
MC3
MC4
MC8
VSS
Fig. 6
Flip-Around SHA
3.5
Telescope opamp schematic.
Settling Time (ns)
VB2
3
2.5
2
1.5
The analog switches, S1 and S2, are realized using nMOSTs with bootstrapped gate control voltage to
reduce the distortion and device size. The conceptual
schematic is shown in Fig. 5(a) [14]. When CK is low,
the capacitor Cb is charged to VDD . Then when CK
is high, the analog switch’s gate voltage is Vi + VDD ,
which can be larger than the supply voltage. The detailed schematic is shown in Fig. 5(b) [15]. If the input
Vi is less than VDD , the voltage stress on the gate oxide
is less than VDD for all transistors. The M13 transistor is added to reduce the maximum Vds of M5. In
this design, the analog switch has a W/L of 40 µm by
0.25 µm.
The schematic of the opamp is shown in Fig. 6.
The telescopic conﬁguration, consisting of M1–M9, is
the most power eﬃcient for similar speed performance.
The circuit’s limited output swing is not a concern
in this precharged SHA application. The transistor
M10 is used to realize the S0 switch shown in Fig. 3.
The continuous-time output common-mode feedback
(CMFB) is realized using MC1–MC8. Due to the
opamp’s reduced output voltage swing, the opamp’s
output common-mode voltage can be sensed simply by
the dual source-coupled pairs, MC1-MC2 and MC3MC4. The input and output common-mode voltage of
the opamp, VCMI and VCMO , can be diﬀerent, and both
1
Precharged SHA
0.01
0.1
(Vi-Vcl)/Vi
Fig. 8
curacy.
SHA hold-mode settling time requirement for 12-bit ac-
can be diﬀerent from the common-mode voltage of the
SHA’s inputs. The opamp has a dc gain of 63 dB and
a diﬀerential output swing of 800 mVpp. Its unity-gain
frequency is 1.2 GHz when driving 1.5 pF capacitive
loads while dissipating only 12.5 mW of power.
Fig. 7 shows the settling time constant of Eq. 2
and Eq. 8 versus diﬀerent values of CL . Assume that
the ﬂip-around SHA has Gm = 15 mA/V, Cs = 4 pF,
Cp,i = 0.25 pF, and Cp,o = 0.4 pF while the precharged
SHA has Gm = 15 mA/V, Cs = 1 pF, Co = 1.5 pF,
Cp,i = 0.25 pF, and Cp,o = 0.4 pF. With CL = 4 pF,
the τa of the ﬂip-around SHA is 31% less than the τa of
the precharged SHA. If dynamic output CMFB is used
in the ﬂip-around SHA to accommodate wide output
voltage swing, additional capacitance of 1 pF is added
to the Cp,o , and its τa becomes 22% less than the τa of
the precharged SHA.
Consider only the exponential transient behavior,
the ﬂip-around SHA requires a hold-mode settling time
HSU and WU: A CMOS 33-MW 100-MHZ 80-DB SFDR SAMPLE-AND-HOLD AMPLIFIER
5
Clock Driver
SHA1
Fig. 9
Chip micrograph of an experimental precharged SHA.
Vi
fs /2
SHA2
SHA1
Vo1
SHA2
f
Vo2
Fig. 11 Output spectrum from the resampling measurement
setup. Sampling frequency fs is 100 MHz. Input frequency is
50.038 MHz.
f
CK1
fs
Fig. 10
1/2
CK2
fs /2
Half-rate resampling measurement setup.
of 8.3τa to achieve 12-bit accuracy. The precharged
SHA requires less τa to achieve the same accuracy due
to the reduced output voltage swing in the hold mode,
described by Eq. 7. The resulting settling time is shown
in Fig. 8. The precharged SHA using the identical
opamp has a larger τa than the ﬂip-around SHA. However, the precharged SHA has a shorter overall settling
time if (Vi − Vcl )/Vi is less than 0.16. In this design,
the value of (Vi − Vcl )/Vi is 0.005, which corresponds
to a settling time 53% less than that of a ﬂip-around
SHA. If a maximum slew rate for the output is imposed,
the settling time advantage of the precharged SHA is
greater, since its reduced output swing also mitigates
the slew-rate eﬀect.
5.
Experimental Results
The precharged SHA is fabricated in a standard 0.25µm
CMOS process. Fig. 9 is the chip micrograph. The
active die area is 0.35 mm2 . Operating from a 2.5 V
supply, the SHA’s total power dissipation is 33 mW.
The chip contains two identical precharged SHAs
to facilitate half-rate resampling measurement [16].
Fig. 10 shows the measurement setup. The sampling
frequency is fs for SHA1, and fs /2 for SHA2. The input Vi is a sinusoidal signal with frequency near the
Nyquist rate, i.e., fs /2 + ∆f . Then the sampled sinu-
SFDR and Distortion (dB)
80
78
SFDR
76
74
72
THD
70
68
66
2
2.5
3
Output Voltage (V)
Fig. 12
Measured SFDR and THD vs. output voltage.
soidal output from SHA2 is a low-frequency signal at
∆f . Fig. 11 shows the measured SHA2’s output spectrum. The sampling frequency fs is 100 MHz and the
input frequency is 50.038 MHz while the output is a 38
KHz 2 Vpp sinusoidal signal. The 3rd-order harmonic
distortion is less than −78 dB. Fig. 12 shows the measured SFDR and total harmonic distortion (THD) of
the SHA versus its output voltage. The SHA can accommodate output swing as large as 2.7 Vpp with over
72 dB SFDR at 100 MHz sampling rate. It achieves
80 dB SFDR at 1.8 Vpp output. The measurement is
limited by the dynamic range of the test setup. The
THD is −76.3 dB for 2 Vpp output.
Fig. 13 shows the measured SFDR at diﬀerent input frequencies while the sampling clock is 125 MHz
and the output voltage is 2 Vpp. The SFDR is mea-
IEICE TRANS. ELECTRON., VOL.E85–C, NO.1 JANUARY 2002
6
Table 1
Sample Rate
SFDR at Nyquist Rate
Diﬀerential Input
Opamp Power
DC Gain of Opamp
Opamp Type
Supply Voltage
CMOS Technology
Performance Summary.
[2]
75 MHz
85 dB
2 Vpp
100 mW
80 dB
Folded Cascode
3V
0.35 µm
[10]
100 MHz
68 dB
2 Vpp
140 mW
76 dB
Super Cascode
5V
1 µm
80
[13]
10 MHz
77 dB
1.5 Vpp
22 mW
97 dB
Telescopic
3.3 V
0.5 µm
This work
100 MHz
80 dB
1.8 Vpp
12.5 mW
63 dB
Telescopic
2.5 V
0.25 µm
100
[10]
[6]
Power/2 (uW)
70
[7]
FOM = 0.2 uW/Msps
N
SFDR (dB)
75
65
60
10
[2]
[17]
[13]
55
50
0
5
10
15
20
25
30
1
10
100
Sampling Rate (MHz)
Input Frequency (MHz)
Fig. 13 Measured SFDR vs. input frequency at 125 MHz sampling rate.
sured from the SHA1 output spectrum without using
the SHA2 resampler. The input frequency has little
eﬀect on the SHA’s SFDR.
Table 1 summarizes the performance of the proposed SHA, and compares it with similar previously
published works. In [2], [10] and [13], the stringent
requirements for the opamp demand more power consumption. The design ﬁgure-of-merit (FOM) of the
SHAs can be deﬁned as:
FOM =
Power
2 N · fs
(10)
where fs is the sampling rate, and N is the resolution
in number of bits. The number N can be calculated by
(SFDR − 1.76)/6.02, where SFDR is in dB. The worstcase SFDR usually occurs when the input frequency
is near fs /2. Fig. 14 compares the FOM of recent
high-speed high-resolution SHAs. Note that most of
the previous designs didn’t include the input buﬀers in
the power speciﬁcations, except [6] and this work. This
work achieves the best performance over the previous
designs in terms of FOM.
6.
This Work
FOM = 0.02 uW/Msps
Conclusions
In a time-interleaved ADC system, a single front-end
SHA can eliminate any phase oﬀset among the paral-
Fig. 14
SHA ﬁgure-of-merit comparison.
lel channels. Then, by taking advantage of the inherent parallelism in a time-interleaved system, such as
precharging, it is possible to improve the SHA’s performances.
In the design of a high-speed and high-resolution
SHA, the application of both the precharging and the
output capacitive coupling techniques can relieve the
original stringent performance requirements for the internal opamp, such as dc gain, settling time, and output voltage swing. Implemented in a standard 0.25 µm
CMOS technology, with a simple telescopic opamp dissipating 12.5 mW from a 2.5 V supply, the resulting SHA achieves 80 dB spurious-free dynamic range
(SFDR) at 100 MHz sampling rate.
Acknowledgement
The authors thank the Chip Implementation Center
for chip fabrication. This research was supported by
the National Science Council (Grant NSC-90-2215-E009-110) of Taiwan, R.O.C., and the Lee-MTI Center
of the National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C.
References
[1] T. Gratzek, B. Brannon, J. Camp, and F. Murden, “A new
paradigm for base station receivers: High IF sampling +
HSU and WU: A CMOS 33-MW 100-MHZ 80-DB SFDR SAMPLE-AND-HOLD AMPLIFIER
7
digital ﬁltering,” IEEE Radio-Frequency Integrated Circuits
Symposium, pp. 143–146, June 1997.
[2] W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer,
“A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85dB SFDR at Nyquist input,” IEEE J. Solid-State Circuits,
vol. 36, pp. 1931–1936, December 2001.
[3] J. A. Wepman, “Analog-to-digital converter technology comparison,” IEEE Commun. Mag., vol. 33, pp. 39–45, May
1995.
[4] K. Poulton, J. J. Corcoran, and T. Hornak, “A 1-GHz 6bit ADC system,” IEEE J. Solid-State Circuits, vol. 22, pp.
962–970, December 1987.
[5] L. Sumanen, M. Waltari, and K. A. I. Halonen, “A 10-bit
200-MS/s CMOS parallel pipeline A/D converter,” IEEE J.
Solid-State Circuits, vol. 36, pp. 1048–1055, July 2001.
[6] A. Boni, A. Pierazzi, and C. Morandi, “A 10-b 185-MS/s
track-and-hold in 0.35-µm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 195–203, February 2001.
[7] K. Hadidi, M. Sasaki, T. Watanabe, D. Muramatsu, and
T. Matsumoto, “An open-loop full CMOS 103MHz -61dB
THD S/H circuit,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 381–383, 1998.
[8] G.-C. Ahn, H.-C. Choi, S.-I. Lim, S.-H. Lee, and C.-D. Lee,
“A 12-b, 10-MHz, 250-mW CMOS A/D converter,” IEEE J.
Solid-State Circuits, vol. 31, pp. 2030–2035, December 1996.
[9] H. V. der Ploeg, G. Hoogzaad, H. A. H. T. M. Vertregt, and
R. J. Roovers, “A 2.5-V 12-B 54-Msample/s 0.25-µm CMOS
ADC in 1-mm2 with mixed-signal chopping and calibration,”
IEEE J. Solid-State Circuits, vol. 36, pp. 1859–1867, December 2001.
[10] K. Y. Kim, A 10-bit, 100 MS/s analog-to-digital converter
in 1-µm CMOS. Univ. Calif., Los Angeles: Ph.D. thesis,
1996.
[11] K. C. Dyer, D. Fu, S. H. Lewis, and P. J. Hurst, “An
analog background calibration technique for time-interleaved
analog-to-digital converters,” IEEE J. Solid-State Circuits,
vol. 33, pp. 1912–1919, December 1998.
[12] P. J. Lim and B. A. Wooley, “A high-speed sample-and-hold
technique using a Miller hold capacitance,” IEEE J. SolidState Circuits, vol. 26, pp. 643–651, April 1991.
[13] J. M. Ingino and B. A. Wooley, “A continuously calibrated
12-b, 10-MS/s, 3.3-V A/D converter,” IEEE J. Solid-State
Circuits, vol. 33, pp. 1920–1931, December 1998.
[14] A. Abo and P. Gray, “A 1.5V 10b 14.3 MSps CMOS pipeline
analog-to-digital converter,” IEEE J. Solid-State Circuits,
vol. 34, pp. 599–606, May 1999.
[15] M. Dessouky and A. Kaiser, “Input switch conﬁguration
suitable for rail-to-rail operation,” IEE Electronics Letters,
vol. 35, pp. 8–9, January 1999.
[16] P. Vorenkamp and J. P. M. Verdaasdonk, “Fully bipolar,
120 Ms/s 10 b track-and-hold circuit,” IEEE J. Solid-State
Circuits, vol. 26, pp. 643–651, April 1992.
[17] W. C. Song, H. W. Choi, S. U. Kwak, and B. S. Song, ‘A
10-b 20-Msample/s low-power CMOS ADC,” IEEE J. SolidState Circuits, vol. 30, pp. 514–521, May 1995.
Cheng-Chung Hsu
was born in
Chang-Hua, Taiwan, in 1975. He received
the B.S. degree and M.S. in electronics engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1997 and
1998, respectively. He is currently working toward the Ph.D. degree in National
Chiao-Tung University.
His current research interests include analog front-end circuits in data communication.
Jieh-Tsorng Wu
was born in Taipei,
Taiwan, on August 31, 1958. He received
the B.S. degree in electronics engineering from National Chiao-Tung University,
Hsin-Chu, Taiwan, in 1980, and the M.S.
and Ph.D. degrees in electrical engineering from Stanford University, Stanford,
CA, in 1983 and 1988, respectively.
From 1980 to 1982 he served in the Chinese Army as a Radar Technical Oﬃcer.
From 1982 to 1988, at Stanford University, he focused his research on high-speed analog-to-digital conversion in CMOS VLSI. From 1988 to 1992 he was a Member
of Technical Staﬀ at Hewlett-Packard Microwave Semiconductor
Division in San Jose, CA, and was responsible for several linear
and digital giga-hertz IC designs. Since 1992, he has been with
the Department of Electronics Engineering, National Chiao-Tung
University, Hsin-Chu, Taiwan, where he is now a Professor. His
current research interests are integrated circuits and systems for
high-speed networks and wireless communications.
Dr. Wu is a member of Phi Tau Phi.