a FEATURES 3.0 ms Acquisition Time to 60.01% max Low Droop Rate: 1.0 mV/ms max Sample/Hold Offset Step: 3 mV max Aperture Jitter: 0.5 ns Extended Temperature Range: –558C to +1258C Internal Hold Capacitor Internal Application Resistors 612 V or 615 V Operation Available in Surface Mount High Speed, Precision Sample-and-Hold Amplifier AD585 FUNCTIONAL BLOCK DIAGRAM DIP LCC/PLCC Package APPLICATIONS Data Acquisition Systems Data Distribution Systems Analog Delay & Storage Peak Amplitude Measurements MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION The AD585 is a complete monolithic sample-and-hold circuit consisting of a high performance operational amplifier in series with an ultralow leakage analog switch and a FET input integrating amplifier. An internal holding capacitor and matched applications resistors have been provided for high precision and applications flexibility. The performance of the AD585 makes it ideal for high speed 10- and 12-bit data acquisition systems, where fast acquisition time, low sample-to-hold offset, and low droop are critical. The AD585 can acquire a signal to ± 0.01% in 3 µs maximum, and then hold that signal with a maximum sample-to-hold offset of 3 mV and less than 1 mV/ms droop, using the on-chip hold capacitor. If lower droop is required, it is possible to add a larger external hold capacitor. The high speed analog switch used in the AD585 exhibits aperture jitter of 0.5 ns, enabling the device to sample full scale (20 V peak-to-peak) signals at frequencies up to 78 kHz with 12-bit precision. The AD585 can be used with any user-defined feedback network to provide any desired gain in the sample mode. On-chip precision thin-film resistors can be used to provide gains of +1, –1, or +2. Output impedance in the hold mode is sufficiently low to maintain an accurate output signal even when driving the dynamic load presented by a successive-approximation A/D converter. However, the output is protected against damage from accidental short circuits. The control signal for the HOLD command can be either active high or active low. The differential HOLD signal is compatible with all logic families, if a suitable reference level is provided. An on-chip TTL reference level is provided for TTL compatibility. The AD585 is available in three performance grades. The JP grade is specified for the 0°C to +70°C commercial temperature range and packaged in a 20-pin PLCC. The AQ grade is specified for the –25°C to +85°C industrial temperature range and is packaged in a 14-pin cerdip. The SQ and SE grades are specified for the –55°C to +125°C military temperature range and are packaged in a 14-pin cerdip and 20-pin LCC. PRODUCT HIGHLIGHTS 1. The fast acquisition time (3 µs) and low aperture jitter (0.5 ns) make it the first choice for very high speed data acquisition systems. 2. The droop rate is only 1.0 mV/ms so that it may be used in slower high accuracy systems without the loss of accuracy. 3. The low charge transfer of the analog switch keeps sample-to hold offset below 3 mV with the on-chip 100 pF hold capacitor, eliminating the trade-off between acquisition time and S/H offset required with other SHAs. 4. The AD585 has internal pretrimmed application resistors for applications versatility. 5. The AD585 is complete with an internal hold capacitor for ease of use. Capacitance can be added externally to reduce the droop rate when long hold times and high accuracy are required. 6. The AD585 is recommended for use with 10- and 12-bit successive-approximation A/D converters such as AD573, AD574A, AD674A, AD7572 and AD7672. 7. The AD585 is available in versions compliant with MIL-STD883. Refer to the Analog Devices Military Products Databook or current AD585/883B data sheet for detailed specifications. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 @ +258C and V = 612 V or 615 V, and C = Internal, A = +1, AD585–SPECIFICATIONS (typical HOLD active unless otherwise noted) S Model Min SAMPLE/HOLD CHARACTERISTICS Acquisition Time, 10 V Step to 0.01% 20 V Step to 0.01% Aperture Time, 20 V p-p Input, HOLD 0 V Aperture Jitter, 20 V p-p Input, HOLD 0 V Settling Time, 20 V p-p Input, HOLD 0 V, to 0.01% Droop Rate Droop Rate TMIN to TMAX Charge Transfer Sample-to-Hold Offset Feedthrough 20 V p-p, 10 kHz Input TRANSFER CHARACTERISTICS 1 Open Loop Gain VOUT = 20 V p-p, RL = 2k Application Resistor Mismatch Common-Mode Rejection VCM = ± 10 V Small Signal Gain Bandwidth VOUT = 100 mV p-p Full Power Bandwidth VOUT = 20 V p-p Slew Rate VOUT = 20 V p-p Output Resistance (Sample Mode) IOUT = ± 10 mA Output Short Circuit Current Output Short Circuit Duration AD585J Typ Min AD585A Typ 3 5 Max Min AD585S Typ 3 5 Max Units 3 5 µs µs 35 35 35 ns 0.5 0.5 0.5 ns 0.5 0.5 0.5 1 Doubles Every 10°C 0.3 –3 3 1 Double Every 10°C 0.3 –3 3 1 Doubles Every 10°C 0.3 –3 3 µs mV/ms pC mV 0.5 0.5 0.5 mV 200,000 200,000 0.3 80 200,000 0.3 80 V/V % dB 80 2.0 2.0 MHz 160 160 160 kHz 10 10 10 V/µs 0.05 0.05 50 Indefinite 5 6 2 5 2 3 2 5 10 20 10 1012 1012 1012 1.6 2.0 1.4 1.2 0.05 Ω mA 2 3 2 502 mV mV nA nA pF 50 Indefinite 10 1.4 1.2 0.3 2.0 50 Indefinite ANALOG INPUT CHARACTERISTICS Offset Voltage Offset Voltage, T MIN to T MAX Bias Current Bias Current, TMIN to TMAX Input Capacitance, f = 1 MHz Input Resistance, Sample or Hold 20 V p-p Input, A = +1 DIGITAL INPUT CHARACTERISTICS TTL Reference Output Logic Input High Voltage TMIN to TMAX Logic Input Low Voltage TMIN to TMAX Logic Input Current (Either Input) Max H 1.6 2.0 1.4 1.2 Ω 1.6 V 2.0 0.8 50 V 0.8 50 0.7 50 V µA POWER SUPPLY CHARACTERISTICS Operating Voltage Range Supply Current, R L = ∞ Power Supply Rejection, Sample Mode +5, –10.8 6 70 ± 18 10 +5, –10.8 6 70 ± 18 10 +5, –10.8 6 70 ± 18 10 V mA dB TEMPERATURE RANGE Specified Performance 0 +70 –25 +85 –55 +125 °C PACKAGE OPTIONS 3, 4 Cerdip (Q-14) LCC (E-20A) PLCC (P-20A) AD585AQ AD585SQ AD585SE AD585JP NOTES 1 Maximum input signal is the minimum supply minus a headroom voltage of 2.5 V. 2 Not tested at –55°C. 3 E = Leadless Ceramic Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip. 4 For AD585/883B specifications, refer to Analog Devices Military Products Databook. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. –2– REV. A AD585 ABSOLUTE MAXIMUM RATINGS Supplies (+VS, –VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS RIN, RFB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . . . 300°C Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite TTL Logic Reference Short Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite Figure 2. Acquisition Time vs. Hold Capacitance (10 V Step to 0.01%) REV. A –3– AD585 SAMPLED DATA SYSTEMS In sampled data systems there are a number of limiting factors in digitizing high frequency signals accurately. Figure 9 shows pictorially the sample-and-hold errors that are the limiting factors. In the following discussions of error sources the errors will be divided into the following groups: 1. Sample-to-Hold Transition, 2. Hold Mode and 3. Hold-to-Sample Transition. f MAX = –( N + 1) 2 π ( Aperture Jitter ) For an application with a 10-bit A/D converter with a 10 V full scale to a 1/2 LSB error maximum. f MAX = –(10 + 1) 2 –9 π (0.5 × 10 ) f MAX = 310.8 kHz. For an application with a 12-bit A/D converter with a 10 V full scale to a 1/2 LSB error maximum: f MAX = –(12 + 1) 2 –9 π (0.5 × 10 ) f MAX = 77.7 kHz. Figure 9. Pictorial Showing Various S/H Characteristics Figure 11 shows the entire range of errors induced by aperture jitter with respect to the input signal frequency. SAMPLE-TO-HOLD TRANSITION The aperture delay time is the time required for the sample-andhold amplifier to switch from sample to hold. Since this is effectively a constant then it may be tuned out. If however, the aperture delay time is not accounted for then errors of the magnitude as shown in Figure 10 will result. Figure 11. Aperture Jitter Error vs. Frequency Sample-to-hold offset is caused by the transfer of charge to the holding capacitor via the gate capacitance of the switch when switching into hold. Since the gate capacitance couples the switch control voltage applied to the gate on to the hold capacitor, the resulting sample-to-hold offset is a function of the logic level . Figure 10. Aperture Delay Error vs. Frequency To eliminate the aperture delay as an error source the sampleto-hold command may be advanced with respect to the input signal . Once the aperture delay time has been eliminated as an error source then the aperture jitter which is the variation in aperture delay time from sample-to-sample remains. The aperture jitter is a true error source and must be considered. The aperture jitter is a result of noise within the switching network which modulates the phase of the hold command and is manifested in the variations in the value of the analog input that has been held. The aperture error which results from this jitter is directly related to the dV/dT of the analog input. The logic inputs were designed for application flexibility and, therefore, a wide range of logic thresholds. This was achieved by using a differential input stage for HOLD and HOLD. Figure 1 shows the change in the sample-to-hold offset voltage based upon an independently programmed reference voltage. Since the input stage is a differential configuration, the offset voltage is a function of the control voltage range around the programmed threshold voltage. The sample-to-hold offset can be reduced by adding capacitance to the internal 100 pF capacitor and by using HOLD instead of HOLD. This may be easily accomplished by adding an external capacitor between Pins 7 and 8. The sample-to-hold offset is then governed by the relationship: The error due to aperture jitter is easily calculated as shown below. The error calculation takes into account the desired accuracy corresponding to the resolution of the N-bit A/D converter. S/H Offset (V ) = –4– Charge ( pC ) C H Total ( pF ) REV. A AD585 For the AD585 in particular it becomes: 0.3 pC S/H Offset (V ) = 100 pF + (C EXT HOLD-TO-SAMPLE TRANSITION The Nyquist theorem states that a band-limited signal which is sampled at a rate at least twice the maximum signal frequency can be reconstructed without loss of information. This means that a sampled data system must sample, convert and acquire the next point at a rate at least twice the signal frequency. Thus the maximum input frequency is equal to ) The addition of an external hold capacitor also affects the acquisition time of the AD585. The change in acquisition time with respect to the CEXT is shown graphically in Figure 2. f MAX = HOLD MODE 1 2 (T ACQ + TCONV + T AP ) In the hold mode there are two important specifications that must be considered; feedthrough and the droop rate. Feedthrough errors appear as an attenuated version of the input at the output while in the hold mode. Hold-Mode feedthrough varies with frequency, increasing at higher frequencies. Feedthrough is an important specification when a sample and hold follows an analog multiplexer that switches among many different channels. Where TACQ is the acquisition time of the sample-to-hold amplifier, TAP is the maximum aperture time (small enough to be ignored) and TCONV is the conversion time of the A/D converter. Hold-mode droop rate is the change in output voltage per unit of time while in the hold mode. Hold-mode droop originates as leakage from the hold capacitor, of which the major leakage current contributors are switch leakage current and bias current. The rate of voltage change on the capacitor dV/dT is the ratio of the total leakage current IL to the hold capacitance CH. The fast acquisition time of the AD585 when used with a high speed A/D converter allows accurate digitization of high frequency signals and high throughput rates in multichannel data acquisition systems. The AD585 can be used with a number of different A/D converters to achieve high throughput rates. Figures 12 and 13 show the use of an AD585 with the AD578 and AD574A. Droop Rate = DATA ACQUISITION SYSTEMS dVOUT I ( pA) (Volts/Sec) = L dT CH ( pF ) For the AD585 in particular; Droop Rate = 100 pA 100 pF + (CEXT ) Additionally the leakage current doubles for every 10°C increase in temperature above 25°C; therefore, the hold-mode droop rate characteristic will also double in the same fashion. The hold-mode droop rate can be traded-off with acquisition time to provide the best combination of droop error and acquisition time. The tradeoff is easily accomplished by varying the value of CEXT. Since a sample and hold is used typically in combination with an A/D converter, then the total droop in the output voltage has to be less than 1/2 LSB during the period of a conversion. The maximum allowable signal change on the input of an A/D converter is: ∆V max = Figure 12. A/D Conversion System, 117.6 kHz Throughput 58.8 kHz max Signal Input Full -Scale Voltage ( N +1) 2 Once the maximum ∆V is determined then the conversion time of the A/D converter (TCONV) is required to calculate the maximum allowable dV/dT. dV ∆V max max = dt T CONV dV max The maximum as shown by the previous equation is dT the limit not only at 25°C but at the maximum expected operating temperature range. Therefore, over the operating temperature range the following criteria must be met (TOPERATION –25°C) = ∆T. ( ∆T °C ) dV 25° C × 2 10°C ≤ dV max dT dT REV. A Figure 13. 12-Bit A/D Conversion System, 26.3 kHz Throughput Rate, 13.1 kHz max Signal Input –5– LOGIC INPUT The sample-and-hold logic control was designed for versatile logic interfacing. The HOLD and HOLD inputs may be used with both low and high level CMOS, TTL and ECL logic systems. Logic threshold programmability was achieved by using a differential amplifier as the input stage for the digital inputs. A predictable logic threshold may be programmed by referencing either HOLD or HOLD to the appropriate threshold voltage. For example, if the internal 1.4 V reference is applied to HOLD an input signal to HOLD between +1.8 V and +VS will place the AD585 in the hold mode. The AD585 will go into the sample mode for this case when the input is between –VS and +1.0 V. The range of references which may be applied is from (–VS +4 V) to (+VS –3 V). OPTIONAL CAPACITOR SELECTION If an additional capacitor is going to be used in conjunction with the internal 100 pF capacitor it must have a low dielectric absorption. Dielectric absorption is just that; it is the charge absorbed into the dielectric that is not immediately added to or removed from the capacitor when rapidly charged or discharged. The capacitor with dielectric absorption is modeled in Figure 14. ence between the voltage being measured and the voltage previously measured determines the fraction by which the dielectric absorption figure is multiplied. It is impossible to readily correct for this error source. The only solution is to use a capacitor with dielectric absorption less than the maximum tolerable error. Capacitor types such as polystyrene, polypropylene or Teflon are recommended. GROUNDING Many data-acquisition components have two or more ground pins which are not connected together within the device. These “grounds” are usually referred to as the Logic Power Return Analog Common (Analog Power Return), and Analog Signal Ground. These grounds must be tied together at one point, usually at the system power-supply ground. Ideally, a single solid ground would be desirable. However, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the ground pin of the AD585. Separate ground returns should be provided to minimize the current flow in the path from sensitive points to the system ground point. In this way supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. C851c–5–4/89 AD585 Figure 14. Capacitor Model with Dielectric Absorption If the capacitor is charged slowly, CDA will eventually charge to the same value as C. But unfortunately, good dielectrics have very high resistances, so while CDA may be small, RX is large and the time constant RX CDA typically runs into the millisecond range. In fast charge, fast-discharge situations the effect of dielectric absorption resembles “memory”. In a data acquisition system where many channels with widely varying data are being sampled the effect is to have an ever changing offset which appears as a very nonlinear sample-to-hold offset since the differ- Figure 15. Basic Grounding Practice OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Terminal LCC (E-20A) 20-Terminal PLCC (P-20A) PRINTED IN U.S.A. 14-Pin Cerdip (Q-14) –6– REV. A LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits General Description Features The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 1010Ω allows high source impedances to be used without degrading accuracy. P-channel junction FET’s are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1 µF hold capacitor. The JFET’s have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages. n Operates from ± 5V to ± 18V supplies n Less than 10 µs acquisition time n TTL, PMOS, CMOS compatible logic input n 0.5 mV typical hold step at Ch = 0.01 µF n Low input offset n 0.002% gain accuracy n Low output noise in hold mode n Input characteristics do not change during hold mode n High supply rejection ratio in sample or hold n Wide bandwidth n Space qualified, JM38510 Logic inputs on the LF198 are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from ± 5V to ± 18V supplies. An “A” version is available with tightened electrical specifications. Typical Connection and Performance Curve Acquisition Time DS005692-32 DS005692-16 Functional Diagram DS005692-1 © 2000 National Semiconductor Corporation DS005692 www.national.com LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits July 2000 LF198/LF298/LF398, LF198A/LF398A Absolute Maximum Ratings (Note 1) Hold Capacitor Short Circuit Duration Lead Temperature (Note 4) H package (Soldering, 10 sec.) N package (Soldering, 10 sec.) M package: Vapor Phase (60 sec.) Infrared (15 sec.) Thermal Resistance (θJA) (typicals) H package 215˚C/W (Board mount in still air) 85˚C/W (Board mount in 400LF/min air flow) N package 115˚C/W M package 106˚C/W θJC (H package, typical) 20˚C/W If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± 18V Supply Voltage Power Dissipation (Package Limitation) (Note 2) 500 mW Operating Ambient Temperature Range LF198/LF198A −55˚C to +125˚C LF298 −25˚C to +85˚C LF398/LF398A 0˚C to +70˚C Storage Temperature Range −65˚C to +150˚C Input Voltage Equal to Supply Voltage Logic To Logic Reference Differential Voltage (Note 3) +7V, −30V Output Short Circuit Duration Indefinite 10 sec 260˚C 260˚C 215˚C 220˚C Electrical Characteristics The following specifcations apply for −VS + 3.5V ≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA = Tj = 25˚C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified. Parameter Conditions LF198/LF298 Min Input Offset Voltage, (Note 5) Tj = 25˚C Max 1 3 5 25 Full Temperature Range Input Bias Current, (Note 5) Min Max 2 7 mV 10 mV 50 nA 100 nA 0.01 % 10 75 10 Input Impedance Tj = 25˚C 10 Gain Error Tj = 25˚C, RL = 10k 0.002 Full Temperature Range 10 0.005 86 96 Ω 10 0.004 0.02 Tj = 25˚C, Ch = 0.01 µF Units Typ 5 Tj = 25˚C Full Temperature Range Feedthrough Attenuation Ratio LF398 Typ 0.02 80 90 % dB at 1 kHz Output Impedance Tj = 25˚C, “HOLD” mode 0.5 Full Temperature Range 2 0.5 4 4 Ω 6 Ω “HOLD” Step, (Note 6) Tj = 25˚C, Ch = 0.01 µF, VOUT = 0 0.5 2.0 1.0 2.5 mV Supply Current, (Note 5) Tj≥25˚C 4.5 5.5 4.5 6.5 mA Logic and Logic Reference Input Tj = 25˚C 2 10 2 10 µA Leakage Current into Hold Tj = 25˚C, (Note 7) 30 100 30 200 pA Capacitor (Note 5) Hold Mode Acquisition Time to 0.1% ∆VOUT = 10V, Ch = 1000 pF 4 4 Current µs Ch = 0.01 µF 20 20 µs Hold Capacitor Charging Current VIN−VOUT = 2V 5 5 mA Supply Voltage Rejection Ratio VOUT = 0 80 110 80 110 dB Differential Logic Threshold Tj = 25˚C 0.8 1.4 2.4 0.8 1.4 2.4 V Input Offset Voltage, (Note 5) Tj = 25˚C 1 1 2 2 mV 3 mV 5 25 10 25 nA 50 nA Full Temperature Range Input Bias Current, (Note 5) 2 Tj = 25˚C Full Temperature Range www.national.com 75 2 Parameter Conditions LF198A Min Input Impedance Gain Error Typ Tj = 25˚C 1010 Tj = 25˚C, RL = 10k 0.002 Full Temperature Range Feedthrough Attenuation Ratio LF398A Max Min Units Typ Max Ω 1010 0.005 0.004 0.005 0.01 Tj = 25˚C, Ch = 0.01 µF 86 96 0.01 86 90 % % dB at 1 kHz Output Impedance Tj = 25˚C, “HOLD” mode 0.5 Full Temperature Range “HOLD” Step, (Note 6) 1 0.5 4 1 Ω 6 Ω Tj = 25˚C, Ch = 0.01µF, VOUT = 0 0.5 1 1.0 1 mV Supply Current, (Note 5) Tj≥25˚C 4.5 5.5 4.5 6.5 mA Logic and Logic Reference Input Tj = 25˚C 2 10 2 10 µA Tj = 25˚C, (Note 7) 30 100 30 100 pA Current Leakage Current into Hold Capacitor (Note 5) Hold Mode Acquisition Time to 0.1% ∆VOUT = 10V, Ch = 1000 pF 4 6 4 6 µs Ch = 0.01 µF 20 25 20 25 µs Hold Capacitor Charging Current VIN−VOUT = 2V Supply Voltage Rejection Ratio VOUT = 0 90 110 Differential Logic Threshold Tj = 25˚C 0.8 1.4 5 5 2.4 90 110 0.8 1.4 mA dB 2.4 V Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum junction temperature, TJMAX, for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C. Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the negative supply. Note 4: See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices. Note 5: These parameters guaranteed over a supply voltage range of ± 5 to ± 18V, and an input range of −VS + 3.5V ≤ VIN ≤ +VS − 3.5V. Note 6: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 7: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range. Note 8: A military RETS electrical test specification is available on request. The LF198 may also be procured to Standard Military Drawing #5962-8760801GA or to MIL-STD-38510 part ID JM38510/12501SGA. Typical Performance Characteristics Aperture Time (Note 9) Dielectric Absorption Error in Hold Capacitor Dynamic Sampling Error DS005692-19 DS005692-17 DS005692-18 Note 9: See Definition of Terms 3 www.national.com LF198/LF298/LF398, LF198A/LF398A Electrical Characteristics The following specifcations apply for −VS + 3.5V ≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA = Tj = 25˚C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified. LF198/LF298/LF398, LF198A/LF398A Typical Performance Characteristics Output Droop Rate (Continued) Hold Step “Hold” Settling Time (Note 10) DS005692-21 DS005692-20 DS005692-22 Leakage Current into Hold Capacitor Phase and Gain (Input to Output, Small Signal) DS005692-25 DS005692-23 Power Supply Rejection DS005692-24 Output Short Circuit Current DS005692-27 DS005692-26 Note 10: See Definition www.national.com Gain Error 4 Output Noise DS005692-28 Input Bias Current (Continued) Feedthrough Rejection Ratio (Hold Mode) Hold Step vs Input Voltage DS005692-31 DS005692-29 DS005692-30 Output Transient at Start of Sample Mode Output Transient at Start of Hold Mode DS005692-12 DS005692-13 Logic Input Configurations TTL & CMOS 3V ≤ VLOGIC (Hi State) ≤ 7V DS005692-33 Threshold = 1.4V DS005692-34 Threshold = 1.4V *Select for 2.8V at pin 8 5 www.national.com LF198/LF298/LF398, LF198A/LF398A Typical Performance Characteristics LF198/LF298/LF398, LF198A/LF398A Logic Input Configurations (Continued) CMOS 7V ≤ VLOGIC (Hi State) ≤ 15V DS005692-35 Threshold = 0.6 (V+) + 1.4V DS005692-36 Threshold = 0.6 (V+) − 1.4V Op Amp Drive DS005692-37 Threshold ≈ +4V DS005692-38 Threshold = −4V Application Hints Hold Capacitor Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values. Use of the curves included with this data sheet should be helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast signals, the capacitor drive currents may cause a significant temperature rise in the LF198. A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A mylar cap, for instance, may “sag back” up to 0.2% after a quick change in voltage. A long sample time is required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not nearly as good. The advantage of polypropylene over polystyrene is that it extends the maximum ambient temperature from 85˚C to 100˚C. Most ceramic capacitors are unusable with > 1% hysteresis. Ceramic “NPO” or “COG” capacitors are now available for 125˚C operation and also have low dielectric absorption. For more exact data, see the curve Dielectric Absorption Error. The hysteresis numbers on the curve are final values, taken after full relaxation. The hysteresis error can be significantly www.national.com reduced if the output of the LF198 is digitized quickly after the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10 — 50 ms. If A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten. DC and AC Zeroing DC zeroing is accomplished by connecting the offset adjust pin to the wiper of a 1 kΩ potentiometer which has one end tied to V+ and the other end tied through a resistor to ground. The resistor should be selected to give ≈0.6 mA through the 1k potentiometer. AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output. A 10 pF capacitor from the wiper to the hold capacitor will give ± 4 mV hold step adjustment with a 0.01 µF hold capacitor and 5V logic supply. For larger logic swings, a smaller capacitor ( < 10 pF) may be used. Logic Rise Time For proper operation, logic signals into the LF198 must have a minimum dV/dt of 1.0 V/µs. Slower signals will cause excessive hold step. If a R/C network is used in front of the 6 LF198/LF298/LF398, LF198A/LF398A Application Hints (Continued) Guarding Technique logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least 1.0 V/µs. Sampling Dynamic Signals Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other parameter. The primary reason for this is that many users make the assumption that the sample and hold amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays through the circuit creating an input-output differential for fast moving signals. In addition, although the output may have settled, the hold capacitor has an additional lag due to the 300Ω series resistor on the chip. This means that at the moment the “hold” command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which switches the circuit from sample to hold. For example, consider an analog input of 20 Vp-p at 10 kHz. Maximum dV/dt is 0.6 V/µs. With no analog phase delay and 100 ns logic delay, one could expect up to (0.1 µs) (0.6V/µs) = 60 mVerror if the “hold” signal arrived near maximum dV/dt of the input. A positive-going input would give a +60 mV error. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a phase delay of 160 ns. If the hold capacitor sees this exact delay, then error due to analog delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To add to the confusion, analog delay is proportioned to hold capacitor value while digital delay remains constant. A family of curves (dynamic sampling error) is included to help estimate errors. A curve labeled Aperture Time has been included for sampling conditions where the input is steady during the sampling period, but may experience a sudden change nearly coincident with the “hold” command. This curve is based on a 1 mV error fed into the output. A second curve, Hold Settling Time indicates the time required for the output to settle to 1 mV after the “hold” command. DS005692-5 Use 10-pin layout. Guard around Chis tied to output. Digital Feedthrough Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as possible from the analog input and the Ch pin. Grounded guarding traces may also be used around the input line, especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also help. 7 www.national.com LF198/LF298/LF398, LF198A/LF398A Typical Applications X1000 Sample & Hold Sample and Difference Circuit (Output Follows Input in Hold Mode) DS005692-40 VOUT = VB + ∆VIN(HOLD MODE) DS005692-39 *For lower gains, the LM108 must be frequency compensated Ramp Generator with Variable Reset Level Integrator with Programmable Reset Level DS005692-42 DS005692-43 www.national.com 8 LF198/LF298/LF398, LF198A/LF398A Typical Applications (Continued) Output Holds at Average of Sampled Input Increased Slew Current DS005692-46 DS005692-47 Reset Stabilized Amplifier (Gain of 1000) Fast Acquisition, Low Droop Sample & Hold DS005692-49 DS005692-50 9 www.national.com LF198/LF298/LF398, LF198A/LF398A Typical Applications (Continued) Synchronous Correlator for Recovering Signals Below Noise Level 2–Channel Switch DS005692-53 A B Gain 1 ± 0.02% 1 ± 0.2% ZIN 1010Ω 47 kΩ BW . 1 MHz . 400 kHz Crosstalk −90 dB −90 dB ≤ 6 mV ≤ 75 mV @ 1 kHz Offset DS005692-52 DC & AC Zeroing Staircase Generator DS005692-59 DS005692-55 *Select for step height 50k → ≅ 1V Step www.national.com 10 LF198/LF298/LF398, LF198A/LF398A Typical Applications (Continued) Differential Hold Capacitor Hysteresis Compensation DS005692-56 DS005692-57 **Adjust for amplitude Definition of Terms Hold Settling Time: The time required for the output to settle within 1 mV of final value after the “hold” logic command. Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note that this error term occurs even for long sample times. Aperture Time: The delay required between “Hold” command and an input analog transition, so that the transition does not affect the held output. Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold mode with a steady (dc) analog input voltage. Logic swing is 5V. Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to settle, but also includes the time required for all internal nodes to settle so that the output assumes the proper value when switched to the hold mode. Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent difference. Connection Diagrams Dual-In-Line Package Small-Outline Package Metal Can Package DS005692-15 DS005692-11 Order Number LF398N or LF398AN See NS Package Number N08E Order Number LF298M or LF398M See NS Package Number M14A DS005692-14 Order Number LF198H, LF198H/883, LF298H, LF398H, LF198AH or LF398AH See NS Package Number H08C (Note 8) 11 www.national.com LF198/LF298/LF398, LF198A/LF398A Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LF198H, LF298H, LF398H, LF198AH or LF398AH NS Package Number H08C Molded Small-Outline Package (M) Order Number LF298M or LF398M NS Package Number M14A www.national.com 12 inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number LF398N or LF398AN NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits Physical Dimensions a CMOS 8-/16-Channel Analog Multiplexers ADG506A/ADG507A FUNCTIONAL BLOCK DIAGRAM FEATURES 44 V Supply Maximum Rating V SS to VDD Analog Signal Range Single/Dual Supply Specifications Wide Supply Ranges (10.8 V to 16.5 V) Extended Plastic Temperature Range (–40ⴗC to +85ⴗC) Low Power Dissipation (28 mW max) Low Leakage (20 pA typ) Available in 28-Lead DIP, SOIC, PLCC, TSSOP and LCCC Packages Superior Alternative to: DG506A, Hl-506 DG507A, Hl-507 GENERAL DESCRIPTION The ADG506A and ADG507A are CMOS monolithic analog multiplexers with 16 channels and dual 8 channels, respectively. The ADG506A switches one of 16 inputs to a common output, depending on the state of four binary addresses and an enable input. The ADG507A switches one of eight differential inputs to a common differential output, depending on the state of three binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic compatible digital inputs. The ADG506A and ADG507A are designed on an enhanced LC2MOS process, which gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can operate comfortably anywhere in the 10.8 V to 16.5 V single or dual supply range. These multiplexers also feature high switching speeds and low RON. PRODUCT HIGHLIGHTS 1. Single/Dual Supply Specifications with a Wide Tolerance The devices are specified in the 10.8 V to 16.5 V range for both single and dual supplies. 2. Extended Signal Range The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of VSS to VDD. 3. Break-Before-Make Switching Switches are guaranteed break-before-make so input signals are protected against momentary shorting. ORDERING GUIDE Model1 Temperature Range Package Option2 ADG506AKN ADG506AKR ADG506AKP ADG506ABQ ADG506ATQ ADG506ATE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C N-28 R-28 P-28A Q-28 Q-28 E-28A ADG507AKN ADG507AKR ADG507AKP ADG507AKRU ADG507ABQ ADG507ATQ ADG507ATE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C N-28 R-28 P-28A RU-28 Q-28 Q-28 E-28A NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. See Analog Devices’ Military/Aerospace Reference Manual (1994) for military data sheet. 2 E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = 0.3" Small Outline IC (SOIC); RU = Thin Shrink Small Outline Package (TSSOP). 4. Low Leakage Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADG506A/ADG507A–SPECIFICATIONS Dual Supply (V DD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V unless otherwise noted) Parameter ANALOG SWITCH Analog Signal Range RON ADG506A ADG506A ADG507A ADG507A K Version B Version –40ⴗC to –40ⴗC to +25ⴗC +85ⴗC +25ⴗC +85ⴗC ADG506A ADG507A T Version –55ⴗC to +25ⴗC +125ⴗC VSS VDD 280 450 300 VSS VDD 280 450 VSS VDD 300 0.6 5 400 RON Drift RON Match 0.6 5 IS (OFF), Off Input Leakage 0.02 1 0.04 1 1 0.04 1 1 ID (OFF), Off Output Leakage ADG506A ADG507A ID (ON), On Channel Leakage ADG506A ADG507A IDIFF, Differential Off Output Leakage (ADG507A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION 1 tOPEN 1 tON (EN)1 tOFF (EN) 1 OFF Isolation CS (OFF) CD (OFF) ADG506A ADG507A QINJ, Charge Injection POWER SUPPLY IDD VSS VDD 600 400 50 200 100 200 100 0.02 1 0.04 1 1 0.04 1 1 50 200 100 200 100 0.02 1 0.04 1 1 0.04 1 1 600 V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 5 2.4 0.8 1 2.4 0.8 1 2.4 0.8 1 V min V max µA max pF max 10 400 400 200 300 50 25 200 300 200 300 8 400 10 400 400 200 300 50 25 200 300 200 300 VDD = 15 V (± 10%), VSS = –15 V (± 10%) VDD = 15 V (± 5%), VSS = –15 V (± 5%) –10 V ≤ VS ≤ +10 V, IDS = 1 mA –10 V ≤ VS ≤ +10 V, IDS = 1 mA 200 100 200 100 nA max 400 –10 V ≤ VS ≤ +10 V, IDS = 1 mA; Test Circuit 1 V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 2 25 8 Comments nA typ nA max nA typ nA max nA max nA typ nA max nA max 50 25 400 10 400 400 ns typ ns max ns typ ns min ns typ ns max ns typ ns max V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 3 V1 = ± 10 V, V2 = ⫿10 V; Test Circuit 4 VIN = 0 to VDD V1 = ± 10 V, V2 = +10 V; Test Circuit 6 Test Circuit 7 Test Circuit 8 Test Circuit 8 68 50 5 68 50 5 68 50 5 dB typ dB min pF typ VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF, VS = 7 V rms, f = 100 kHz VEN = 0.8 V 44 22 4 44 22 4 44 22 4 pF typ pF typ pC typ VEN = 0.8 V 0.6 0.6 20 0.6 1.5 20 0.2 Power Dissipation 600 400 V min V max Ω typ Ω max Ω max Ω max %/°C typ % typ 25 1.5 ISS VSS VDD 0.6 5 8 200 300 50 25 200 300 200 300 VSS VDD 280 450 300 Units 10 20 0.2 10 28 1.5 0.2 10 28 28 RS = 0 Ω, VS = 0 V; Test Circuit 9 mA typ VIN = VINL or VlNH mA max µA typ VIN = VIN or VINH mA max mW typ mW max NOTES 1 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. –2– REV. C Single Supply (V ADG506A/ADG507A DD = +10.8 V to +16.5 V, VSS = GND = 0 V unless otherwise noted) Parameter ANALOG SWITCH Analog Signal Range RON RON Drift RON Match IS (OFF), Off Input Leakage ID (OFF), Off Output Leakage ADG506A ADG507A ID (ON), On Channel Leakage ADG506A ADG507A IDIFF, Differential Off Output Leakage (ADG507A Only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance DYNAMIC CHARACTERISTICS tTRANSITION 1 tOPEN 1 tON (EN)1 tOFF (EN) 1 OFF Isolation CS (OFF) CD (OFF) ADG506A ADG507A QINJ, Charge Injection POWER SUPPLY IDD ADG506A ADG506A ADG507A ADG507A K Version B Version –40ⴗC to –40ⴗC to +25ⴗC +85ⴗC +25ⴗC +85ⴗC ADG506A ADG507A T Version –55ⴗC to +25ⴗC +125ⴗC Units VSS VDD 500 700 0.6 5 VSS VDD 500 700 0.6 5 V min V max Ω typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA; Test Circuit 1 Ω max %/°C typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA % typ 0 V ≤ VS ≤ +10 V, IDS = 0.5 mA 0.02 1 0.04 1 1 0.04 1 1 VSS VDD 1000 50 200 100 200 100 VSS VDD 1000 0.02 1 0.04 1 1 0.04 1 1 200 100 200 100 1000 200 100 nA typ nA max nA typ nA max nA max nA typ nA max nA max 50 200 100 25 25 nA max 2.4 0.8 1 2.4 0.8 1 2.4 0.8 1 V min V max µA max pF max 8 600 10 600 600 8 300 450 50 25 250 450 250 450 300 450 50 25 250 450 250 450 600 10 600 600 600 10 600 600 V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 4 V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 5 VIN = 0 to VDD ns typ ns max ns typ ns min ns typ ns max ns typ ns max V1 = +10 V/0 V, V2 = +10 V; Test Circuit 6 Test Circuit 7 Test Circuit 8 Test Circuit 8 68 50 5 68 50 5 dB typ dB min pF typ VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF, VS = 3.5 V rms, f = 100 kHz VEN = 0.8 V 44 22 4 44 22 4 44 22 4 pF typ pF typ pC typ VEN = 0.8 V 0.6 0.6 0.6 10 1.5 1.5 10 10 25 25 25 NOTES 1 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. RS = 0 Ω, VS = 0 V; Test Circuit 9 mA typ VIN = VINL or VlNH mA max mW typ mW max Truth Table (ADG506A) Truth Table (ADG507A) A3 EN On Switch A2 A1 A0 EN On Switch Pair 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 REV. C V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 2 V1 = +10 V/0 V, V2 = 0 V/ +10 V; Test Circuit 3 68 50 5 1.5 Power Dissipation 0.02 1 0.04 1 1 0.04 1 1 50 VSS VDD 25 8 300 450 50 25 250 450 250 450 VSS VDD 500 700 0.6 5 Comments A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 –3– NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X = Don’t Care NONE 1 2 3 4 5 6 7 8 ADG506A/ADG507A Power Dissipation (Any Package) Up to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V Analog Inputs2 Voltage at S, D . . . . . . . . . . . . . . . . . . . . . . . VSS – 2 V to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 2 V or . . . . . . . . . . . . . . . . . . . . . . 20 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Pulsed Current S or D 1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . . 40 mA Digital Inputs2 Voltage at A, EN . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to VDD + 4 V or . . . . . . . . . . . . . . . . . . . . . . 20 mA, Whichever Occurs First NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Overvoltage at A, EN, S or D will be clamped by diodes. Current should be limited to the Maximum Rating above. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG506A /ADG507A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATIONS DIP, SOIC LCCC S6 ADG506A 24 S14 6 TOP VIEW 23 S5 S13 7 (Not to Scale) 22 S4 S15 5 25 S7 S14 6 24 S6 3 2 1 28 27 26 S8 VSS VDD D 4 PIN 1 IDENTIFIER S15 5 25 S7 S14 6 24 S6 ADG506A 23 S5 TOP VIEW (Not to Scale) 22 S4 S13 7 ADG506A 23 S5 21 S3 S12 8 TOP VIEW (Not to Scale) 22 S4 S13 7 S12 8 NC 28 27 26 S16 1 NC 2 S8 3 D 4 VSS 25 S7 NC 26 S8 S16 4 VDD 27 VSS NC 3 S16 NC 2 S15 5 PLCC 28 D NC VDD 1 S12 8 21 S3 S11 9 S11 9 20 S2 S10 10 20 S2 S11 9 21 S3 S10 10 19 S1 S9 11 19 S1 S10 10 20 S2 S9 11 19 S1 A0 18 EN 16 17 A1 14 15 A2 15 A2 NC = NO CONNECT NC GND 12 13 NC = NO CONNECT A3 EN A0 A1 16 A1 A3 14 A2 NC 13 12 13 14 15 16 17 18 A3 17 A0 NC 18 EN GND S9 11 GND 12 NC = NO CONNECT DIP, SOIC, TSSOP TOP VIEW 23 S5A S5B 7 (Not to Scale) 22 S4A S7B 5 25 S7A S6B 6 24 S6A S5A S5B 7 ADG507A 23 S4B 8 TOP VIEW (Not to Scale) 22 S4A 21 DA 4 3 2 1 28 27 26 VSS VDD 28 27 26 DB 1 S8B 2 NC S8A S6A ADG507A 24 S6B 6 3 DA S7B 5 4 VSS 25 S7A DB 26 S8A S8B 4 VDD 27 VSS NC 3 S8B DB 2 NC 28 DA S8A PLCC LCCC VDD 1 PIN 1 IDENTIFIER S7B 5 25 S7A S6B 6 24 S6A S5B 7 ADG507A 23 S5A S3A S4B 8 TOP VIEW (Not to Scale) 22 S4A S4B 8 21 S3A S3B 9 20 S2A S2B 10 20 S2A S3B 9 21 S3A S2B 10 19 S1A S1B 11 19 S1A S2B 10 20 S2A S1B 11 19 S1A NC = NO CONNECT 18 EN A0 16 17 A1 A2 14 15 NC NC NC = NO CONNECT 12 13 GND EN 15 A2 A0 NC 14 A1 16 A1 A2 NC 13 12 13 14 15 16 17 18 NC 17 A0 NC 18 EN GND S1B 11 GND 12 S3B 9 NC = NO CONNECT –4– REV. C Typical Performance Characteristics–ADG506A/ADG507A The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V. Figure 1. RON as a Function of VD (VS): Dual Supply Voltage, TA = +25 °C Figure 4. RON as a Function of VD (VS) Single Supply Voltage, TA = +25 °C Figure 2. Leakage Current as a Function of Temperature (Note: Leakage Currents Reduce as the Supply Voltages Reduce) Figure 5. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = +25 °C Figure 3. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = + 25°C (Note: For VDD and /VSS / < 10 V; V1 = VDD /VSS, V2 = VSS /VDD. See Test Circuit 6) REV. C Figure 6. IDD vs. Supply Voltage: Dual or Single Supply, TA = +25 °C –5– ADG506A/ADG507A–Test Circuits Note: All Digital Input Signal Rise and Fall Times Measured from 10% to 90% of 3 V. tR = tF = 20 ns. Test Circuit 2. IS (OFF) Test Circuit 1. RON Test Circuit 3. ID (OFF) Test Circuit 5. IDIFF Test Circuit 4. ID (ON) Test Circuit 6. Switching Time of Multiplexer, tTRANSITION Test Circuit 7. Break-Before-Make Delay, tOPEN –6– REV. C ADG506A/ADG507A Test Circuit 8. Enable Delay, tON (EN), tOFF (EN) Test Circuit 9. Charge Injection SINGLE SUPPLY AUTOMOTIVE APPLICATION The excellent performance of the multiplexers under single supply conditions makes the ADG506A/ADG507A suitable in applications such as automotive and disc drives where only positive power supply voltages are normally available. The following application circuit shows the ADG507A connected as an 8-channel differential multiplexer in an automotive, data acquisition application circuit. The AD7580 is a 10-bit successive approximation ADC, which has an on-chip sample-hold amplifier and provides a conversion result in 20 µs. The ADC has differential analog inputs and is configured in the application circuit for a span of 2.5 V over a common-mode range 0 V to + 5 V. Wider common-mode ranges can be accommodated. See the AD7579/AD7580 data sheet for more details. The complete system operates from +12 V (+10%) and +5 V supplies. The analog input signals to the ADG507A contain information such as temperature, pressure, speed etc. Figure 7. ADG507A in a Single Supply Automotive Data Acquisition Application REV. C –7– TERMINOLOGY tOFF (EN) RON RON Match RON Drift IS (OFF) tTRANSITION Ohmic resistance between terminals D and S Difference between the RON of any two channels Change in RON versus temperature Source terminal leakage current when the switch is off Drain terminal leakage current when the switch is off Leakage current that flows from the closed switch into the body Analog voltage on terminal S or D Channel input capacitance for “OFF” condition Channel output capacitance for “OFF” condition Digital input capacitance Delay time between the 50% and 90% points of the digital input and switch “ON” condition ID (OFF) ID (ON) VS (VD) CS (OFF) CD (OFF) CIN tON (EN) Delay time between the 50% and 10% points of the digital input and switch “OFF” condition Delay time between the 50% and 90% points of the digital inputs and switch “ON” condition when switching from one address state to another “OFF” time measured between 50% points of both switches when switching from one address state to another Maximum input voltage for Logic “0” Minimum input voltage for Logic “1” Input current of the digital input Most positive voltage supply Most negative voltage supply Positive supply current Negative supply current tOPEN VINL VINH IINL (IINH) VDD VSS IDD ISS C1150c–0–6/98 ADG506A/ADG507A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Suffix Q) 28-Lead Plastic DIP (Suffix N) 1.490 (37.84) MAX 0.550 (13.97) 0.53 (13.47) 0.525 (13.33) 0.515 (13.08) 1.45(36.83) 1.44 (36.58) 0.606 (15.4) 0.594 (15.09) 0.16 (4.07) 0.14 (3.56) 0.22 (5.59) GLASS MAX SEALANT 0.2 (5.08) MAX 0.020 (0.508) 0.105 (2.67) 0.015 (0.381) 0.095 (2.42) 0.012 (0.305) 0.175 (4.45) 0.008 (0.203) 0.12 (3.05) 0.11 (2.79) 0.099 (2.28) 0.386 (9.80) 0.378 (9.60) 0.1043 (2.65) 0.0926 (2.35) PIN 1 IDENTIFIER 8° 0.0500 (1.27) 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 26 25 TOP VIEW 11 12 19 18 0.456 (11.582) 0.450 (11.430) SQ 0.498 (12.57) SQ 0.485 (12.32) 14 SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.028 (0.70) 0.020 (0.50) 8° 0° 0.0079 (0.20) 0.0035 (0.090) 28-Terminal Leadless Ceramic Chip Carrier (Suffix E) 0.050 ⴞ0.005 01.27 ⴞ0.13 0.021 (0.533) 0.430 (10.5) 0.013 (0.331) 0.390 (9.9) 0.032 (0.812) 0.026 (0.661) (PINS DOWN) 1 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0291 (0.74) x 45° 0.0098 (0.25) 28-Terminal Plastic Leaded Chip Carrier (Suffix P) 4 15 0.256 (6.50) 0.246 (6.25) 14 28 0.177 (4.50) 0.169 (4.30) 1 0.4193 (10.65) 0.3937 (10.00) 15 0.2992 (7.60) 0.2914 (7.40) 28 5 0.012 (0.305) 0.008 (0.203) 15° 0° 28-Lead TSSOP (Suffix RU) 0.7125 (18.10) 0.6969 (17.70) 0.0500 (1.27) BSC 0.02 (0.5) 0.016 (0.406) 0.18(4.57) MAX LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 28-Lead SOIC (Suffix R) 0.0118 (0.30) 0.0040 (0.10) 0.125 (3.175) MIN 15ⴗ 0 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 PIN 1 0.62 (15.74) 0.59 (14.93) 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.458 (11.63) 0.442 (11.23) 0.458 SQ (11.63) MAX SQ 0.120 (3.04) 0.090 (2.29) 0.180 (4.51) 0.165 (4.20) 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) –8– 26 2 5 0.300 (7.62) BSC 0.150 (3.51) BSC 4 28 5 1 BOTTOM VIEW 19 18 0.055 (1.40) 0.045 (1.14) 12 11 0.200 (5.08) BSC 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 45° TYP REV. C PRINTED IN U.S.A. 0.065 (1.66) 0.045 (1.15) 0.06 (1.52) 0.05 (1.27) Revised April 2002 CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer General Description Features The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. ■ Wide range of digital and analog signal levels: digital 3 – 15V, analog to 15Vp-p CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output. CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs. ■ Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p signal-input range for VDD − VEE = 15V ■ High “OFF” resistance: channel leakage of ±10 pA (typ.) at VDD − VEE = 10V ■ Logic level conversion for digital addressing signals of 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals to 15 Vp-p (VDD − VEE = 15V) ■ Matched switch characteristics: ∆RON = 5Ω (typ.) for VDD − VEE = 15V ■ Very low quiescent power dissipation under all digital-control input and supply conditions: 1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V ■ Binary address decoding on chip CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole double-throw configuration. Ordering Code: Order Number CD4051BCM CD4051BCSJ CD4051BCMTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide CD4051BCN N16E CD4052BCM M16A 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 Fairchild Semiconductor Corporation DS005662 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer November 1983 CD4051BC • CD4052BC • CD4053BC Connection Diagrams Pin Assignments for DIP and SOIC CD4051BC CD4052BC CD4053BC Truth Table INPUT STATES “ON” CHANNELS INHIBIT C B A CD4051B CD4052B CD4053B 0 0 0 0 0 0X, 0Y cx, bx, ax 0 0 0 1 1 1X, 1Y cx, bx, ay 0 0 1 0 2 2X, 2Y cx, by, ax 0 0 1 1 3 3X, 3Y 0 1 0 0 4 cy, bx, ax 0 1 0 1 5 cy, bx, ay 0 1 1 0 6 cy, by, ax 0 1 1 1 7 1 * * * NONE *Don’t Care condition. www.fairchildsemi.com cx, by, ay 2 cy, by, ay NONE NONE CD4051BC • CD4052BC • CD4053BC Logic Diagrams CD4051BC CD4052BC 3 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Logic Diagrams (Continued) CD4053BC www.fairchildsemi.com 4 DC Supply Voltage (VDD) Input Voltage (VIN) Recommended Operating Conditions −0.5 VDC to +18 VDC −0.5 VDC to VDD +0.5 VDC Input Voltage (VIN) −65°C to +150°C Range (TS) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) CD4051BC/CD4052BC/CD4053BC Dual-In-Line 700 mW Small Outline 500 mW 260°C (soldering, 10 seconds) DC Electrical Characteristics Parameter −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions for actual device operation. Lead Temperature (TL) Symbol +5 VDC to +15 VDC DC Supply Voltage (VDD) Storage Temperature (Note 2) −55°C Conditions Min +25° Max Min Typ 125°C Max Min Max Units Control A, B, C and Inhibit IIN Input Current VDD = 15V, VEE = 0V VIN = 0V VDD = 15V, Quiescent Device Current −10−5 0.1 10−5 −0.1 −1.0 µA VEE = 0V VIN = 15V IDD −0.1 0.1 1.0 VDD = 5V 5 5 150 VDD = 10V 10 10 300 VDD = 15V 20 20 600 µA Signal Inputs (VIS) and Outputs (VOS) RON “ON” Resistance (Peak RL = 10 kΩ VDD = 2.5V, for VEE ≤ VIS ≤ VDD) (any channel VEE = −2.5V selected) or VDD = 5V, 800 270 1050 1300 Ω 310 120 400 550 Ω 200 80 240 320 Ω VEE = 0V VDD = 5V, VEE = −5V or VDD = 10V, VEE = 0V VDD = 7.5V, VEE = −7.5V or VDD = 15V, VEE = 0V ∆RON ∆ “ON” Resistance RL = 10 kΩ VDD = 2.5V, Between Any Two (any channel VEE = −2.5V Channels selected) or VDD = 5V, 10 Ω 10 Ω 5 Ω VEE = 0V VDD = 5V VEE = −5V or VDD = 10V, VEE = 0V VDD = 7.5V, VEE = −7.5V or VDD = 15V, VEE = 0V “OFF” Channel Leakage VDD=7.5V, VEE=−7.5V ±50 ±0.01 ±50 ±500 CD4051 ±200 ±0.08 ±200 ±2000 D4052 ±200 ±0.04 ±200 ±2000 CD4053 ±200 ±0.02 ±200 ±2000 Current, any channel “OFF” O/I=±7.5V, I/O=0V “OFF” Channel Leakage Inhibit = 7.5V Current, all channels VDD = 7.5V, “OFF” (Common VEE = −7.5V, OUT/IN) O/I = 0V I/O = ±7.5V 5 nA nA www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Absolute Maximum Ratings(Note 1) CD4051BC • CD4052BC • CD4053BC DC Electrical Characteristics Symbol Parameter (Continued) −55°C Conditions Min +25° Max Min Typ 125°C Max Min Max Units Control Inputs A, B, C and Inhibit VIL LOW Level Input Voltage VEE = VSS RL = 1 kΩ to VSS IIS<2 µA on all OFF Channels VIS = VDD thru 1 kΩ VIH HIGH Level Input Voltage VDD = 5V 1.5 1.5 1.5 VDD = 10V 3.0 3.0 3.0 VDD = 15V 4.0 4.0 4.0 VDD = 5 3.5 3.5 VDD = 10 7 7 7 VDD = 15 11 11 11 Note 2: All voltages measured with respect to VSS unless otherwise specified. www.fairchildsemi.com 6 V 3.5 V (Note 3) TA = 25°C, tr = tf = 20 ns, unless otherwise specified. Symbol tPZH, tPZL Parameter Propagation Delay Time from Conditions VEE = VSS = 0V VDD 5V Min Typ Max 600 1200 Inhibit to Signal Output RL = 1 kΩ 10V 225 450 (channel turning on) CL = 50 pF 15V 160 320 420 tPHZ, Propagation Delay Time from VEE = VSS = 0V 5V 210 tPLZ Inhibit to Signal Output RL = 1 kΩ 10V 100 200 (channel turning off) CL = 50 pF 15V 75 150 Control input 5 7.5 Signal Input (IN/OUT) 10 15 CIN COUT Units ns ns Input Capacitance pF Output Capacitance (common OUT/IN) CD4051 CD4052 VEE = VSS = 0V CD4053 CIOS Feedthrough Capacitance CPD Power Dissipation Capacitance 10V 30 10V 15 10V 8 pF 0.2 CD4051 110 CD4052 140 CD4053 70 pF pF Signal Inputs (VIS) and Outputs (VOS) Sine Wave Response (Distortion) RL = 10 kΩ fIS = 1 kHz 10V 0.04 % 10V 40 MHz 10V 10 MHz 10V 3 MHz VIS = 5 Vp-p VEE = VSI = 0V Frequency Response, Channel RL = 1 kΩ, VEE = 0V, VIS = 5Vp-p, “ON” (Sine Wave Input) 20 log10 VOS/VIS = −3 dB Feedthrough, Channel “OFF” RL = 1 kΩ, VEE = VSS = 0V, VIS = 5Vp-p, 20 log10 VOS/VIS = −40 dB Crosstalk Between Any Two RL = 1 kΩ, VEE = VSS = 0V, VIS(A) = 5Vp-p Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4) tPHL Propagation Delay Signal VEE = VSS = 0V 5V 25 55 tPLH Input to Signal Output CL = 50 pF 10V 15 35 15V 10 25 10V 65 ns Control Inputs, A, B, C and Inhibit Control Input to Signal Crosstalk VEE = VSS = 0V, RL = 10 kΩ at both ends of channel. mV (peak) Input Square Wave Amplitude = 10V tPHL, Propagation Delay Time from VEE = VSS = 0V 5V 500 1000 tPLH Address to Signal Output CL = 50 pF 10V 180 360 15V 120 240 (channels “ON” or “OFF”) ns Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”. 7 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC AC Electrical Characteristics CD4051BC • CD4052BC • CD4053BC Special Considerations switch must not exceed 0.6V at TA ≤ 25°C, or 0.4V at TA > 25°C (calculated from RON values shown). No VDD current will flow through RL if the switch current flows into OUT/IN pin. In certain applications the external load-resistor current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into IN/OUT pin, the voltage drop across the bidirectional Typical Performance Characteristics “ON” Resistance vs Signal Voltage for TA = 25°C “ON” Resistance as a Function of Temperature for VDD− VEE = 10V “ON” Resistance as a Function of Temperature for VDD− VEE = 15V “ON” Resistance as a Function of Temperature for VDD − VEE = 5V www.fairchildsemi.com 8 CD4051BC • CD4052BC • CD4053BC Switching Time Waveforms 9 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 10 CD4051BC • CD4052BC • CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 11 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 12 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 13 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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