Polyphase Realisation of Fractional Sample Rate
Converters

Heinz G. GOCKLER
Abstract
By suitably decomposing the highly inecient
structure of Fig.1 into polyphase components, it is
The polyphase approach to synchronous fractional possible to perform all arithmetic operations at the
sample rate conversion by L=M , where L, M are co- subnyquist rate
prime integers, is revisited. In contrast to existing
publications [1-5], a rigorous, systematic and yet Fs = F = Fi = Fo , zs = esTLM = z LM (3)
LM M
L
straightforward derivation of an optimum causal
implementation is deduced.
A heuristic derivation of this approach is given in
[1,2]. An optimum polyphase structure of a frac1 Introduction
tional sample rate converter was disclosed in a USA particular and important case of the omnipresent patent [3] and two conference papers [4,5], respecneed of sample rate alteration in digital signal pro- tively. This approach requires one input commucessing is the conversion of the sampling rate by a tator for M -fold decimation, and one output comnoninteger factor L=M , where L and M are pos- mutator for L-fold sample interleaving. All operitive, relatively prime integers. The system theo- ations (including memory shift) are performed at
retic approach to fractional sample rate alteration the subnyquist rate Fs . In [3-5], however, a proper
is characterised by the cascade connection of an in- step-by-step derivation of this polyphase structure
terpolator for L-fold rate increase followed by a dec- is missing. Hence, a rigorous, systematic derivation
imator for M -fold rate reduction [1,2] according to of an optimum polyphase realisation of the above
Fig.1, where the interpolator and decimator lters dened fractional sample rate converter (FSRC) is
have merged in one lter H (z ). Here, all lter op- developed subsequently.
erations have to be performed at the highest rate
F = 1=T (T : Sampling period), which is related to 2 An Optimum Polyphase Realisation
the system input rate Fi and output rate Fo in a Starting from Fig.1 let
synchronous manner by
H (z ) = z ; Hc (z );
2 N0
(4)
F = LFi = MFo
(1)
where Hc (z ) represents a causal, possibly minimum
phase FIR or IIR lter. Due to the extra memory,
H (z ) is no longer minimum phase but still causal
and, hence, realisable.
The derivation of the optimum FSRC realisation
is subdivided into ve steps. In Step 1, the
lter H (z ) is decomposed into polyphase
Figure 1: Systemtheoretic approach to fractional FSRC
components,
where subsequently always type 1
sample rate conversion (FSRC)
polyphase decomposition [1] is applied. In Step 2,
the sequential order of these polyphase components
As a result, the z -domain representations of the in- is systematically rearranged, such that the noble
put and output signals of Fig.1 are related to the identities [1] can readily be exploited in Step 3.
respective input and output sampling rates [1,2] ac- In Step 4, each original polyphase component is
cording to
subjected to a second polyphase decomposition,
sT
sTL
L
sT
sTM
M
i
o
zi = e = e
= z and zo = e = e
= z thus yielding an optimum FSRC structure: Block(2) ing the input signal into a length-M vector-valued
signal, which is the input to a multiple-input
Digital Signal Processing Group, Ruhr-Universit
at multiple-output (MIMO) linear time-invariant
Bochum, D-44780 Bochum, Germany
(LTI) system producing a length-L vector-valued
email: [email protected]
This work was supported by Deutsche Forschungsgemein- signal at its output that, subsequently, is unblocked
schaft under contract GO 849/1-1
to form the output signal. Finally, the optimum
polyphase realisation with one input and one
output commutator each is presented in Step 5.
Polyphase decomposition is straightforward for
FIR lters [1,2] whereas, in general, a standard
IIR lter transfer function must be subjected to
an equivalence transformation before polyphase
decomposition can be applied [6].
Step 1: Polyphase Decomposition of Hc(z)
In the derivation procedure we start, for instance,
with an L-branch polyphase decomposition of the
FSRC lter [1,2]:
H (z ) = z ;
LX
;1
z ;l Hl (z L )
l=0
(5)
Step 2: Systematic Rearrangement of Sequential Figure 2: Rearranged polyphase decomposition acOrder of Polyphase Components according to (5) cording to step 2
The rst polyphase decomposition (5) is rearranged
by mapping of the summation index l according to
l := (lM )L = (lM ) modulo L = lM ; pl L
(6) It is observed from (10) in comparison with (4) and
(5) that all the rearranged polyphase components
where l = 0; 1; :::; L ; 1, pl 2 N 0 and 0 pl pL;1 . are causal and, thus, immediately realisable.
This substitution represents a one-to-one mapping This is accomplished by the additional memory
on f0; 1; :::; L ; 1g since L and M are coprime. introduced in (5) with according to (7) and (8).
Upper and lower bounds of pL;1 are readily de- By this choice of it is also guaranteed that the
duced from (6) using the fact that l = 0 is def- extra delay is minimum. This follows from (10)
initely related to p0 = 0, limiting the remaining since for l = L ; 1, the rearranged polyphase
mapped indices to 1 (lM )L L ; 1. Introducing component is identical to the original polyphase
l = L ; 1 into these inequalities in conjunction with component of (5) with index ([L ; 1]M )L . Finally,
the right hand side of (6), yields the upper bound it should be noticed that all components of (10)
of pL;1 2 N :
are mere functions of z L; Fig.2.
(L ; 1)M ; 1
pL;1 =
(7) Step 3: Application of Noble Identities [1]
L
The structure obtained so far by decomposition
where 0 x ; bxc < 1. By introducing the index of H (z ) according to (9) and Fig.2 represents a
mapping (6) into (5) and by setting in compliance polyphase input interpolator of the FSRC with
subsequent decimation by M , such that all L
with (7)
= pL;1 L
(8) branch lters (10) receive identical input signals
expanded by L [1,2]. Next, by applying the
we get
noble identities [1] to the branch lters and the
output delay chain of (9) being composed of delays
LX
;1
that are multiples of z ;M , the input expander
H (z ) = z ;pL;1 L
z ;(lM ;pl L) H(lM )L (z L )
and the output decimator are shifted into the
l=0
decomposed FSRC polyphase lter until they are
LX
;1
=
z ;lM El (z L )
(9) directly cascaded at the output of each polyphase
branch lter. Reversing the sequential order of
l=0
the expander-decimator cascade, as justied in [1],
where the quantities
results in the transformed structure as shown in
Fig.3. The associated polyphase representation,
El (z L ) = H(lM )L (z L )z ;(pL;1 ;pl )L
(10) derived from (9), is given by
represent the reordered components of the LLX
;1
LX
;1
branch polyphase decomposition of the FSRC lter
H (z ) =
z ;lM El (z L ) =
zo;l El (zi ) (11)
H (z ), as depicted in Fig.2.
l=0
l=0
where the z-domain variables are related to the op- the polyphase representation (11) yields:
erating sampling rates according to (2).
LX
;1
LX
;1 MX
;1
H (z ) =
zo;l El (zi ) =
zo;l
Elm (zs )zi;m
l=0
l=0
m=0
(12)
Again, this representation is related to the actual
sampling rates used for ltering (Fs ), blocking (Fi )
and unblocking (Fo ) operations, as dened by (3).
Step 5: Commutator Polyphase Structure
Figure 3: Step 3 transformation of FSRC
In Fig.5 the 1-to-M input blocking and the L-to-1
unblocking circuits of Fig.4 are replaced by commutators rotating counterclockwise as appropriate
[1,2]. Furthermore, the detailed structures of the
MIMO system S(zs ), resulting from the described
twofold polyphase decomposition, is revealed. The
corresponding FSRC representation is given by
(12).
Step 4: Polyphase Decomposition of Branch Filters
The dashed blocks in Fig.3 represent complete decimators for M -fold sample rate reduction. Hence,
each of the associated branch lters is subjected
to a further polyphase decomposition into M
polyphase components with subsequent standard
application of the noble identities to polyphase decimators [1]. As a result, we obtain L polyphase decimators with identical decimator-delay chain circuits for blocking the input signal X (zi ) into L
identical vector-valued signals of length M , and one
output expander-delay chain for interleaving (unblocking) L branch signals. Eventually, the L identical input blocking circuits are replaced by one by
means of elementary signal ow graph identities.
Thus, the general block structure of Fig.4 results,
where the MIMO block represents an LTI system
with an L M transfer matrix S(zs ).
Applying the described structural optimisation to
Figure 5: Optimum polyphase realisation with one
input and one output commutator
3 Example
With L = 3, M = 5 and the canonical, causal lter
H c (z ) =
Figure 4: Block structure of FSRC
14
X
k=0
hk z ;k
(13)
we have chosen a simple FIR example to gain maximum insight. Since the lter length N = 15 is set
equal to the number of branches L M = 15 (cf.
Fig.5), each path is provided with just one non-zero
coecient by the twofold polyphase decomposition
process. From (7) and (8) follows p2 = 3 and = 9,
corresponding to the short extra delay of 9T = 3Ti .
The index mapping (6) of the rst polyphase decomposition yields
l
0 1 2
pl
0 1 3
(14)
(lM )L
0 2 1
resulting in the assignment dened by (10) in conjunction with (2) and (5)
E0 (zi ) = zi;3 H0 (zi ) = zi;3
=
7
X
k=0
e0k zi;k ;
4
X
k=0
h3k zi;k
e00 = e01 = e02 = 0
X
E1 (zi ) = zi;2 H2 (zi ) = zi;2
h3k+2 zi;k
4
=
X
6
k=0
k=0
e1k zi;k ;
E2 (zi ) = H1 (zi ) =
=
4
X
k=0
4
X
k=0
e2k zi;k
Figure 6: FSRC example: L = 3, M = 5, lter
length N = 15
the polyphase decomposition of the output decimator for rate reduction by M . Both approaches and
their features will be compared with each other in
a forthcoming extended paper.
e10 = e11 = 0
h3k+1 zi;k
References
(15)
In the second decomposition process the quantities
El (zi ), l = 0; 1; 2, are additionally decomposed into
M = 5 polyphase components each in a straightforward manner. The ultimately obtained signal
ow graph of the optimum fractional sample rate
converter (=3/5-decimator) is depicted in Fig.6.
4 Conclusion
An alternative but for the rst time systematic and
rigorous derivation of an optimum realisation of
the synchronous L=M sample rate converter, with
L; M 2 N being relatively prime, has been given.
Its merits are: i) All multiplications and additions
with zero terms are avoided, ii) all operations (multiplications, additions, delays) are performed at a
clock rate ranging both below the input and output rates of the FSRC, and iii) parallel processing
is achieved by means of one input commutator for
decimation by M , and one output commutator for
interleaving of L polyphase sequences.
Note that the decomposition procedure of the developed optimum FSRC started with an L-branch
polyphase decomposition of the input interpolator. Similarly, we could also have started with
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