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COPPER SEED AGING EFFECTS ON POST ELECTROPLATING DEFECTS
By
DANIELE GILKES
A THESIS PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF SCIENCE
UNIVERSITY OF FLORIDA
2002
Copyright 2002
by
Daniele Gilkes
ACKNOWLEDGMENTS
First, I would like to thank the staff of Florida Engineering Education Delivery
System headed by Art Zirger who offer the ability for working engineers to continue their
engineering education. Next, I would like to thank the many materials science professors,
namely Dr. David Norton, Dr. Stephen Pearton, and Dr. Cammy Abernathy, for not only
taking on the added aggravation of forever engraving their classes on to tape but also
encouraging and furthering the educational goals of working students. I am honored to
have them as committee members. In addition, I would like to thank Dr. Sailesh
Merchant, Dr. Minseok Oh, Dr. Deepak Rammapa, and Edit Braunstein at Bell
Laboratories for their constant support and guidance. They set flawless examples of great
engineers and wonderful friends.
I would also like to thank Jennifer Horton, without whom I would have gone
crazy staying on track every semester. In addition, I thank my parents and parents-in-law
for their inspiration and confidence. Last, but certainly not least, I would like to thank my
husband, Bruce Gilkes, for believing in me and always lending a helping hand.
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TABLE OF CONTENTS
page
ACKNOWLEDGMENTS ................................................................................................. iii
LIST OF TABLES............................................................................................................ vii
LIST OF FIGURES ......................................................................................................... viii
ABSTRACT....................................................................................................................... xi
CHAPTER
1 INTRODUCTION ...........................................................................................................1
2 BACKGROUND .............................................................................................................4
The Beginning................................................................................................................. 4
Semiconductor Manufacturing........................................................................................ 5
Wafer Fabrication Steps........................................................................................... 5
Layering .............................................................................................................6
Patterning ...........................................................................................................6
Doping................................................................................................................6
Heat Treatments .................................................................................................6
Example Fabrication Process ................................................................................... 7
Multilevel Metallization.................................................................................................. 8
Requirements for a Good Conductor .............................................................................. 9
Aluminum .............................................................................................................. 10
Aluminum-Silicon Alloys ...................................................................................... 10
Aluminum-Copper Alloys...................................................................................... 10
Physical vapor deposition of aluminum alloys ................................................11
Problems with aluminum alloy deposition ......................................................11
Inherent problems with aluminum alloys ........................................................13
Copper .................................................................................................................... 15
Increased performance .....................................................................................16
Decreased Electromigration.............................................................................17
Drawbacks of copper .......................................................................................17
New metallization schemes..............................................................................18
Surface preparation for copper electroplating..................................................19
Electroplating process for copper interconnects ..............................................20
Copper Electroplating Defects...................................................................................... 26
iv
Copper Surface Degradation by Oxide Growth............................................................ 28
Theory of Oxide Growth on Metals ....................................................................... 28
Oxidation Kinetics of Copper ................................................................................ 35
Copper Oxidation Phenomena ............................................................................... 37
Structure of oxygen on Cu(1 1 1) surface........................................................38
Structure of Oxygen on a Cu(1 1 0) surface ....................................................40
Structure of Oxygen on a Cu(1 0 0) surface ....................................................42
Copper Oxide Effect on Electroplating.................................................................. 42
Copper Surface Pre-treatments for Oxide Removal ..................................................... 43
Plasma Pretreatment............................................................................................... 44
Reverse Electroplating ........................................................................................... 45
Copper Sulphate Rinse........................................................................................... 46
Ammonium Biflouride with Ethanolamine Clean ................................................. 47
3 MATERIALS AND METHODS...................................................................................48
Deposition Methods ...................................................................................................... 48
Barrier and Seed Deposition Methods ................................................................... 49
Bulk Copper Deposition......................................................................................... 50
Copper Defectivity Measurements ............................................................................... 53
Defect Location...................................................................................................... 53
Scanning Electron Microscopy .............................................................................. 54
Surface Treatments ....................................................................................................... 55
Copper Oxide Reduction........................................................................................ 55
Reverse Electroplating ........................................................................................... 56
Copper Electrolyte Rinse ....................................................................................... 57
Single Wafer Clean ................................................................................................ 57
Seed Surface Characterization ...................................................................................... 58
Contact Angle Measurements ................................................................................ 58
Sheet Resistance..................................................................................................... 60
Optoacoustic Measurements .................................................................................. 61
Reflectance Spectrometry ...................................................................................... 63
Experimental Details Summary .................................................................................... 65
Copper Seed Aging ................................................................................................ 66
Copper Seed Aging Treatments ............................................................................. 66
4 EFFECTS OF COPPER SEED AGING........................................................................67
Early Indications ........................................................................................................... 67
Systematic Defect Study ........................................................................................ 67
Seed Aging Indication by Defect Increase............................................................. 71
Seed Aging Indication by Contact Resistance Increase......................................... 72
Aged Seed Layer Characterization ............................................................................... 73
Contact Angle Measurements ................................................................................ 73
Spectrometry of Aged Seed Wafers....................................................................... 74
Opto-acoustic Spectra of Aged Seed Wafers ......................................................... 76
v
Sheet Resistance Measurement .............................................................................. 79
Summary and Discussion.............................................................................................. 80
Defects after Electroplating.................................................................................... 80
Seed Surface Characterization ............................................................................... 81
5 POST–ELECTROPLATING DEFECT IMPROVEMENT BY TREATMENT OF
COPPER SEED.............................................................................................................83
Background ................................................................................................................... 83
Copper Oxide Reduction........................................................................................ 83
Reverse Electroplating ........................................................................................... 84
Copper Electrolyte Rinse ....................................................................................... 84
Single Wafer Clean Tool........................................................................................ 84
Experimental Results .................................................................................................... 84
Defect Characterization.......................................................................................... 84
Contact Angle Measurements ................................................................................ 91
Treatment ...................................................................................................................... 92
Spectrometry of Treated Aged Seed Wafers.......................................................... 92
Opto-Acoustic Spectra of Treated Aged Seed Wafers........................................... 94
Sheet Resistance..................................................................................................... 98
Discussion ..................................................................................................................... 99
6 CONCLUSION............................................................................................................102
LIST OF REFERENCES.................................................................................................106
BIOGRAPHICAL SKETCH ...........................................................................................112
vi
LIST OF TABLES
page
Table
5-1 Post-Electroplating Defect Count with Treated Aged Copper Seed Wafers..............87
5-2 Contact Angle Measurement Results for Treated Wafers ..........................................92
5-3 Thickness Results following Wafer Treatment ..........................................................98
5-4 Sheet Resistance Results following Wafer Treatment ...............................................99
vii
LIST OF FIGURES
page
Figure
2-1 Multilevel Metal Interconnect Structure.......................................................................8
2-2 Electromigration Lifetimes of AlCu versus Cu..........................................................17
2-3 Tafel Equation ............................................................................................................23
2-4 Super-Conformal Copper Fill.....................................................................................26
2-5 Photolithography Process Defects ..............................................................................27
2-6 Etch Process Defects ..................................................................................................27
2-7 Electroplating Process Defects ...................................................................................28
2-8 Partial Steps of the Oxidation Reaction. A) transport of oxygen ions or vacancies;
reaction takes place at the metal-oxide interface; B) transport of metal ions or
vacancies reaction takes place at the oxide surface ...............................................29
2-9 Solid State Structure of a Metal Covered by an Oxide Layer. A) without field; B)
with field ................................................................................................................30
2-10 Oxide growth curve and potential (V) determined by the Martin & Fromm Model 35
2-11 Sputtered Copper Film Oxidation at 50°C and 100°C. A) Cu2O thickness as a
function of time; B) Rate of oxide growth.............................................................36
2-12 STM images of clean Cu(1 1 1) and Cu(1 1 1) reacting in a pressure of O2 at 7x105
Pa at room temperature. A) Clean Cu(1 1 1) (1000 x 1000Å2 V=500 mV, I=0.03
nA); B) Recorded after 10 min in oxygen, the dashed arrows indicate the original
position of the step edge (1200 X 1200 Å2, V=700mV, I=0.07nA); C) After 20
min exposure the step edges have retreated (1200 X 1200 Å2, V=700mV,
I=0.03nA); D) 33 min; E) 39 min The small arrows indicate new ``terrace oxide''
formed in the latter stages of adsorption; F) 66 min (3000 X 3000 Å2, V=700mV,
I=0.03nA)...............................................................................................................39
2-13 Potential versus PH diagram for the Copper-Water system at 25°C........................46
3-1 HCM Source ...............................................................................................................50
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3-2 Central Plating Bath Schematic..................................................................................51
3-3 Plating Cell Geometry ................................................................................................52
3-4 Sabre Plating Tool: Front-View / Top-View..............................................................53
3-5 Contact Angle Measurement ......................................................................................59
3-6 Rame-Hart Goniometer ..............................................................................................60
3-7 Sheet Resistance Measurement Set-Up ......................................................................61
3-8 MetaPULSE System ...................................................................................................62
3-9 MetaPULSE System Operation ..................................................................................63
3-10 OptiProbe 3290 System ............................................................................................64
3-11 Spectroscope.............................................................................................................65
4-1 Common Electroplating Defects ................................................................................70
4-2 Defects Post Electroplating (Left) and Post CMP (Right) .........................................71
4-3 Swirl Defect Post Electroplating (left); Swirl Defect Post CMP (right) ....................72
4-4 Electroplating Defects as a Function of Copper Seed Delay Time ............................74
4-5 Classified Electroplating Defects as a Function of Copper Seed Delay Time ...........74
4-6 Normalized Via Resistance as a Function of Barrier Seed Aging..............................75
4-7 Contact Angle Increase with Seed Aging...................................................................76
4-8 Copper Seed Reflectance as a Function of Incident Wavelength of Light.................78
4-9 Copper Seed Reflectance as a Function of 250-350nm Wavelength Light................78
4-10 Copper Seed Reflectance as a Function of 500-550nm Wavelength Light..............79
4-11 Opto-acoustic Spectrum from Aged Seed Wafers....................................................80
4-12 Copper Seed Layer Stack .........................................................................................82
4-13 Copper Seed Sheet Resistance Over Time ...............................................................83
5-1 Experimental Set-Up ..................................................................................................86
5-2 Post-Electroplating Defect Count of Aged Copper Seed Wafers...............................87
ix
5-3 Post-Electroplating Defect Count with Treated Aged Copper Seed Wafers..............88
5-4 Post-Electroplated Wafer Defect Maps from Aged Control Wafers..........................88
5-5 Post-Electroplated Wafer Defect Maps Following Three Days of Seed Aging .........89
5-6 Post-Electroplated Wafer Defect Maps Following Nine Days of Seed Aging...........90
5-7 Post-Electroplated Wafer Defect Maps After Fourteen Days of Seed Aging ............90
5-8 Defect Examples from Treated and Control Wafers ..................................................91
5-9 Contact Angle Measurement Following Wafer Treatment ........................................92
5-10 Reflectivity of Treated Wafers with Incident Light 250-350nm Wavelength..........93
5-11 Reflectivity of Treated Wafers with Incident Light 500-550nm Wavelength..........94
5-12 Opto-Acoustic Spectra from Electrolyte Rinse Treatment.......................................95
5-13 Opto-Acoustic Spectra from Single Wafer Clean Treatment ...................................96
5-14 Opto-Acoustic Spectra from Copper Oxide Reduction Treatment ..........................96
5-15 Opto-Acoustic Spectra from Reverse Plate Treatment.............................................98
x
Abstract of Thesis Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Master of Science
COPPER SEED AGING EFFECTS ON POST ELECTROPLATING DEFECTS
By
Daniele Gilkes
December 2002
Chair: David P. Norton
Major Department: Materials Science and Engineering
The semiconductor industry has adopted copper metallization schemes for the
development of sub-180 nm devices for increased speed and improved resistance to
electromigration. The transition from aluminum copper alloys to copper has meant the
introduction of “new” processing techniques, unique to copper metallization, which
impose new defect-related challenges. Electroplating of bulk copper onto a thin layer
(100-200 nm) of physical or chemical vapor deposited (PVD/CVD) copper has emerged
as a cost-effective methodology used for forming copper interconnects. Although
electroplating has long been employed in traditional metallurgical applications, the use of
electrolytic deposition for feature fill of semiconductor devices is new and challenges
such as unstable defect counts must be overcome to make the copper electroplating
process robust.
Voids, observed after copper electroplating, have been identified as defects,
which proliferate with increased delay time between PVD copper seed deposition and
xi
subsequent bulk copper deposition by electroplating; the delay time is termed “seed
aging.” It is postulated that seed aging causes a lack of adequate wetting of the copper
seed surface by the electrolyte, inducing voids. Typically, in a manufacturing
environment, a batch or several batches of control wafers are fabricated at one time and
stored for monitoring subsequent processing steps; the copper seed ages during the
storage time. There may be reasons for additional tool problems, which could prevent the
immediate electroplating of wafers and consequently detrimental storage time. In
addition to causing serious device operational effects, defects caused by the aging process
could be confounded with actual electroplating process-related defects.
Four surface treatments just prior to electroplating were explored to promote
wetting, thereby mitigating post-electroplating voids. The first treatment included a
reduction of the copper oxide film (formed by exposure to clean room ambient) by
hydrogen using a commercially available sputtering tool. Other treatments included
reverse plating of the copper surface, rinsing the seed wafer surface with electrolyte, and
cleaning the surface with ammonium bifluoride and ethanolamine mixture. Each
treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to
electroplating. Results show a significant decrease in post-electroplating defects with all
four treatments. The reduction of copper oxide by hydrogen exhibited the most marked
results. An increase in surface wetting is shown by a decrease in contact angle
measurements and an increase in film reflectivity for treated versus untreated copper
wafers. This study shows that although the copper surface exhibits strong aging effects
over a short period of time, utilizing proper surface treatments can eliminate these effects
and decrease post-electroplating copper voids.
xii
CHAPTER 1
INTRODUCTION
The history of the deposition of precious metals can be traced to Luigi V.
Brugnatelli, Italian chemist and university professor, who first performed his
electrodeposition of gold around 1800. Brugnatelli was a friend of Allisandro Volta, who
had just discovered the chemical principles that would later lead to the development of
"voltaic" electrical batteries. Volta's first practical demonstration of this was called a
"Voltaic Pile." As a result, Brugnatelli's early work using voltaic electricity enabled him
to experiment with various metallic-plating solutions. By 1805, he had refined his process
enough to plate a fine layer of gold over large silver metals. However, an insult from
Napoleon Bonaparte caused Brugnatelli to confine the publication of his works to his
own journal, causing the loss of this information for almost forty years.1
By 1839, scientists in Great Britain and Russia had independently devised metal
deposition processes similar to Brugnatelli's for the copper electroplating of printing
press plates. John Wright, from Birmingham, England, found that potassium cyanide was
a suitable electrolyte for gold and silver electroplating. His work, combined with that of
the Elkington cousins and other developments by Barratt, resulted in the issue of several
patents in 1840. These discoveries and patents are the foundation of modern gold and
silver plating. This alliance, and its discoveries, was almost certainly precipitated by the
invention of copper electroplating (referred to as electroforming and electrotyping in the
literature) developed in the latter part of 1838 and early 1839, leading to the adaptation of
galvanic current for the deposition of gold and silver.
1
2
As knowledge of electrochemistry broadened and its relationship to the
electroplating process became more widely known, other types of non-decorative metal
plating would soon be developed. Electroplating processes for bright nickel, brass, tin,
and zinc were adapted for commercial purposes by the 1850's. Many of these types of
platings were utilized for specific manufacturing and engineering applications. As the
industrial age and financial capital expanded from Great Britain to the rest of the world,
electroplating processes would find more use in the manufacturing of goods and
services.1
Despite the expansion of electroplating processes to other industries, no
significant scientific developments were discovered until the emergence of the electronics
industry in the mid-1940’s. The late 1940’s witnessed the rediscovery of heavy gold
plating for electronic components. By the mid-1950's, the utilization of new and safer
plating baths based on acid formulas began to displace some of the traditional cyanide
based formulas in large-scale commercial use. The 1970's led to numerous regulatory
laws for waste water emissions and disposal that set the direction for the electroplating
industry for the next 30 years. Improvements in chemical formulas and technical
hardware allowed for the rapid and continuous plating of wire, metal strips, complex
metal shapes, and semiconductors.
In 1997, the semiconductor industry questioned whether or not it would use
copper as a metal interconnect material for the integrated circuit. The question changed
from whether or not to use copper to how to deposit and process it. The industry soon
concluded that copper would be used and electroplating would be used as the deposition
method.2,3 However, since the application of copper electroplating for copper
3
interconnect metallization is new, several processing issues remain to be resolved.
Although the electroplating process offers compelling cost and throughput advantages for
semiconductor companies, challenges such as unstable defect counts must be overcome
to make the copper electroplating process robust.4 The advancement of the electronics
industry continues to drive improvements worldwide in the electroplating industry.
CHAPTER 2
BACKGROUND
The Beginning
From the early 1920’s through the 1950’s vacuum tubes were the primary
components of electronic devices. Vacuum tubes were bulky and had a short lifecycle.
These problems led to the development of the transistor in 1947 when three Bell
Laboratory scientists, John Bardeen, Walter Brattin, and William Shockley, demonstrated
an electrical amplifier made from a semiconductor material, germanium. The
announcement of the first solid-state transistor marked the beginning of the solid-state
electronics age and the microelectronics industry. By the early 1950s, the semiconductor
industry was supplying devices for transistor radios and transistor based computers. In
the early stages, the semiconductor industry produced discrete devices, one device per
chip, such as capacitors, resistors, and diodes. However, in 1959, Jack Kilbey, an
engineer at Texas Instruments, formed a complete circuit on a single piece of germanium.
This invention was the integrated circuit. Next, Robert Noyce applied the technique of
using a layer of evaporated aluminum on silicon which was patterned to serve as a wiring
device to wire several individual devices together. This was different from Kilbey, who
employed an actual wire. Kilbey and Noyce shared the patent for the integrated circuit.5
In the 1960’s, new semiconductor chip manufacturers entered the market while
the early companies solidified their position. In the 1970’s, semiconductor manufacturing
changed from processing small batches to large-scale manufacturing. At the beginning of
the decade, the integrated circuit was at a medium scale-integration level, 50-5000
4
5
components per chip. The processing moved from operator control to automatic control
to increase wafer throughput and uniformity. From the 1980’s onward, the industry has
been concentrated on improvements in process control, automation, cost control, and
process characterization. The technical driving factors have been speed, feature size
reduction, wafer diameter increases, and yield improvement.
Semiconductor Manufacturing
Semiconductor manufacturing requires four stages. In the first stage, material
preparation, the raw semiconducting materials are mined to meet the needed
specifications. Next, by a process called crystal growth, the raw material is formed into
wafers. Wafers are thin slices of semiconducting material. During the third stage, wafer
fabrication, the devices or actual integrated circuits are formed on the wafer.6 The
integrated circuit takes up a certain amount of area on the wafer called the die or chip.
After wafer fabrication, the chips must be electrically tested to determine if they meet the
supplier’s specifications. Chips that do not meet the specifications will be marked in
some manner and will count against the yield of that wafer. Lastly, packaging is the step
in which the wafer is separated into individual die and placed in protective packaging.
The chip will be connected by durable leads, which will eventually connect the chip to
the printed circuit board.
Wafer Fabrication Steps
Wafer fabrication facilities around the world produce billions of chips with
thousands of functions, but the variation in processing among companies can seem
infinite. There are four main operations performed on a wafer during the fabrication
process: layering, patterning, doping, and heat treatments.7
6
Layering
Layering is the operation of adding thin layers to the wafer surface. These layers
can be insulators, conductors or semiconductors and are either grown or deposited by
various techniques. Oxidation is an example of a technique where a layer is grown on the
surface of a wafer. Deposition techniques include, chemical vapor deposition,
evaporation, sputtering, and electroplating.
Patterning
Patterning is a series of steps that results in the removal of selected portions of the
added surface layers. After removal, either a hole or an island remains from the original
material. The patterning operation creates the pieces in the proper location of the surface,
which define the devices that make up a circuit. The patterning process is known by
several names such as photomasking, photolithography, or microlithography.
Doping
Doping is the process that puts a specified amount of dopants in the wafer surface
in the areas that were opened by the patterning process. Two of the techniques utilized for
this purpose are diffusion and ion implantation. Thermal diffusion is a process where the
wafer is exposed to vapors of a dopant, which are created when a wafer is heated to high
temperatures (1000°C). On the other hand, ion implantation is a process where ionized
dopant atoms are accelerated and bombard the wafer surface. The doping operation forms
the p- or n- junction that is a necessity for the formation of transistors, capacitors, and
resistors.
Heat Treatments
In a heat treatment process, the wafer is simply heated or cooled to change the
material properties and obtain a desired effect. After the metal stripes on a wafer are
7
formed a heat treatment is applied to alloy the metal to the wafer surface. This promotes
electrical conduction. Heat treatments are also used as a repair mechanism after ion
implantation. As the dopant atoms bombard the wafer surface, they cause a disruption to
the crystal lattice. Heat treatments will mend the crystal lattice damage.
Example Fabrication Process
The construction of a circuit involves putting the above steps together to form the
wafer fabrication process. The process starts with a bare silicon wafer. The process
proceeds with oxidation of the wafer surface to both protect the wafer and also serve as a
doping layer. Next, the patterning process is used to create islands or holes in the oxide
layer which will form the source and drain areas of the transistor. The wafer is then
doped with p- or n- type dopants. Then the field oxide between the source and drain are
removed. The exposed silicon in the gate region is re-oxidized with a thin layer known as
the gate oxide. An oxide layer is also formed on the source and drain holes. In the
subsequent patterning step, two holes are formed on the source and drain oxide layer.
Next, a conductive metal layer is deposited on the wafer surface which is then patterned
such that metal remains only in the areas necessary to connect components which make
up the circuit. The wafer will then go to a heat treatment step. In this step, the metal will
be alloyed to the source and drain region to promote electrical contact. The layering and
patterning steps may be completed several times to complete the device design and
connect the components, which make up the circuit. The final layer of the device will be
a passivation layer, used as protection. A portion of this layer will be removed during a
patterning step to expose the metal that will be used as a terminal to connect the device.7
8
Multilevel Metallization
The most common use of metal films in semiconductor technology is for wiring
integrated circuits containing transistors, resistors, and memory regions, which connect to
form a circuit. Metal interconnects form the highway distributing power to the active
elements in a circuit. They also provide a connection to the chip from the outside world.
Metallization is the process which describes the materials and methods for “wiring” the
components of a device together.
In the earlier stages of semiconductor development, metallization involved merely
a single step process. Small holes, called contacts, were etched through the surface layers
to the circuit component. Next, vacuum evaporation, sputtering, or CVD techniques
would be used to deposit a conducting metal layer. The unnecessary part of this layer
would be removed leaving a metal connection between the components, called an
interconnect.8
As semiconductor processing has advanced, integrated circuit density has
increased causing interconnect packing densities to increase. This has decreased the
surface area available for wiring. Therefore, several layers of interconnect material are
required for efficient routing, resulting in multilevel metallization structures that are
separated by interlevel dielectrics, see figure 2-1.
METAL 2
W2
METAL 1
D2
Figure 2-1. Multilevel Metal Interconnect Structure
9
At each interconnect level the components are partially wired. A dielectric layer,
which is patterned and etched with holes called vias or plugs, provides the linkage
between one metal level and the next. The unnecessary portions of the metal layer is
removed, leaving metal lines or interconnects which create contact to the first metal
layer.
Metal layers serve several functions in the integrated circuit. They provide contact
to active elements, connect devices together to form the integrated circuit, distribute
power, and connect the package to the outside world.9
Requirements for a Good Conductor
A metal system must meet certain criteria to be considered as a good conductor
for use as a metal interconnect material. As discussed above, the interconnect will be the
highway which distributes power to the components in a device; therefore, the metal
interconnect stack must have good current carrying capability (current density). The
resistivity of the interconnect must be very low to ensure that there is no loss in power in
the circuit. There must be good electrical contact with the wafer material. The materials
must adhere together even through thermal cycling to prevent voids, peeling of material
layers, or cracking. The materials must be corrosion resistant, have a uniform grain
structure, and offer long-term stability. The materials must be able to be processed in a
high throughput, low cost manner with reproducible across wafer, between wafer, and
with-in wafer properties. When used as a contact, via or runner the metal materials must
have a high electromigration resistance. The deposited layers must be uniform with a low
defect density.10 Several metal conductors meet these criteria including: aluminum,
10
aluminum-silicon alloys, aluminum-copper alloys, and copper. The main conductor used
in a multilevel metal stack is aluminum, aluminum alloys, or copper.
Aluminum
In the early stages of semiconductor development, the primary metallization
material was aluminum. Aluminum was the chosen metal even though it was less
conductive than gold or copper. Gold and copper suffered from a high contact resistance
with silicon. In addition, if copper diffuses to the active regions of the device it can
render the device useless. Gold was too soft, requiring a top layer of molybdenum.
Aluminum has a low resistivity (2.7 µΩ cm)8, good current carrying density, good
adhesion to silicon dioxide, low contact resistance with silicon, and is relatively easy to
pattern, making it a good choice.
Aluminum-Silicon Alloys
Creating an ohmic type contact, where voltage-current characteristics behave
according to ohm’s law, required a heat treatment of the aluminum-silicon interface.
However, at 450°C aluminum and silicon dissolve into one another and a eutectic forms.
The alloy formation will melt into the wafer destroying any shallow junctions. To combat
this problem either a barrier layer is employed between the aluminum and silicon11 or the
aluminum is alloyed with 1 to 2 percent silicon.12 In the latter method, during contact
heating, the aluminum will alloy more with the silicon in the alloy than the silicon in the
wafer.
Aluminum-Copper Alloys
A second problem with using aluminum is susceptibility to electromigration. The
current sets up an electric field, which decreases from the input side to the output side,
and occurs in aluminum wire, which is carrying high currents over long distances. The
11
heat generated by this flowing current also sets up a thermal gradient along the lead. The
aluminum becomes mobile and moves along the gradient causing the wire to thin and in
worse cases to separate completely causing device failure. To counteract
electromigration, an alloy of aluminum is used which is comprised of 0.5 to 4 percent
copper13 or an alloy of 0.1 to 0.5 percent titanium. The drawbacks of alloying aluminum
with other metals are increased complexity for equipment and processes, different etch
rates, and an increase in resistivity.10
Physical vapor deposition of aluminum alloys
Physical vapor deposition in the semiconductor industry has been adapted from
Sir William Robert Grove who developed it in 185214. Physical vapor deposition occurs
in a vacuum chamber containing a target made of the desired deposition material, in this
case aluminum alloy. The target is electrically grounded. An inert gas is introduced into
the chamber and ionized to a positive charge. The positively charged atoms are attracted
to the grounded target and accelerated toward it. The positively charged gas ions strike a
target (cathode). The momentum of the charged inert gas ions transfers to the aluminum
atoms and molecules, which make up the target, causing them to dislodge from the
source, forming a vapor. This process is also called sputtering. The sputtered atoms
scatter throughout the chamber and are transported through a low-pressure region to the
wafer where the species deposit (condense) to form a thin film layer of aluminum on the
surface of the wafer.15
Problems with aluminum alloy deposition
For metallization of very large scale integration (VLSI) circuits, aluminum
suffers from major limitations that are due both to the properties of the metal and to the
deposition techniques. Aluminum is difficult to deposit in high aspect ratio vias using
12
physical vapor deposition. Historically, openings (vias or plugs) were too large to worry
about step coverage. As devices have decreased to less than 0.25 µm, step coverage has
become an issue. The sputtered film creates a thicker layer at the top of the via as
compared to the via bottom.16 Several attempts were made to address this problem
including tapering the edges of the openings as well as fundamental changes to the
deposition process.
Via tapering. A tapered via allows improved coverage when a sputtering process
is employed. Although this offers an improvement for step-coverage, the top diameter is
constrained by design rules (i.e., interconnect density) so the bottom area of the via must
be reduced. For a 0.5-µm via with an aspect ratio of 2:1, an 85 degree slope increases the
via resistance by a factor of ~2.0.9 Thus the via photo and etch processes have to be
optimized to provide the required via shape with tight control of via slope between 86-88
degrees. In addition, designers favor the use of straight-walled openings to increase
density, thus favoring reduced design rules.
PVD process variations. Coverage at the bottom of vias has been improved by
collimating obliquely incident sputtered atoms.17 The collimator is a physical filter which
blocks sputtered atoms which possess an incident angle greater than the arc-cotangent of
the collimator aspect ratio. Those atoms with angles less than this amount are allowed to
pass through and deposit on the wafer, though an angle-dependent fraction are still
blocked by the collimator. Atoms with low incident angles are able to get down into high
aspect ratio features much more effectively than those with higher angles. In addition to
collimation of the incident ions, deposition has been optimized by increasing the surface
mobility of atoms that enter the feature opening to allow re-arrangement and formation of
13
a continuous layer. Increasing the substrate temperature, applying bias to the wafer to
direct ions to bottom of vias, and using multi-step deposition techniques have helped to
improve step coverage.18
Inherent problems with aluminum alloys
For the development of ultra-large scale integration (ULSI), the electrical
resistivities of aluminum and its alloys are not low enough. In addition, they suffer from
an important reliability problem, electromigration, as discussed previously. As the
minimum geometry is scaled down to less than 0.25-µm, aluminum and its alloys will be
replaced by other interconnect materials.19
RC Delay. The slowing of circuit signals comes from the combination of the
metal resistance and capacitance and is called the RC time constant. As the basic device
dimension decreases, the carrier transient time across the length of the channel also
decreases, creating a faster device. However, the signal propagation to and from the
device must occur through the interconnections. These charge carriers are also
capacitively coupled to insulating dielectrics. Digital switching speed is proportional to
the capacitance on the node. As technologies have improved, an increasingly large part of
the capacitance is due to the interconnect wire. This can be either capacitance between
the substrate and metal or capacitance between the wires. As the wiring density increases,
the wires get narrower. This results in the so-called RC delay. For a circuit, the RC delay
is defined in terms of the circuit response, which is given by:
Vout = 1 − e − ( t / RC )
(1)
where Vout is output voltage of the circuit, t is the time, R is the total resistance of
circuit, and C is the total capacitance of circuit.
14
A rough estimate of the RC time constant can be determined by modeling it as
one side of a parallel plate capacitor as follows:20
C=
LWk ox ε o
t ox
R = ρ met
L
Wt met
(2)
(3)
Therefore,
RC = ρ met
ε ox L2
t met t ox
(4)
where ρ met , tmet, L, ε ox , and tox, respectively, are the resistivity of the metal, thickness of
the metal, length of interconnection, interlayer dielectric permittivity, and dielectric
thickness. This equation highlights the importance of the length of the interconnect. The
delay time increases with the square of the length of the interconnect. Therefore as the
thickness of the line widths decreases and the length of the interconnection increases the
circuit will suffer from an increased delay time. The resistivity of the metal becomes an
increasingly important part of this equation.
Electromigration. Electromigration is the movement of conducting atoms as a
result of momentum transfer from current carrying electrons.21 Electromigration occurs
when the conductor is subjected to high current densities where atomic diffusion is high,
leading to a mass transport association with atomic flux divergence. If a non-zero
diveregence exists anywhere along a line, metal atoms will be accumulated or depleted.
Upon depletion, open circuits form. Upon accumulation, hillocks tend to form. The
enhanced and directional mobility of atoms are caused by (1) the direction influence of
the electric field on the ionized atoms and (2) the collision of electrons with atoms,
15
leading to a momentum transfer (called electron-wind effect) and atom movement. For
aluminum metallization systems, this forms a serious problem; a circuit that works well
initially may fail in the field after a short lifetime. A phenomenological perspective on
electromigration is given by Black’s equation as follows.22
−n
MTF = AJ e
−
Ea
kT
(5)
where MTF is the median time to failure, J is the current density, n is the fitting
parameter, Ea is the activation energy, and A is a constant. Ea depends on the diffusivity
of the metal atom. At high temperatures (above 350°C), the activation energy for
aluminum closely matches the self diffusivity of aluminum. At lower temperatures,
where integrated circuits operate, the activation energy for electromigration is smaller,
and grain boundary diffusion along the facets of the aluminum crystal dominates.
Addition of copper atoms greatly reduces the grain boundary diffusion thereby increasing
the activation energy for electromigration.23
Copper
Signal delay, due to the electrical resistance of interconnects and the
interdielectric capacitance, is one of the most important issues concerning the fabrication
of future generation ultra large scale integration devices. The signal delay can be reduced
by using narrow-pitched interconnects, thereby reducing the chip size, which is related to
the maximum interconnect length. Current density will be higher in the narrow-pitched
interconnects, therefore, a metal with a high electromigration resistance is needed.
Copper has lower electrical resistivity and higher electromigration resistance than
aluminum and its alloys.24 The problems with aluminum and its deposition, as discussed
above, have led to the transition to copper as the main interconnect material in integrated
16
circuits. The use of copper would allow thinner conductors at the same resistance. This
produces a lower line-to-line capacitance and less cross talk induced noise.
In addition to the benefits of increased speed, copper has improved
electromigration performance as compared to aluminum, allowing a higher-current
carrying capability. Copper can fill plugs with good step coverage and can be deposited
at lower temperatures than aluminum. Copper can be deposited by chemical vapor
deposition (CVD), sputtering, electroless plating, and electrolytic plating.
In 1997, IBM announced the first implementation of copper interconnect
technology.2 Subsequently other companies proceeded in the direction of copper
metallization. The initial technology introduced by IBM combined six copper wiring
levels at ultra large scaled integration densities. The transition from aluminum to copper
has been fueled by the advantages of lower resistance, higher current density and
increased scalability.
Increased performance
The varying needs of wiring from low capacitance to low RC delay to low
resistance suggest a hierarchical wiring scheme.24 At the lower wire levels pitch and
thickness are minimized to minimize capacitance and maximize density. At the upper
levels, the wires are scaled uniformly to maintain a constant capacitance and reduce
resistance.
It has been established that when employing copper interconnects, the bulk
resistivity for copper metal of 1.7µΩ*cm20 can be obtained. This is far different from the
resistivity values of the aluminum alloys. Alloying aluminum along with alloy reacted
cladding layers is much more highly resistive then the three sided refractory liner used
17
with unalloyed copper. As an example, when comparing the Ti/Al(Cu)/Ti/TiN lines
previously used, there is a 45% reduction in resistivity when using copper.25
Decreased Electromigration
The overall reliability of the metallization structure must be tested under
accelerated stress conditions by holding the wafer at high temperatures or high current
densities. Both the intrinsic material and the extrinsic completed chip must be subjected
to a wide range of testing. For intrinsic wire reliability, proper electromigration was
confirmed to be orders of magnitude better than that of the previously used aluminum
stack. Figure 2-2 shows the electromigration data for metal 1 lines on tungsten studs at
295° C with a current density stress of 2.5 MA/cm2. Therefore, copper metallization can
support a much higher current density and boasts the extension of copper wiring to future
pitches and higher performance.2
Figure 2-2. Electromigration Lifetimes of AlCu versus Cu2
Drawbacks of copper
The early drawbacks for copper were etching problems and vulnerability to
scratching and corrosion. In addition, fast diffusion of copper into the underlying
substrate and formation of deep level recombination centers is a major disadvantage of
copper metallization. To eliminate the copper diffusion into the substrate, a layer of
18
diffusion barrier material,26 which has less grain boundaries, no reaction with copper,
good adhesion to Si, SiO2, and electrical stability in high temperature is needed. Because
copper surfaces are highly electrochemically active and do not form a natural protective
layer, so they corrode and oxidize easily. Copper reacts with oxidizing agents, silicon,
silicides, and other metals commonly used for ultra large-scale integrated circuit
metallization and packaging at relatively low temperatures.
Several different fabrication techniques needed to be employed in order to
accommodate copper into the metallization scheme and mitigate the drawbacks, as
discussed above. To accomplish this meant the development of an electroplating process
to construct the copper network,27 a dual damascene metallization scheme,28 a chemical
mechanical polishing technique, and an effective copper diffusion barrier.26
A typical copper metallization process consists of:28 (a) a physical vapor
deposition (PVD) barrier layer deposited on a patterned dielectric stack having submicron features; (b) a PVD copper seed layer deposited on the barrier layer; (c)
electroplated copper fill on the seed layer by electroplating method; (d) chemical–
mechanical polishing to remove the overfill of copper and top barrier layer.
Electrochemical deposition (ECD) in the copper metallization process has been
implemented in deep sub-micron Cu interconnect of CMOS devices. This is because
electrochemical plating of copper has the several advantages of lower cost, lower
processing temperature and better ability to fill vias and trenches.
New metallization schemes
The dual-damascene process is employed to fabricate the multilevel metal copper
interconnects. The dual-damascene process is used to inlay metal into etched dielectric
material to form copper interconnect wires. The damascene process was developed when
19
developing a copper etch process failed.29 The dual damascene process has required
changes in almost every process area, offering an entirely new look at conventional
processing techniques.
The damascene process consists of etching a 4000-5000Å trench in a dielectric
material. The term “dual damascene” refers to the formation of a second channel, a via
5000-7000 Å deep within the trench. Following the creation of the trench and via, a
tantalum or tantalum nitride layer is deposited to prevent copper from diffusing into the
underlying dielectric. The deposition of the thin barrier layer or barrier bilayers is
followed by the PVD or CVD deposition of a copper seed layer, which is a prerequisite
for the subsequent bulk copper deposition by electroplating. The excess copper is then
removed by chemical mechanical polishing to form a planar surface.
Surface preparation for copper electroplating
Successful integration of electroplated copper damascene structures requires two
critical metallization steps. First, it requires a barrier layer30-31 since copper diffuses
readily into oxides and low-k dielectrics, causing line-to-line leakage, and it can react
with silicon at temperatures below 200 Celsius. The barrier layer must prevent copper
diffusion, exhibit low film resistivity, and have good adhesion to both dielectrics and
copper. The barrier layer must be conformal and continuous to fully encapsulate the Cu
lines with as thin a layer as possible. Due to the higher resistivity of the barrier material,
its thickness should be minimized to allow for Cu to occupy the maximum crosssectional area. Ta and TaN are materials32 are used as diffusion barriers for copper. The
ideal barrier layer should have a dense amorphous microstructure and a smooth surface
morphology free of micro-defects.
20
Following the barrier layer, a thin, continuous copper seed layer promotes
adhesion and facilitates the subsequent growth of the bulk copper by electroplating. The
seed layer provides the conduction path for current along the contours of the patterned
dual damascene structure, serving as a nucleation layer. The seed layer should be thin,
smooth, and continuous to ensure void-free fill. In addition, the Cu seed layer should be
highly pure to maintain the effective resistivity of the filled copper interconnect
structure.33
Electroplating process for copper interconnects
One of the more interesting points about employing copper for interconnect
technologies is the high conductivity of copper. This meant the possibility of using an
electrochemical process as the deposition technique. Electrodeposition of metals is
performed by immersing a conductive surface in a solution containing ions of the metal
to be deposited. The surface is electrically connected to an external power supply, and
current is passed through the surface into the solution.34
Consider a metal M, immersed in an aqueous solution containing ions of the
metal, M+. An exchange of ions will occur between the ions that make up the metal and
the ions in solution. One reaction may occur faster than the other. For instance, if more
M2+ ions leave the crystal lattice of the metal than enter, the metal will become negatively
charged. In response to the negative charge on the metal, ions within the aqueous solution
will begin to rearrange. The negative charge on the metal will attract the positively
charged ions present in the solution. The solution near the interface of the metal will
begin to acquire a slightly positive charge. As the positive charge is induced it will begin
to slow down the flux of ions leaving the metal as a slight repulsive force is built up. This
slight repulsion will help to slow down the rate of ions leaving the crystal lattice and
21
encourage ions in the solution to enter the crystal lattice. After a certain period of time,
the number of electrons that enter the crystal lattice will be equal to the number of
electrons which leave, creating a dynamic equilibrium as follows:
+
M x + xe − → M
(6)
The left to right reaction consumes electrons and is called reduction. When the reaction
occurs from the right to left side, it is termed oxidation.35
When current flows through two nodes, which are immersed in a conductive
solution, then the dynamic equilibrium is interrupted and a potential is created. In this
event, the difference between the equilibrium potential (when no current is applied) and
the potential when current is applied is called the overpotential and is described by the
following equation, where E(I) is the potential of the copper cathode:
η = E(I ) − E
(7)
When the overpotential value is large and negative then the current density, i, will
increase exponentially with overpotential as follows:
i = −io e −αzfη
(8)
For large positive values of overpotential, expresses the current density as follows:
i = −io e − (1−α ) zfη
(9)
where io, is the exchange current density and α, is the transfer coefficient and f is a
constant. It follows from the two preceding equations that if the overpotential is zero, the
electrode is in equilibrium; there is a constant exchange of electrons across the interface.
However, when the electrode potential is increased the current density is largely
22
influenced. After taking the logarithm of equations 8 and 9 and solving for the
overpotential the resulting equation, known as the Tafel equation, emerges:35
η = a ± b log i
(10)
The above equations are valid when the charge transfer is the rate-determining
step. At some point the reaction is limited by mass transport of the metal ions in the
solution. A more general form of the relationship between the overpotential and the
current density is shown in figure 2-3 below. As potential continues to increase, mass
transfer effects become predominant, and the potential reaches a limiting current plateau.
At high potentials, where the reaction is limited by metal ion transport, the concentration
of ions in the bulk of the solution will be different than at a certain distance γ from the
electrode surface. In order for the electrodeposition to take place, ions in the bulk (x > γ)
must penetrate through the distance γ to the interphase. Species in the bulk no longer
reach the interface at a rate sufficient to sustain the rate of reaction.35 As a general rule,
plating processes are operated at currents no greater than 30-50% of the limiting current
in order to avoid undesirable deposit (film) characteristics.
To ensure that the rate of mass transfer of electroactive species to the interface is
large compared to the reaction rate and uniform across the wafer surface, the rates of
migration diffusion and convection must be understood and controlled. Convection is the
most important mode of mass transfer and can vary from stagnant to laminar or turbulent
flow. It includes impinging flow caused by solution pumping, flows that are due to
substrate movement and flows resulting from density variations.
23
Figure 2-3. Tafel Equation10
Electroplating can be carried out using a constant current, a constant voltage, or
variable waveforms of current or voltage. Using a constant current, accurate control of
the mass of deposited metal is most easily obtained. Plating at a constant voltage and
using variable waveforms requires more complex equipment and control but can be
useful in tailoring specific thickness distributions and film properties.
In the specific case of electrodeposition of copper onto wafer, the wafer is first
coated with a thin conductive layer of copper (seed layer). The thin layer of copper is on
the order of 1000-2000Å and is usually deposited by chemical (CVD) or physical (PVD)
vapor depostion.33 Following the seed layer deposition, the conductive copper surface is
contacted by electrodes along the outer perimeter of the wafer. The electrodes form an
electrical contact with the seed layer, and current is passed to the wafer. The uncontacted
portion of the wafer is then immersed in a solution containing cupric ions, while the
wafer to electrode contact is protected by a seal as seen in figure 2-4. The wafer,
electrically connected so that metal ions are reduced to metal atoms, is referred to as the
cathode.
24
Another electrically active surface, known as the anode, is present in the
conductive solution to complete the electrical circuit. At the anode, an oxidation reaction
occurs that balances the current flow at the cathode, thus maintaining electrical neutrality
in the solution. In the case of copper plating, all cupric ions removed from solution at the
wafer cathode are replaced by dissolution from a solid copper anode.27 In the absence of
any secondary reaction, the current delivered to a conductive surface during
electroplating is directly proportional to the quantity of metal deposited (Faraday's law of
electrolysis). Faraday’s law states the following:36
w = ZQ
(11)
where w is the mass of the deposited copper, Z is the electrochemical equivalent and Q is
the electric charge. Q is the product of time and current in amperes therefore equation 11
becomes
w = ZIt
(12)
Using this relationship, the mass deposited can be readily controlled through variations of
plating current and time. The thickness, h, can be determined from Faradays law as
follows where V is the volume of the deposit and a is the surface area of the deposit:36
h=
V
w ZQ ZIt
=
=
=
a ad ad
ad
(13)
Electroplating chemistry
The grain size, surface roughness, and feature fill characteristics of electroplated
copper films are highly dependent on the chemistry of the electrolyte used for plating. To
fill high aspect ratio vias and trenches a superconformal or bottom-up growth method is
needed.37 In particular, a plating bath should be used to introduce a diffusion-limited
leveler, resulting in a higher copper deposition rate at the bottom of the features than on
25
the sidewalls. To obtain this type of feature fill two types of additives, accelerator and
suppressor (or leveling agent), are added to the plating bath, which consists of sulfuric
acid, copper sulfate, and chloride ions. The accelerator, commonly called a brightener in
most of the literature, enhances deposition of copper on the bottom of vias. It reduces the
surface tension of the electrolyte, making it easier to transport into deep gaps. Typically
the accelerator is 2-mercaptopyridine (2-MP) or 3-mercapto-1-propanesulfonate. The
suppressor, is a larger organic molecule, and is often described as a carrier, which inhibits
copper deposition on the open area outside of the via. Suppressors for copper growth
inhibition are polyethylene glycol (PEG), chloride ions, and bis 3-sulfopropyl disulfide.
The electrolyte additive composition is tailored to provide lower surface tension,
sufficient activation overpotential, and selective inhibition gradient in the features.38-39
If only an accelerating agent is used in the plating bath, a depletion of Cu2+ ions
will eventually occur within the damascene structure.40-41 The slow replenishment rate of
Cu2+ ions inside the trench will result in a slower deposition rate inside the trench.
However, the addition of small amounts of suppressor (25ml/L), displaces the copper that
would otherwise be absorbed on the outer edges of the trench. The suppressor will
adsorb at the metal electrolyte interface and reduce the active metal area thereby
promoting the conservation of copper metal ions. Since the suppressor is dilute in
concentration (10-3 to 10-6 mol/L) the adsorption process is considered to be diffusion
limited. The suppressor is absorbed and desorbed via physisorption or chemisorption
reactions at the Cu seed/electrolyte interface, either forming a copper complex or
undergoing reductive desorption during metal deposition. The geometry of the via or
trench as compared to the large size of the organic suppressor molecule prevents it from
26
entering the trench or via and suppressing the deposition. This results in a concentration
gradient of suppressor inside the trenches with the concentration at the top of the trench
being greater than at the bottom of the trench. The concentration gradients result in
different growth rates at different nucleation sites inside the trench, causing copper to
deposit more rapidly at the bottom of the trenches than at the opening. This explanation
as well as others42-44 describes the “bottom-up” superconformal electroplating process,
shown in figure 2-4, that is needed for void-free fill.
Figure 2-4. Super-Conformal Copper Fill2
Copper Electroplating Defects
The introduction of copper as the interconnect material, and the processing
changes that follow, introduce an entirely new set of defects.4,45-48 After chemical
mechanical polishing the overfill of the bulk electroplated copper, many yield-limiting
defects are often noticed.46 Oftentimes, it appears that the copper electroplating process is
the culprit for the defect problems.4 However, a systematic study of the origin of the
chemical mechanical polishing defect reveals that defects may be masked and altered at
27
various processing steps.47 For example, figure 2-5 shows two photolithography related
defects. A photoresist bubble from improperly dispensed material causes the top defect
whereas the bottom picture is a particle introduced during the etch process. Figure 2-6
shows defects that were introduced following post etch and cleaning. From the post
chemical mechanical polishing picture alone, the defects could easily be mistaken for
defects caused by the electroplating process since the actual particle/contaminant would
have been removed during chemical mechanical polishing.47
Post Etch
Post CMP
Figure 2-5. Photolithography Process Defects47
Post Etch
Post B/S
Post CMP
Al2O3
Particle
Carbon
Compound
Figure 2-6. Etch Process Defects47
Two major defects have been linked directly to the copper electroplating process
as seen in figure 2-7. The first defect is termed the “embedded defect.” The defect is fully
comprised of copper and is entirely removed by the chemical mechanical polishing step.
28
The second defect however encompasses many copper lines, leaving them void of
copper. Several sources4,47 have identified this defect as being linked to electroplating
due to a lack of wetting of the surface by the electrolyte. An increase in defect count with
an increase in delay time between copper seed deposition and electroplating has been
noted and thought to be due to the wafer wetting issue.
Post EP
Post CMP
Figure 2-7. Electroplating Process Defects47
Copper Surface Degradation by Oxide Growth
An obstacle, which has poised itself in the way of the forging Cu technology, is
its oxidation rate at low temperatures. Unlike aluminum which forms a thin and dense
layer of oxide to stop further oxidation, copper oxides are believed to be less protective
and oxidation goes on at a significant rate, leading to serious degradation of the metal
interconnect.49 The formation of oxide on the copper surface will electrically and
mechanically degrade device performance, increasing sheet resistance and changing its
optical properties.49-50 Potential reliability problems will result from the oxidation of the
Cu surface.
Theory of Oxide Growth on Metals
Cabrera and Mott51 offer one of the first explanations of the metal oxidation
phenomena. They introduced the concept of a contact potential between metal and
29
adsorbed oxygen. Since the distance between the metal phase and the adsorbed oxygen
species is only a few nm, the electric field is very high although the potential is only on
the order of 0.5 V. Ion passage across the oxide film occurs due to the presence of the
strong electric field, moving ions through the oxide. The oxygen or metal atoms migrate
as charged defects through the oxide lattice. The potential enhances the transport of the
defects and, thus, a detectible amount of oxide can grow, even at ambient or low
temperatures.
Figure 2-8 describes the Cabrera-Mott theory51 in more detail. Electrons flow
from the metal-oxide interface to the oxide surface to form negative oxygen
chemisorption species. Two electron transport mechanisms can be considered. For thin
oxide layers, electrons can tunnel through the oxide potential barrier. For thicker oxides,
the electron current is sustained by thermally activated semiconduction in the oxide.
Figure 2-8. Partial Steps of the Oxidation Reaction. A) transport of oxygen ions or
vacancies; reaction takes place at the metal-oxide interface; B) transport of
metal ions or vacancies reaction takes place at the oxide surface53
Figure 2-9 shows the band structure with and without the potential, V. Electrons
at the Fermi level in the oxygen are separated by a bandgap, U, from the conduction band
of oxygen. The physisorbed oxygen atoms are located on the oxide surface and are
30
electron acceptor sites. The distance between the Fermi level and the empty acceptor
levels of the oxygen are labeled W. Electrons that are in the metal with energies in the
width, W, gain energy if they occupy an empty surface site. The surface is charged
negatively and a positive compensation charge is left at the metal-oxide interface. This
causes a potential difference to build which shifts the energy levels of the acceptor sites
to higher values. Electronic equilibrium is reached when the energy of the acceptor levels
has approached the Fermi energy as seen in Figure 2-9. Thus, by the electronic
equilibrium, a contact potential is established which enhances the defect current and
subsequently oxide growth. From this theory, Cabrera-Mott derived an inverse
logarithmic growth law under the condition that the growth rate is limited by the
diffusion of metal ions in a strong electric field.52 Thus, in these cases the step that
controls the reaction rate has been attributed to the transport of ions or electrons across
the oxide film.
Figure 2-9. Solid State Structure of a Metal Covered by an Oxide Layer. A) without field;
B) with field53
Fromhold53 furthered the ideas of Cabrera and Mott with the introduction of the
coupled currents concept and numeric flux equation. He developed a flux equation for
31
ions under a strong electric field. It is derived from the condition of overall charge
neutrality and assumes that the concentration of charged species changes inside the oxide
are small compared with the flux of reacting particles.
Ishikawa’s52 work, which is based on Fromhold’s numerical flux equation and
Dignam’s flux equation for cations, uses an in-depth concentration profile equation of
mobile ion defects using experimental results to discern an inverse logarithmic growth
rate (i.e. an intercept of a coordinate time axis and a gradient). By calculation, he found
that the concentration of mobile cation defects at the surface of oxide/gas depends
strongly on the potential barrier, U, and changes greatly with an increase in electric field.
He also found the change of the concentration in the vicinity of metal/oxide interface
decreases with increasing electric field.
In 1997, Martin and Fromm54 consider the typical results of advanced models of
metal oxidation at low oxidation temperatures based on the theories of both Cabrera-Mott
and Fromhold. However, they point out that the consideration by Fromhold did not
correctly describe the reactions at interfaces. They include interface reactions by starting
with an adhering oxide layer, which is formed on a metal as in the following reaction:
xMe +
y
O2 
→ Me x + O y (14)
2
Once an oxide layer is formed on the metal, then the overall reaction will be
impeded since the reacting components, metal and oxygen, are now separated by an
oxide film. As a consequence, the reaction will proceed in partial steps, which include
generation, transport and annihilation of intermediate reaction products. Depending on
the type of the migrating lattice defect, the reaction can either take place at the oxide-air
interface or at the oxide-metal interface as seen in Figure 2-8. For the reaction, which
32
takes place at the metal-oxide interface, the transport of oxygen ions or vacancies is
considered. For the oxide-air reactions, transport of metal ions or vacancies is considered.
Metal or oxygen can be transported as interstitials or as vacancies through the oxide
layer. In addition, a flux of electrons is required from the metal to the oxide surface to
maintain overall charge neutrality and reactions must occur between lattice defects,
electrons and adsorbed species at both interfaces.
At the oxide-air interface, oxygen molecules are weakly bonded to the oxide
surface or physisorbed.
O2 ←

→ O2 ( phys)

(15)
The physisorbed oxygen species act as acceptors for electrons from the metal and
generate strongly bonded chemisorption species such as, O-, O2-, or O2-.
O2 ( phys) + e(metal ) ←

→ O2− (chem)

(16)
The adsorbed oxygen species can then undergo reactions with other defects on the
oxide surface. This will cause the annihilation of the metal interstitials.
xMe z + + zxO2 (chem) ←

→ Me x O y + ( zx − y / 2)O2 ( phys)

(17)
If all of the species on the oxide-air surface are assumed to be in equilibrium, then
the equilibrium relation can be represented as follows:
(θ Me z − ) (θ 0− )
−x
2
− zx
(θ o2 )
( zx − y / 2 )
− ∆G80
)
= exp(
k BT
(18)
At low pressures, the transport of oxygen to the oxide surface must be considered.
The flux of oxygen molecules hitting the surface at an oxygen pressure po is proportional
2
33
to po /ª (2mkBT). The rate of physisorption from the gas phase is given by the
2
following:
J 02 =
( x) p o2 (1 − θ 02 )
2πk B T
(19)
where x is a constant.
The desorption rate is proportional to the number of occupied sites as follows
J ' 02 = θ o2ν exp
− Ea
k BT
(20)
where Ea is the activation energy for the physisorption reaction and υ is the frequency
factor. An oxygen molecule impinging on the surface either reacts with a metal defect or
desorbs back to the gas phase.
At the metal-oxide interface the reaction proceeds as follows:
Me(bulk ) ←

→ Me z + (oxide) + ze − (inmetal )

(21)
The equilibrium concentration of the metal interstitials, Mez+, is given by:
θ Me = exp(
z+
− ∆G40
− zeV
) exp(
)
k BT
Lk B T
(22)
where –∆G4 is the standard free enthalpy.
Martin and Fromm54 considered the above interface reactions along with both
local ionic currents and electric currents, considered by Cabrera-Mott51 and Frommhold52
as discussed above. They coupled this with the idea of a tunnel current. The tunnel
current is given by the product of the flux of electrons in the metal to the oxide surface,
the tunnel probability across the oxide, and the probability of finding an unoccupied
chemisorption site at the oxide surface. Since the tunnel current decreases exponentially
with layer thickness, another mechanism for the electron current must become active to
34
guarantee further oxide growth. A number of mechanisms have been noted such as the
Richardson emission, semiconduction, or diffusion of electrons. Martin and Fromm chose
the Richardson emission for the inclusion of tunnel current to fully complete their model
of low temperature oxidation of metals.
Martin and Fromm’s54 presentation of the structure of low-temperature oxidation
models show that several partial processes are needed to describe a reaction mechanism.
Figure 2-10 is the simulated oxygen growth curves they obtained. The absorbed amount
of oxygen is given as layer thickness in ML O2 and plotted versus the logarithm of time.
The potential V existing across the oxide layer is shown at the bottom for the same time
scale. The oxide growth curve can be divided into three different stages. In the first stage
the layer growth is very fast and the potential is high. The potential is almost constant and
mainly determined by the chemisorption level. The reaction rate is determined by the ion
flux, which is very high since the activation barrier of diffusion is reduced by the high
electric field. In stage two, the potential curve is declining and the oxide growth rate
slows. The electronic flux to the oxide surface is declining. It does not suffice to keep the
potential at the equilibrium level since the electrons arriving at the surface are consumed
by reactions with ions. Therefore, the electronic forward flux becomes rate determining.
Finally, in stage three the potential disappears. The field across the oxide layer is
determined by low diffusion potentials of the ionic and electronic fluxes. The
consequence of this transport mechanism of coupled diffusion currents is a retardation of
the faster current to the lower one. The potential defines the three stages of lowtemperature oxidation.
35
Figure 2-10. Oxide growth curve and potential (V) determined by the Martin & Fromm
Model54
Oxidation Kinetics of Copper
Using the Cabrera-Mott theory, the oxidation-time dependence can be calculated
from the following equation where L and t are oxide thickness and time, and B is the
parabolic coefficient respectively:
L2 = Bt + C 2
(23)
B = C1e − ( Ea / kT )
(24)
Many studies55-58 have been completed to empirically determine the oxidation
kinetics and products of copper surfaces at various temperatures and compare to the
Cabrera-Mott theory. In most cases, the results correlated with respect to a high rate of
oxide growth followed by a decreasing to almost constant growth rate. This coincides
with the idea of oxide growth caused by a potential, which eventually decreases with
thickness due to a decrease in potential.
The copper surfaces studied include electroless, sputtered, and bulk copper using
a variety of methods such as thermogravimetric analysis (TGA), x-ray diffraction (XRD),
scanning electron microscopy (SEM), and x-ray photo-emission spectrometry (XPS).
When the results from these studies are compared, they determine that between 175275°C there is a critical temperature, which determines the dominant kinetics and
36
oxidation products of copper. Below this temperature, Cu is oxidized to form Cu2O with
linear or inverse logarithmic growth kinetics (depending on the study) where a compact,
fine-grained oxide layer is formed, minimizing further oxidation. CuO forms at higher
temperatures of about ~275°C. The growth of CuO scale follows a parabolic rate law or
cubic rate law, depending on the study, with activation energies ranging from 1580kJ/mol. Higher activation energies are calculated for bulk copper and lower for thin
film Cu, indicating that bulk and thin film copper have different oxidation mechanisms,
and thin film copper is more readily oxidized.
The concern in the current study involving post-electroplating defects is a
sputtered copper wafer surface, which has been oxidized at atmospheric temperatures
while being stored between process steps. M. O’Reilly59 employed spectroscopic
ellipsometry to study the low temperature oxidation rates of sputtered and electroless
copper surfaces. The thickness of the oxide layer grown in dry air at 50°C and 100°C was
plotted against time in figure 2-11. The thickness of the oxide film heat treated at 100°C
was greater than that of the oxide grown at 50°C. The reaction kinetics follow an inverse
rate law.
(a)
(b)
Figure 2-11. Sputtered Copper Film Oxidation at 50°C and 100°C. A) Cu2O thickness as
a function of time; B) Rate of oxide growth59
37
Copper Oxidation Phenomena
G. Shwalbe et al.59 found that copper films deposited by sputtering are in the α-Cu
phase. Regardless of the underlayer of the sputtered copper, either tantalum or silicon
dioxide, the preferred orientation is always (111). However, the texture quantified by the
intensity ratio of the (111) and the (200) peak depends clearly on the substrate. With
amorphous silicon dioxide as the underlayer, the orientation is less preferred as compared
to the <100> textured tetragonal Ta, where the Cu (200) peak is very small or not
detectable. XRD analysis completed by N.D. McCuster et al.60 showed that the texture
for sputter-deposited copper was mainly (111), with some (200) and other smaller
components. The volume fraction percentages of 56% (111) and 16% (200) are very
similar to those reported for sputtered copper on various other substrates.61 In addition,
Hoo-Jeong Lee62 found, from electron diffraction patterns, that β-Ta deposited on SiO2
has a strong texture with its closest packed plane (002). Subsequently, the growth of
(111) Cu is preferred, which has superior electromigration resistance.
The orientation of the sputtered copper surface is an important consequence for
copper oxidation. The oxidation process of Cu surfaces is dependent on the
crystallographic plane of the surface.63-69 For Cu(1 1 1) oxidation,64-67 three pathways
were found including: the formation of oxide domains growing into step edges through
ejection of Cu. The second is the association of the released Cu atoms with diffusing O
atoms to form “added oxide” islands on the terrace. The third is the ejection of Cu atoms
from terraces after most of the surface is covered with oxide islands. The last process is
similar to the oxidation processes for Cu(1 1 0) and Cu(1 0 0) surfaces, respectively
regarding mass transport. On Cu(1 1 0),55-56,58-59 Cu atoms diffuse from step edges and
38
uniform (2 X 1)O islands are formed on terraces as stripes. On Cu(1 0 0),57 the oxide
islands are formed on terraces by squeezing out Cu atoms from the terraces and the step
edges are less important during oxidation. The oxidation is observed to be
(ª2X2ª2)R45° O phase.
Structure of oxygen on Cu(1 1 1) surface
The formation of Cu2O thin films having the structure of Cu2O on Cu(1 1 1) are
frequently reported to be well-ordered.64-65 F. Besenbacher et al.65 used Scanning
Tunneling Microscopy (STM) and low energy electron diffraction (LEED) to study the
surface of oxidized Cu(111). At elevated temperatures the ordered ‘29’-(ª13R46.1° X
7R21.8°) and ‘44’- (ª73R5.8° X ª21R10.9°) structures are produced on Cu(1 1 1) by
exposure to oxygen.65 However, other researchers reported that only disordered structures
were formed on Cu(1 1 1) by oxidation, not only at room temperature, but also even at
elevated temperatures.66
Matsumoto et al.67 studied the adsorption of O2 on Cu(1 1 1) at room temperature
using scanning tunneling microscopy (STM) and low energy electron diffraction (LEED).
They found that the adsorption of oxygen leads to formation of a surface oxide by
incorporation of Cu atoms from step edges and terraces. This process is most rapid along
the close packed direction of the surface. Three characteristic features were observed
during the initial stage of adsorption: dark fringes along the Cu(1 1 1) step edges, dark
domains within the Cu(1 1 1) terrace, and rather mobile light patches on top of the Cu
terraces. They found that within these regions atomic scale features could be imaged as
well as a structure related to that of Cu2O. The dark fringes and dark domains grew
39
slowly in oxygen, whereas the bright patches only became visible when gas-phase O2 was
evacuated.
Figure 2-12 displays STM images by Matsumoto et al.,67 giving an overview of
the Cu(1 1 1) oxidation process. The bold arrows in panels (a)-(f) indicate the same point
on the surface. Panel (a) shows a large area scan (1000Å) of a terrace including some
vacancy islands (one is shown by the arrow) observed on the clean Cu(1 1 1) surface. The
step edges of the clean surface in Figure 2-12 (a) are smooth and then become angular at
exposures of 7X10-5 Pa O2, Figure 2-12 (b). The angular step edges join a new surface
structure, which appears with an apparent height intermediate between terraces separated
by a single step. The extent of the new structure is limited to the old Cu(1 1 1) step edges
which were present before O2 introduction. Matsumoto et al. suggests that this is
indicative that oxide grows into the upper terrace from the step edge.
Figure 2-12. STM images of clean Cu(1 1 1) and Cu(1 1 1) reacting in a pressure of O2
at 7x10-5 Pa at room temperature. A) Clean Cu(1 1 1) (1000 x 1000Å2
V=500 mV, I=0.03 nA); B) Recorded after 10 min in oxygen, the dashed
arrows indicate the original position of the step edge (1200 X 1200 Å2,
V=700mV, I=0.07nA); C) After 20 min exposure the step edges have
retreated (1200 X 1200 Å2, V=700mV, I=0.03nA); D) 33 min; E) 39 min
40
The small arrows indicate new ``terrace oxide'' formed in the latter stages
of adsorption; F) 66 min (3000 X 3000 Å2, V=700mV, I=0.03nA)67
Within the O2 at Cu(1 1 1) terraces, the initial image (a) shows vacancy islands,
which expand to form triangles with exposure to O2 in images (b)-(d). The large solid
arrows in (b)-(f) indicate the position of the growing “terrace oxide” which originated
from the vacancy island. The step edges and perimeters of the triangles on the oxidized
Cu surfaces prefer the close packed directions of the atomic rows of Cu(1 1 1), namely,
[1 1 0] and equivalent directions. In Figure 2-12(d) the surface is notably more streaked,
with the appearance of structure on top of the terraces. A great deal of surface
restructuring is apparent by the final panel in (f), with the loss of the clear triangular
features of (b) and (c).
Structure of Oxygen on a Cu(1 1 0) surface
Several studies68-70 have been completed to investigate the oxygen adsorption on
Cu (1 1 0) surfaces. They determined the formation of a reconstructed (2 x 1)O phase. In
two successive studies by Coulman et al.69 and Jensen et al.,70 it has been shown that the
reconstruction is of the “added-row” type and described by the following reactions:
O2 + 2 ∗ 
→ 2Oad
(25)
Cu step ←

→ Cu ad

(26)
Oad + Cu ad ←

→ Cu − O (27)

After the disassociation of molecular oxygen, atomic oxygen combines with
mobile Cu adatoms that are released at the terrace edges and diffuse onto the terrace.
Strong attractive interactions between these Cu-O compounds and/or further oxygen and
Cu adatoms result in the formation of Cu-O chains along the [0 0 1] directions.
41
Subsequently, Cu-O chains coalesce and form islands of the reconstructed (2 x 1)O phase
which exhibit gaps along the [1 1 0] direction.
S.Y. Liem et al.55 studied the diffusion of Cu and O adatoms on the clean
unreconstructed Cu(1 1 0) surface. They found that O adatoms diffuse easily in the
troughs between Cu rows (the activation barrier is only 150 meV), whereas jumping
across the Cu rows to another trough is less favorable (300 meV). This is in agreement
with a recent STM study by J. Buisset et al.56 in which O adatom diffusion was observed
only parallel to the troughs at 70 K. They also investigated the formation of isolated Cu–
O pairs aligned parallel to the [0 0 1] direction. Such a pair forms the critical nucleus for
the growth of the Cu–O–Cu added rows. The formation energy is 0.53 eV, indicating that
such pairs can form easily. Cu adatoms and adsorbed O adatoms can diffuse freely on a
surface. Eventually an O and a Cu adatom form a pair along the [0 0 1] direction that
becomes the nucleus for the formation of a new row. Additional Cu and O attach to
nucleus leading to a rapid growth of the chain. This process is most likely to happen close
to steps or already existing Cu–O–Cu rows, because rows and steps form a diffusion
barrier for O adatoms.56 Essential to this model is the high mobility of O and Cu adatoms
on the Cu(1 1 0) surface. Therefore the growth of the chains is basically only limited by
the number of Cu adatoms evaporating from steps.55 The growth of rows parallel to
existing steps in the [0 0 1] direction is particularly favored, because it can reduce the
required mass transport on the surface. In that case, once the nucleus for the row has
formed, additional Cu atoms can jump directly from the step to the chain. This process
and the fact that steps form diffusion barriers are probably responsible for the observation
that added rows first start to grow in the vicinity or even parallel to steps.
42
Structure of Oxygen on a Cu(1 0 0) surface
Kittel et al.57 studied the local adsorption structure of oxygen on Cu(1 0 0) at low
and high coverage using O 1s scanned-energy mode photoelectron diffraction. The
detailed quantitative determination of the structure of the 0.5 ML (ª2X2ª2)R45° phase
confirms the missing-row character of this reconstruction. The adsorbed O atoms lay only
approximately 0.1Å above the outermost Cu layer. The essential feature of the
(ª2X2ª2)R45° structure on Cu(1 0 0) is characterized by having every fourth [0 0 1] row
of outermost-layer of Cu atoms missing. The O adsorbate atoms occupy sites, which
would be essentially near-coplanar hollow sites in this top layer except for the removal of
one of the top-layer nearest-neighbor Cu atoms. Because of the presence of this missing
row, the O atoms actually occupy sites of the reduced top-layer along the edges of the
monatomic steps on either side of the missing row. The O atoms thus have three nearneighbor outermost layer Cu atoms and one Cu neighbor in the layer below at a similar
distance.
Copper Oxide Effect on Electroplating
The seed layer for copper electroplating should provide an electrically
uniform surface to ensure a continuous bulk electroplated copper surface.71 When the
surface has been oxidized by exposure to ambient conditions for an extended period of
time before electroplating, the current transport mechanisms through the metal oxide film
must be considered. Heuster72 showed that tunneling is the dominant current transport
mechanism through copper oxide films less than 30 Å thick, and that current density falls
exponentially with increasing film thickness. If the oxide film is thick enough, the
current transport will be accomplished by conduction involving carriers. Dogonadze73
developed a simple semiconductor model, which showed that the current through a metal,
43
which has been oxidized, is dependent on the oxide film thickness. By either mechanism
of current transport, tunneling or carrier conduction, the current density through an oxide
film will be strongly decreased with an increase in oxide film thickness. Therefore,
surfaces covered with a layer of oxide will inhibit electroplating. The oxide on the seed
layer should be removed to ensure a consistent bulk electroplated copper film.
Copper Surface Pre-treatments for Oxide Removal
As discussed above, a thin copper surface layer deposited by physical vapor
deposition or chemical vapor deposition is needed as a conductive substrate for copper
electroplating.74 However, following deposition of the copper seed layer, the wafers are
removed from vacuum and exposed to clean room ambient. The sections above describe
how a copper surface oxidizes readily even at room temperature.
Voids, observed after copper electroplating, have been identified as defects which
proliferate with increased delay time between PVD copper seed deposition and
subsequent bulk copper deposition by electroplating;45-47 the delay time is termed “seed
aging.” J. P. Lu et al.47 indicates that the lack of wetting is caused by the surface
oxidation of the copper seed prior to electroplating. Dogonadze et al.73 showed that
copper oxide can limit the current density in a localized area. Therefore, when a batch or
several batches of control wafers, un-patterned copper seed wafers used to monitor the
electroplating process, are fabricated at one time and stored they can become
compromised for future use. If the copper seed wafers are allowed to sit over time in a
clean room ambient and then electroplated, defects caused by the aging process will be
confounded with electroplating process-related defects. Even worse, device wafers,
which are not immediately electroplated, may develop bulk copper pitting, rendering the
device useless.
44
The aim of this project was to determine whether electrolyte wetting of the copper
surface could be improved and employing several treatments to the wafer surface could
mitigate post-electroplating defects. Four surface treatments just prior to electroplating
were explored to promote wetting thereby mitigating voids. The first treatment included
a reduction of the copper oxide film (formed over time on the copper seed layer as
control wafers are exposed to the clean room ambient) by hydrogen using a commercially
available sputtering tool. The second treatment involved reverse plating of the copper
surface, prior to bulk electrolytic copper deposition. The third treatment required rinsing
the seed wafer surface with the electrolyte and drying it prior to bulk copper deposition.
Lastly, a single wafer clean treatment, using ammonium biflouride with ethanolamine
clean was employed to remove any oxide film layer, which may have grown.
Plasma Pretreatment
The metal-to-oxygen bond is strong and may require ion bombardment to rid the
surface of oxide contamination. The reduction of metallic oxides by plasma treatment has
been widely used to deoxidize surfaces with either dc, radio frequency, or microwave
sources.75-78
T. Belimonte et al.78 studied copper oxides reduced under Ar-H2-N2 microwave
post discharges with different compositions to determine the active species (N2, H2, NHx)
responsible for metal oxide reduction. Belimonte et al.78 concluded that the diffusion of
hydrogen in copper and the dissociation of the H2 at the surface of Cu are the rate
limiting steps. Atomic hydrogen was found to modify the activation energy for the oxide
growth layer. The reduction reaction for copper oxide by hydrogen is given below:
Cu 2 O + 2 H → 2Cu + H 2 O
(28)
45
CuO + 2 H → Cu + H 2 O
(29)
In addition, they found that nitrogen reduces oxides but with slower kinetics than
with atomic hydrogen.
Z. Falkenstein et al.79 compared the removal rate of copper oxide by both argon
sputtering as well as C2F6 sputter etching. They determined that sputter etching by C2F6 is
three times more efficient than argon sputtering using RBS measurements. Woong Park
et al.80 treated a TiN film by hydrogen plasma before depositing the surface with copper
by MOCVD. They determined that copper nucleation is enhanced after a surface is
exposed to hydrogen plasma. In this case, TiN is reacted with hydrogen ions to form Ti
and NH3.
Reverse Electroplating
The phase diagram in figure 2-13 shows a copper-water system at 25°C. When
copper oxide is negatively biased in an electroplating medium, the most stable phase is
metallic copper. The surface on the copper oxide will be spontaneously reduced to
metallic copper. Two reduction steps may occur, one for cupric oxide and the other for
cuprous oxide.81 The reaction proceeds as follows:
Cu 2 O + 2e − → 2Cu + O −2
(30)
The metal species in the metal oxide is reduced to metal at the cathode, oxide ions
leave the metal oxide lattice and dissolve in the electrolyte. The dissolved oxide ions are
transported to the anode, where they are oxidized to oxygen gas.
If the bias is reversed such that the surface of copper wafer serves as the anode
then the following anodic reactions of the copper are expected to occur:
Cu → Cu + + e −
(31)
46
Cu → Cu +2 + 2e −
(32)
Cu 2 O + 2 H + → Cu +2 + H 2 O + 2e −
(33)
Figure 2-13. Potential versus PH diagram for the Copper-Water system at 25°C81
In this case, copper in the copper oxide film is oxidized and dissolved. Under low
PH conditions and positive bias, oxide phase films should be absent as seen by the phase
diagram in figure 2-13.
This treatment was chosen, as it requires no changes to the electroplating
equipment. The wafer is simply reverse biased and then electroplated.
Copper Sulphate Rinse
Copper cleaning in printed circuit board manufacturing is generally completed
using a mixture of hydrogen peroxide and sulfuric acid. However, a drawback of using
hydrogen peroxide is that the hydrogen peroxide is unstable and constantly gives off
oxygen molecules. Copper oxide has been found to readily dissolve in the sulphuric acid
solution. The reaction of copper in acidic copper sulphate solutions proceeds as follows:
Cu 2 O + 2 H + + SO4−2 → CuSO4 + H 2 O + 2e −
(34)
This indicates that the portion of the copper on the surface will also be dissolved
to form copper sulfate in the solution. T.C. Change et al.82 pre-treated aluminum oxide
wafers with hydroxylamine sulfate mixed with Cu2SO4 and found that this removed metal
47
oxide at the bottom of vias. When the wafers were cleaned with this solution prior to
tungsten CVD deposition, the result was a lower via resistance.
This specific copper cleaning method was chosen for its simplicity. It requires no
equipment or solution changes. The wafer is simply immersed in the electrolytic plating
solution containing copper sulfate. As discussed above, a metal M, immersed in an
aqueous solution containing ions of that metal, M+ will exchange ions between the ions
that make up the metal (Cu+2, O-2) and the ions in solution (Cu+2).
Ammonium Biflouride with Ethanolamine Clean
Ammonium biflouride (NH4F.HF) with ethanolamine is a cleaning solution to
clean the bottom of vias following oxide etch on a copper substrate. The intent of this
chemical mixture is to remove any polymeric material remaining from the photoresist
using the ethanolamine in the solution as well as removal of any oxide contaminants
which may have been sputtered from the side walls of the vias to the bottom of the via
which is exposed copper. Since the single wafer batch tool was already in use for a
similar application (trace oxide removal on copper after oxide etch), no additional tooling
or process changes were required to incorporate this chemical clean as a process step
prior to electroplating.
CHAPTER 3
MATERIALS AND METHODS
This chapter will describe the techniques and procedures used to conduct the
research described in the following chapters. The first section will describe the system
used to deposit the thin film layer of tantalum followed by copper seed, and the
subsequent electroplating process, which is utilized to deposit bulk copper. The second
section describes the techniques used to locate, quantify, and describe the defects found
on bulk copper wafers. An optical contrast tool for data location and review as well as a
scanning electron microscope (SEM) for defect classification were utilized for defect
monitoring. The third section describes the tools and processes utilized for the
experimental treatments including a sputtering system used for hydrogen reduction, a
single wafer cleaning tool utilized for chemical removal of residue, and an electroplating
system used for reverse electroplating and electrolyte rinse. The next section will
describe the methods used to determine the changes in the copper seed layer as a function
of seed aging including contact angle, reflectivity, sheet resistance, and opto-acoustics,
using goniometry, spectrometry, four-point probe technique, and laser opto-acoustics,
respectively.
Deposition Methods
Seventy-five unpatterned 200mm diameter silicon wafers were deposited with
500nm CVD oxide layer followed by sequential sputter deposition of 20nm of tantalum
(barrier layer) and 200nm of copper in a hollow cathode magnetron (HCM) sputtering
system manufactured by Novellus Systems. Following the deposition of the barrier and
48
49
seed layers, wafers were stored in a process cassette and left to age in clean room ambient
conditions (22°C, 56% Humidity) from several minutes to several days until they were
used for the experiment. Five wafers were utilized for contact angle, reflectivity, sheet
resistance, and opto-acoustic measurements as a function of time. The remaining wafers
were treated by different methods described in this chapter and then electroplated in the
SABRE plating system manufactured by Novellus Systems.
Barrier and Seed Deposition Methods
Sputter deposition of 20nm of tantalum (barrier layer) and 200nm of copper (seed
layer) was accomplished utilizing a hollow cathode magnetron (HCM) sputtering system
manufactured by Novellus Systems. The hollow-cathode magnetron (HCM) source is a
new metal deposition technology, which uses a high-density diffused plasma (1012/cm3)
for efficient ionization of sputtered metals. The HCM source and its components are
shown schematically in figure 3-1. The source consists of (1) a cup shaped target (2)
fixed magnet array (3) rotating magnet top array (4) an electrically isolated anode ring (5)
an electromagnet (6) a grounded adapter ring. The HCM employs a magnetron discharge
confined in an inverted cup-shaped target. As such, it does not require any additional rf or
microwave sources for generation of metal ions. The main difference between the HCM
and the planar PVD source are the shape of the target and the magnetic field near the
opening of the target. The magnetic field lines of the HCM are formed in such a manner
that the magnetic cusp is generated near the opening of the target. The cusp acts to extract
the plasma from within the target area to the area close to the surface of the wafer. As the
cusp moves closer to opening of the target, the source becomes more efficient at
confining electrons, resulting in a higher plasma density.
50
The source assembly sits on a high vacuum PVD chamber that is capable of
reaching vacuum levels in the 1 x 10-6 Torr range. The wafer is electrostatically clamped
on a stage that is below the adapter ring. The stage can be heated or cooled depending on
the process. For the copper process, the stage is cooled to a temperature of approximately
–50°C. The HCM target is cooled by running ~5 GPM of water directly behind the
annular flow. The source is operated with a DC power supply with a maximum output of
36kW. The ion flux shaping electromagnet is a 361-turn coil operated between 0.1 and
3.5 A dc depending on the material to be processed. E. Klawuhn83 and Z. Wang84 give a
detailed discussion of the physics of the operation of the source and its applications to
copper seed barrier deposition.
Figure 3-1. HCM Source83
Bulk Copper Deposition
Following copper seed deposition and aging time, wafers were deposited in a
fully automated commercially available electroplating tool (SABRE) manufactured by
Novellus Systems using a copper sulfate-based electrolyte bath. The SABRE system was
introduced in July 1998 after an extensive development program with IBM. The base
electrolyte consists of 176 g/L of sulfuric acid, 18 g/L copper, and 50 mg/L of chloride
51
stored in a 150-liter central plating bath reservoir. In addition, a variety of chemicals such
as inhibitors, accelerants, and brighteners, may be added to the bath for improved and
consistent feature fill. Since optimal electrofilling of 4:1 aspect ratio trenches requires the
addition of 1 ml/L of accelerator and 25 ml/L of suppressor, this was included in the
make-up of the bath as seen in figure 3-2. A detailed discussion of the physics of the
electrolytic deposition is given by A. Bard et al.35
Stock Plating
Solution
Chloride
Ion
Water
Additives
CENTRAL PLATING
BATH
(150 Liters)
Rinse Component - Water
SPIN / RINSE / DRY
CELLS
Figure 3-2. Central Plating Bath Schematic
The SABRE requires two types of process modules to complete the electrofill
process, one for electrofilling (3 stations total) and the other for spinning, rinsing, and
drying of the wafers (another 3 stations). Figure 3-3 shows the design of the plating cell
on the Novellus Sabre. The proprietary design of the wafer fixture, includes a contact
scheme which eliminates backside contact with the plating bath, preventing copper
contamination. During processing, the wafer bevel and the backside are kept dry by the
wafer fixture's triple seal. The triple seal causes an edge-exclusion of the plated film,
which helps eliminate buildup at the bevel.
An automated wafer handler retrieves wafers from the carrier cassette and places
the wafer (backside-up) onto the wafer fixture. Vacuum seals hold the wafer in place and
cause a watertight seal of the electrical contacts. The wafer fixture lowers into the plating
bath with a low current (1 Amp) applied.
52
Figure 3-3. Plating Cell Geometry
The front side of the wafer enters the plating bath while spinning at 100 rpm, as a
solution pumps the electrolyte from the plating reservoir to the plating cell at a solution
flow rate of 12 liters per minute. The plating solution returns to the reservoir by means of
overflowing between the cell wall and the outer liquid containment jacket surrounding
the internal plating cell. The plating bath temperature is operated at 25°C. An average
current density of approximately 10 mA / cm2 is applied to the wafer during deposition
with the current varying over different steps within the process. The total deposition time
is approximately 70 seconds per wafer.
After the wafer fixture retracts to slightly above the plating solution, the wafer is
rinsed and spun with de-ionized water to remove the electrolyte solution. The automated
handler then removes the wafer from the plating cell and places it in a spin/rinse/dry unit
where the wafer is rinsed and then spun at 1600 rpm to remove any subsequent traces of
electrolyte.
Approximately 6 kÅ of bulk copper material are deposited using the method described.
Figure 3-4 shows the front and top view of the SABRE plating tool.
53
Figure 3-4. Sabre Plating Tool: Front-View / Top-View
Copper Defectivity Measurements
Inspection of bulk electroplating copper defects was conducted using an optical
contrast technique employed by the KLA-Tencor AIT II system. Following defect
location using the AIT II, a detailed defect review was completed using the Scanning
Electron Microscope. This approach has been used to classify and address defects in a
systematic manner. The defects were classified as voids or as other types not relevant to
this study.
Defect Location
The total defect count on the wafers following electroplating were characterized
using an optical contrast inspection tool common to most semiconductor facilities, KLATencor AIT II. This tool was also used to ensure that following copper seed deposition,
wafers with less than 35 defects at 120nm or greater size were utilized in this experiment.
The AIT uses Darkfield inspection optics of a laser beam to illuminate the wafer
surface at a low angle, thereby minimizing light scatter from the wafer surface and
previous layers, while maximizing the scatter from defects and other anomalies. In
“double darkfield” systems such as the AIT II, the optics that collect the scattered light
are also located at a low angle, further suppressing unwanted surface scatter or “noise.”
54
Polarizers, advanced optical enhancements, and software algorithms work further to
extract the signal from background scatter. Once signals are captured, computations
isolate defect signals and assign specific x-y coordinates. The double darkfield
technology provides color and grain suppression to optimize the defect signal and filter
out noise. The AIT II inspection system has three independent collectors with selectable
polarizers. The laser spot size chosen to maximize true defect detection and minimize
noise was 0.10 um.
Scanning Electron Microscopy
Scanning Electron Microscopy (SEM) was utilized to obtain the film surface
image at magnifications up to 20,000x. The SEM functions using electrons emitted from
a heated filament. A voltage of 15kV then accelerates these electrons before a magnetic
condenser lens reduces the electron beam size. Electrons from a source are focused on the
sample. The electrons reflect off the sample and are then picked up by an electron
detector and processed into an image.
The SEM has a tungsten filament. When passing current through it heats such a
filament, it not only emits light, but an electron cloud forms around the filament. A
negatively charged cathode plate is placed near the filament with a hole in it and a
positively charged anode (which they are attracted to) under this with another hole in it
(electron gun). The electron cloud is attracted to the anode plate enough that they will
travel through the hole in the cathode. But in doing so, they gain enough speed that most
of them travel right through the hole in the anode plate. The speed of the electrons
emitted from this gun is controlled by the amount of potential (accelerating voltage)
applied to the cathode and anode plates. Magnetic lenses are used to reduce the spot size
further to provide the appropriate magnification for secondary electron image.
55
Secondary electron image provides information about sample surface
morphology. The secondary electron collector is placed at a low angle close to the
sample. EDX detector is also placed close to the sample to collect the characteristic xrays. S. Wilson85 gives a more detailed discussion about the SEM/EDX. The SEM/EDX
system used for this work was the SEMVISION manufactured by Applied Materials.
Surface Treatments
Four experimental treatments described in this section were considered to reduce
the effects of seed aging. Every three days, two wafers were subjected to each surface
treatment and then immediately electroplated. Two untreated wafers, which served as
controls for the experiment, were electroplated at the same time as the treated wafers.
Copper Oxide Reduction
The copper oxide reduction by hydrogen was completed in a commercially
available physical vapor deposition tool manufactured by Applied Materials. A plasma
containing 5% hydrogen in helium gas is formed above the wafer surface. The chamber
consists of an upper inductor coil powered by a 2 MHz RF power supply and a cathode
powered by a 13.56 MHz supply. The coil is a copper strap wrapped around
hemispherical dome. The electric and magnetic fields are induced inside the dome
causing the electrical breakdown of He and H2 to create a plasma. The plasma density
inside the coil increases as the coil power is increased.
To reduce a copper oxide film, the hydrogen molecules dissociate and diffuse to
the wafer surface where oxide reduction takes place. The reduction of the copper oxide is
the formation of water and metallic copper. The reactions are described below:
56
Cu 2 O + 2 H → 2Cu + H 2 O
∆G = −69kcal / mol
CuO + 2 H → Cu + H 2 O
∆G = −95kcal / mol
The hydrogen molecules are broken to a more reactive state by the plasma.
Thermal dissociation of hydrogen is not necessary. The process is performed at 80 mT or
less pressure. The low pressure allows the water product molecules to be pumped out by
the turbo pump. The pump is a 350 l/sec leybold turbo pump. The 5% hydrogen mixture
is provided by a premixed cylinder. A metal shield made of a magnetic alloy contains the
RF energy. The quartz insulator covers the sides of the titanium pedestal. The thick
quartz forces the RF power to go to the plasma through the wafer rather than radiate in all
directions.
Reverse Electroplating
The reverse electroplating treatment was carried out on wafers with varied seed
age in the Novellus Sabre Plating system as described above. The plating solution
consisted of 176 g/L of sulfuric acid, 18 g/L copper, and 50 mg/L of chloride, 1 mL/L of
accelerator, and 25 mL/L of suppressor.
The wafer was reverse biased with –2 amps of current, spun at 100rpm and
lowered into the plating solution for approximately 2 seconds. In this case, the copper
wafer acted as the anode when current was applied and the surface of the wafer dissolved
leaving the surface with a fresh metallic copper layer. The reaction at the wafer surface
is as follows:
Cu ( s ) → Cu 2 + + 2e − → Cu ( s )
57
Following reverse electroplating, the wafer surface was rinsed with deionized
water for 3 seconds and then placed in the spin rinse and dry unit by an automated
handler and again rinsed for 30 seconds while being spun at 1600 RPM to remove any
residual electrolyte solution.
Copper Electrolyte Rinse
The electrolyte rinse treatment was also carried out in the Novellus Sabre
electroplating tool. The wafer was spun at 100 rpm and then lowered into the plating
solution for 3 seconds. No current was applied to the wafer during the treatment. The
plating solution consisted of 176 g/L of sulfuric acid, 18 g/L copper, and 50 mg/L of
chloride, 1 mL/L of accelerator, and 25 mL/L of suppressor.
Following the electrolyte rinse in the solution, the wafer surface was rinsed with
de-ionized water for 3 seconds and then placed in an spin rinse and dry unit and rinsed
for 30 seconds while being spun at 1600 RPM to remove any residual electrolyte
solution. The intended reaction at the wafer surface is as follows:
CuO + H 2 SO4 (l ) → CuSO4 + H 2 O(l )
Single Wafer Clean
Each wafer was treated individually using a single wafer spin-process
technology, on the SEZ 203. The system includes a process chamber, wafer chuck and
medium dispenser. The wafer to be processed is placed on the chuck with the side to be
processed facing up. The wafer floats above the rotating chuck without touching it. A
nitrogen cushion protects the side facing the chuck throughout the entire process.
A proprietary chemical composed of triethanolamine (polymer removal) and
ammonium bifluoride (oxide removal) is utilized for the treatment. This proprietary
58
mixture is formulated to remove any residue, remaining on the copper surface. This
chemical clean is currently used for copper interconnect fabrication to remove residue on
copper left by the oxide etch process. The residues are known to increase resistance and
reduce device speed. The wafer is sprayed with the proprietary chemical while being
spun at 1500 rpm inside an enclosed process chamber.
Seed Surface Characterization
The copper seed surface of one monitor wafer for each experimental cell was
characterized daily for contact angle, reflectivity, and opto-acoustic spectral changes. In
addition, on the twelfth day of the experiment, one wafer was subjected to each of the
surface treatments and measured for contact angle and reflectivity.
Contact Angle Measurements
The contact angle of one copper seed sample wafer was measured over a period of
14 days as well as before and after each separate wafer treatment on the fourteenth day of
aging. Contact angle measurements are used as indication of the chemical bonding of the
uppermost surface layers of a solid. This bonding determines wettability and adhesion,
and allows prediction of trace surface contaminants. The contact angle is reported in
degrees (as seen in figure 3-5) as a measure of a surface's hydrophobicity. The degree of
hydrophobicity can be determined from the height/diameter ratio of an aqueous bubble on
a surface. A hydrophobic membrane would cause the bubble to spread over the
membrane surface since water is excluded from the bubble-membrane interface. This
“flattening” would correspond to a smaller ratio (a perfect sphere would have a ratio of
1.0), while a hydrophilic surface would result in a larger ratio. Thus a reduction in the
height/diameter ratio caused a larger contact angle and a greater hydrophobicity of the
membrane surface.
59
Figure 3-5. Contact Angle Measurement
The drop of liquid forming an angle may be considered as resting in equilibrium
by balancing the three forces involved: the interfacial tensions between solid and liquid
(SL), that between solid and vapor (SV) and that between liquid and vapor (LV). The
angle within the liquid phase is known as the contact angle or wetting angle. It is the
angle included between the tangent plane to the surface of the liquid and the tangent
plane to the surface of the solid, at any point along their line of contact. The surface
tension of the solid will favor spreading of the liquid, but this is opposed by the solidliquid interfacial tension and the vector of the surface tension of the liquid in the plane of
the solid surface.
A Rame’-Hart manual contact angle tool, seen in figure 3-6, was utilized for
contact angle measurements. With a wafer placed on the stage, a mounted microscope
produces a sharply defined image of a pendant drop, observed as a silhouette. The stage
is movable, such that droplet can be centered on a viewable crosshair using the
microscope. An angled scale with 0.2° resolution is used to manually determine the
contact angle.
60
Figure 3-6. Rame-Hart Goniometer
Sheet Resistance
The sheet resistance of one copper seed sample wafer was measured over a period
of 14 days as well as before and after each separate wafer treatment on the twelfth day of
aging. The four-point probe method was used to conduct resistivity measurements of
wafers using the Tencor OmniMap™ Resistivity Mapping System model RS75. Fourpoint probe sheet resistance measurements were made on all wafers using a 194mm test
diameter. Five concentric rings equaling 121 test sites were measured on each wafer, and
the average was recorded.
The four-point probe setup used consists of four equally spaced F-probe type
tungsten carbide metal tips with a tip-radius of 40µm, as seen in figure 3-7. Each tip is
supported by 100-gram spring load on the other end to minimize sample damage during
probing. The four metal tips are part of an auto-mechanical stage, which travels up and
down during measurements. A high impedance current source is used to supply current
through the outer two probes; a voltmeter measures the voltage across the inner two
probes to determine the sample resistivity. The F-probe spacing (s) is 0.635 millimeters.
61
Figure 3-7. Sheet Resistance Measurement Set-Up
The sheet resistance, Rs, can be calculated by the following equation where V is
the measured voltage, I is the applied current and k is a constant which includes
geometric effects such as tip spacing:
V 
Rs = k  
I
Once the sheet resistance of a material is measured, it can be used to calculate the
film thickness, t, when bulk resistivity, ρ, is known, using the following equation:
ρ
Rs =  
t 
Optoacoustic Measurements
The optoacoustic spectrum of one copper seed sample wafer was measured over a
period of 14 days as well as before and after each separate wafer treatment on the twelfth
day of aging using the MetaPULSE system manufactured by Rudolph Technologies (see
figure 3-8). In addition, from this spectrum, the thickness of the copper seed wafers
following treatments was determined. The MetaPULSE uses picosecond ultrasonic laser
sonar to measure the thickness of single or multi-layer metal films ranging from less than
62
20 Å to greater than 5 µm. Thickness measurements were determined from the
optoacoustic spectra to determine if the treatments affected the seed layer thickness.
Figure 3-8. MetaPULSE System
Figure 3-9 depicts the operation of the MetaPULSE system. A 100 femtosecond
(100 x 10-15 second) laser light pulse (pump pulse) focused onto the sample surface
produces a localized 5-10° C temperature rise (1a). Rapid thermal expansion generates a
sound wave that propagates away from the surface at the speed of sound in that material
(1b). When the sound wave encounters an interface, a portion of it reflects back to the
surface as an echo, the remainder crosses the interface and continues into the next layer
(1c). When the echo returns to the surface it changes the surface reflectivity (1d). This
change in sample reflectivity is detected by light, which has been diverted by a beam
splitter from the probe pulse. The change in reflectivity is plotted against delay time
between the original pulse and the portion of the pulse that is delayed. The system
converts the elapsed time between sound generation and echo detection into an accurate
film thickness value. The thickness, t, can be determined from the observed oscillatory
behavior of reflectivity change with period τ, by ,
t=
vτ
2
63
where ν is the velocity of sound through the film. Film thickness is adjusted
iteratively until simulated data, based on a model, matches the measured data.
Figure 3-9 MetaPULSE System Operation
The echo's amplitude and phase can be used to detect film properties, interlayer
problems and missing layers. After reflecting off of an ideal interface the amplitude will
decrease by a factor equal to the acoustic reflection coefficient between the film and the
substrate. Amplitude damping in any other form indicates a non-ideal case. Since
different problems affect amplitude and phase uniquely, a variety of interlayer
phenomena can be measured.
Reflectance Spectrometry
The reflectivity of one copper sample wafer was measured over a period of 14
days as well as before and after each separate wafer treatment on the twelth day. The
64
reflectivity of the sample wafers was measured using the Therma-wave Opti-Probe 3290,
seen in figure 3-10, which is found in most semiconductor facilities.
Figure 3-10. OptiProbe 3290 System
A spectroscope, as seen in figure 3-11, is an instrument that breaks up a beam of
light or other electromagnetic waves into the various colors or wavelengths which are
present, allows measurement of the wavelengths of the various components, and
sometimes allows measurement of the relative intensity of these components (in which
case the instrument is called a spectrometer). For visible light, the light is normally
broken up (or dispersed) with either a prism or a diffraction grating.
Most materials are selective in the wavelengths of electromagnetic radiation,
which they reflect. The study of this property, called reflectance spectroscopy, is a basic
tool in the study of surface properties. With this technique, the light does not originate
with the object studied, but comes from somewhere else and reflects off of the object
studied. Some of the light is absorbed or transmitted and the remaining light is reflected.
The reflectance is defined as the ratio of the reflected and incident beams. The
transmittance is given by the ratio of the intensities of the transmitted and incident beams.
For normal incidence, the reflectance (or reflectivity) R and transmittance T are written
as follows:
 n − nt
I
R = R =  i
I O  ni + nt



2
65
T=
I T  4ni2  nt

=
I O  (ni + nt )2  ni



Figure 3-11. Spectroscope
The Opti-Probe uses combined visible/UV light sources and solid state detectors
to measure reflectance from the wafer surfaces at different wavelengths. The system
contains deuterium and tungsten bulbs as UV and Visible light sources, respectively. The
combination of these two light sources allows a continuous full spectral range of
wavelengths. A monochrometer selects the appropriate wavelength for measurement in
the UV range. There are I-UV and R-UV detectors to detect incident and reflected
signals. The effective beam spot used in this experiment is 15µm.
Experimental Details Summary
This section will describe a concise overview of the experiment. For more
specific information regarding the tools and procedures used, the sections above should
be referred to.
66
Copper Seed Aging
Unpatterned 200mm diameter silicon wafers were deposited with a 500nm CVD
oxide layer followed by sequential sputter deposition of 20nm of tantalum (barrier layer)
and 200nm of copper in a commercially available PVD cluster tool. Following copper
seed deposition, each wafer was measured on an optical inspection tool for total defect
count. Only wafers with less than 35 defects at 120nm or greater size were utilized in
this experiment. The wafers were stored in a closed cassette from several minutes to
several days until they were used in the experiments. The copper seed surface of one
monitor wafer for each experimental cell was characterized daily for contact angle, sheet
resistance, reflectivity, and opto-acoustic spectral changes.
Copper Seed Aging Treatments
Every three days, two wafers were subjected to surface treatments described in
the section above and then immediately electroplated. Two untreated wafers, which
served as controls for the experiment, were electroplated at the same time as the treated
wafers. Following bulk copper deposition, the wafers were again measured for their total
defect count and reviewed in a scanning electron microscope (SEM) to characterize the
defects as voids or classified as other types not relevant to this study. In addition, on the
twelfth day of the experiment, one wafer was subjected to each of the surface treatments
and measured for contact angle, sheet resistance, reflectivity, and opto-acoustic spectral
changes.
CHAPTER 4
EFFECTS OF COPPER SEED AGING
Voids, observed after copper electroplating, have been identified as defects which
proliferate with increased delay time between PVD copper seed deposition and
subsequent bulk copper deposition by electroplating;45,47 the delay time is termed “seed
aging.” It is postulated that lack of adequate wetting of the copper seed surface by the
electrolyte induces voids. This lack of wetting poses a particular problem when unpatterned copper seed wafers are used as control wafers to monitor the electroplating
process. Typically, in a manufacturing environment, a batch or several batches of control
wafers are fabricated at one time and stored for monitoring subsequent processing steps.
If the copper seed wafers are allowed to sit over time in a clean room ambient and then
electroplated, defects caused by the aging process will be confounded with electroplating
process-related defects. Therefore, the difficulty in discerning intrinsic copper defects
caused from seed-aging induced defects will prevent the electroplating process from
being properly monitored.
Early Indications
Systematic Defect Study
Defects identified on patterned copper electroplated using the AITII were
quantified and classified by type on a Scanning Electron Microscope (SEM). A pareto
chart of the defects compiled from four patterned electroplated wafers each coming from
a different wafer lot is given in figure 4-1. The wafers detailed in the pareto chart were
immediately electroplated following copper seed and barrier deposition. This shows the
67
68
“typical” expectation for quantity and type of electroplating defects. The y-axis gives the
quantity of defects per square centimeter of wafer surface. The SEM images of the
specific defect type on a one micron scale are included to better understand the
classification of defect type.
Figure 4-1 indicates that the “embedded” defect type is the most prevalent with a
defect density almost ten times as great as the void or surface pits. The void picture
shows three trenches, which were not plated with copper during the electroplating
process. The final SEM image depicts small pits with unknown depth. The small pits are
usually apparent as “strings” of small voids.
Figure 4-1. Common Electroplating Defects
To gain additional insight into the repercussions of the above defect types,
patterned wafers with similar defect types were chemical-mechanical polished (CMP)
to determine if defects are removed or persist to subsequent process steps. The two
defects studied included the embedded defect and a void that traverses five copper
lines. The top leftmost SEM image in figure 4-2 shows an embedded defect
approximately 3 µm in width identified immediately after electroplating. The defect
69
location was visited again following CMP. This image is shown to the right. This
shows that the embedded defect is removed during chemical mechanical polishing
leaving completely filled copper lines. The bottom left most SEM image shows a
copper void that is approximately 3 µm in length. Following CMP (right), copper is
missing within the metal lines. It appears that the chemical mechanical polishing
displaced the surrounding copper into the metal lines, leaving them only partially
filled with copper. This could result in “opens” as current fails to flow through the
open area of the metal.
Figure 4-2. Defects Post Electroplating (Left) and Post CMP (Right)
Figure 4-3 (left) shows a defect map of a blanket copper wafer, which was
electroplated with 8,000Å of copper twenty days after the copper seed and barrier layer
was deposited. The result shows a significant deviation from the defect count and type
identified in figure 4-1. In fact, with approximately 4000 defects it was impossible to
70
classify each one as embedded, voids, or pits. However, the swirl pattern on the defect
map indicates that the majority of the defects are pits and voids in the wafer surface.
In the center of figure 4-3, a SEM image of the “swirl” region is included. To
determine whether or not the pits extended beneath the surface layer of copper, the wafer
was chemical-mechanical polished, removing approximately 6000Å of bulk copper. The
right defect map in figure 4-3 shows that 3000 defects remain following chemical
mechanical polishing. The defect pattern on the polished wafer is similar to the
electroplated copper defect map with few defects being removed during chemicalmechanical polishing. The remainder of the defects, if located in patterned areas, could
possibly cause “opens” in the metal lines.
Total
Defect
Count:
3969
Total
Defect
Count:
2856
Figure 4-3. Swirl Defect Post Electroplating (left); Swirl Defect Post CMP (right)
The important difference between the results displayed in figure 4-3 and figure 41 is the copper seed aging time. Figure 4-1 displayed “typical” defect results when wafers
are immediately electroplated following barrier seed deposition. However, figure 4-3
shows a significant increase in pit and void defects on wafers that were plated after the
copper seed wafer was aged for twenty days.
71
Seed Aging Indication by Defect Increase
The information above indicated a possible connection between copper seed aging
and resulting electroplating defect count and type. To further investigate this relationship,
several patterned wafers were deposited with a tantalum barrier and copper seed layer as
described in section 3.1.1, stored in a wafer cassette, and copper electroplated over time.
The defects were classified and counted by type to determine defect increase over time.
Figure 4-4 shows an increase in the total copper defects with seed aging time. The
first group of four wafers was immediately electroplated following PVD barrier
deposition and resulted in approximately 75 defects. However, wafers, which were
deposited following five days of seed aging, had in excess of 250 defects following
copper electroplating.
Figure 4-5 shows the classification of defects by type for the electroplated wafers.
This plot shows that the embedded defect type does not increase as function of aging.
However, the pits and voids show a significant increase with time. As discussed
previously, the pits and voids are not merely on the surface but extend to the copper seed
layer. The result is a trench or via area which is not fully electroplated.
350
Post-Electroplating Defect Count
4 wafers electroplated each day
300
250
200
150
100
50
0
-1
0
1
2
3
4
5
6
Number of Days Between PVD Seed and Copper EP
Figure 4-4. Electroplating Defects as a Function of Copper Seed Delay Time43
72
Post Electroplating Defect Count
250
EP-Voids
Embedded
200
Voids
150
100
Embedded defect
50
0
-1
0
1
2
3
4
5
6
Number of Days Between PVD Cu Seed & Cu EP
Figure 4-5. Classified Electroplating Defects as a Function of Copper Seed Delay Time43
Seed Aging Indication by Contact Resistance Increase
Parametric testing was conducted to determine whether or not a difference in seed
aging from 0,1,2,or 5 days could be discerned. The wafers discussed in the previous
section were chemical mechanical polished and then electrically tested for contact
resistance. Karthikeyan Subramanian of Bell Laboratories in Orlando, Florida provided
the results.
A probe machine with the proper probe card for this device structure was used to
test the second metal level via structure. A voltage is applied to the component contact
probe and the resultant current between the contacts is measured. The resistance of the
device modifies the current. The fundamental relationship is known as Ohm’s Law:
R=
V
I
Figure 4-6 displays the median result from each test wafer normalized with
respect to the first data point. The results show that contact resistance is increased by
73
30% from wafers electroplated after five days of seed aging versus wafers, which were
immediately electroplated. This result shows that seed aging can directly affect device
performance.
Normalized Median Resistance
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0
100
200
300
400
Time delay between Barrier Seed and Electroplating (hours)
Figure 4-6. Normalized Via Resistance as a Function of Barrier Seed Aging
Aged Seed Layer Characterization
The copper seed surface of one monitor wafer for each experimental cell was
characterized daily for contact angle, reflectivity, and opto-acoustic spectral changes.
Contact Angle Measurements
One copper seed wafer was measured for contact angle daily for fourteen days
and stored in a wafer cassette between measurements. The wafer was measured at the
center, top, and bottom and the contact angle results were presented for the three points.
The data from the copper seed wafers that were measured on a daily basis indicate a
linear increase in contact angle with time as seen in figure 4-7. The contact angle for a
newly sputter deposited copper seed wafer is about 40° as compared to a contact angle of
about 63° after fourteen days of seed aging. Figure 4-7 shows a linear increase in contact
angle with copper seed aging time between one and fourteen days.
74
Contact Angle
65
60
55
50
45
40
0
5
Day
10
15
Figure 4-7. Contact Angle Increase with Seed Aging
A larger contact angle indicates a greater hydrophobic behavior of the wafer
surface. An increase in hydrophobicity suggests a decrease in wettability in aqueous
solutions. Therefore, as the contact angle is increased with time, the copper surface is less
likely to be wetted by the electrolyte. If the surface is not completely wetted by the
electrolyte during electroplating, then the copper deposition process will be hindered,
resulting in copper voids.
Spectrometry of Aged Seed Wafers
One copper seed wafer was measured for reflectivity daily for fourteen days and
stored in a wafer cassette between measurements. Each day the reflectance measurement
was made in the center point of the wafer. The wavelength of incident light was increased
in 4 nm increments from 250-650 nm. The reflectance was measured at each of these
increments. Figure 4-8 shows the reflectance versus wavelength curve constructed from
100 data points. At low wavelengths of incident light, approximately fifty percent of the
incident light is reflected. At incident light wavelengths of 370-600 nm the reflectance
increases sharply from about 0.7 to 2.6. At incident light wavelengths greater than
600nm, the reflectivity remains constant at approximately 2.6.
75
A graph of the lower and higher incident light wavelengths is constructed to show
the reflectivity of the copper wafer decreases with seed aging. Figure 4-9 shows the
reflectance from one wafer measured on day 1, 3, 11, and 20, as well as a copper seed
wafer with a layer of 30Å of copper oxide. With incident light wavelengths ranging
between 250-350 nm, the most significant decrease in reflectivity occurs between day 1
and day 3. The wafer with 30Å of copper oxide has reflectivity spectra similar to the
wafer aged for 20 days. Figure 4-10 shows the spectra for higher wavelength incident
light between 500-550 nm, the reflectance is also decreased but the most significant
decrease occurs between day 3 and day 11 of seed aging. Again, the wafer with 30Å of
copper oxide has reflectivity spectra similar to the wafer aged for 20 days.
The change in reflectivity of the wafer surface indicates that the surface properties
Reflectance
are changing. Contamination or oxidation is a likely cause for the decrease in reflectivity.
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
250
300
350
400 450 500
Wavelength (nm)
550
600
650
Figure 4-8. Copper Seed Reflectance as a Function of Incident Wavelength of Light
76
Reflectivity
0.73
Day 1
Day 3
Day 11
Day 20
30Å of CuO
0.63
0.53
0.43
250
300
Wavelength (nm)
350
Figure 4-9. Copper Seed Reflectance as a Function of 250-350nm Wavelength Light
Reflectivity
1.74
Day 1
Day 3
Day 11
Day 20
30Å of CuO
1.64
1.54
500
520
Wavelength (nm)
540
Figure 4-10. Copper Seed Reflectance as a Function of 500-550nm Wavelength Light
Opto-acoustic Spectra of Aged Seed Wafers
One copper seed wafer was measured daily for opto-acoustic spectra changes. In
addition, a separate wafer was oxidized (50°C anneal, ambient conditions; 30min) to
form 30Å of copper oxide and measured for comparison. The opto-acoustic spectrum is
obtained when the test wafer is subjected to a short laser pulse, which generates heat and
subsequently strain. The rapid thermal expansion in the heated volume induces a sound
77
wave, which travels from the surface of the film towards the interior of the film at the
velocity of sound within the material.86 The sound wave is partially reflected at each
interface. After being reflected, the sound pulse returns to the surface of the film, causing
a change in the reflectivity of incident light when the wave returns to the surface. The
change in surface reflectivity is identified by means of a second laser pulse, which is
controllably delayed by a time t from the first laser pulse. The opto-acoustic spectrum is a
plot of the change is surface reflectivity versus time. The longer the time, the farther the
sound wave has penetrated the wafer before reflecting off an interface. Times closer to
zero indicate what is occurring at the wafer surface.
Figure 4-11 shows acoustic spectra from a copper seed wafer aged 1, 4, 6 and 11
days as well as a wafer with 30Å of copper oxide film. These spectra have been overlaid
as a comparison to identify any significant deviations. At approximately 10 picoseconds,
the first change in reflectivity is noted. For the wafer aged only 1 day, only a slight
change in reflectivity is noted. However, an increase in reflectivity is identified as seed
aging time is increased as well as in the case of the copper seed wafer with 30Å of copper
oxide. The increase in amplitude indicates that the sound wave has encountered an
interface, such as an oxidation or contamination layer, and was reflected back to the
wafer surface causing a localized change in reflectivity.
The relative amplitudes of echoes give information about material properties and
interfaces. The amplitude depends on the acoustic reflection coefficient, r, where
r=
Z substrate − Z film
Z substrate + Z film
and Z is the acoustic impedance, which is the product of density and sound
velocity. A film, which is poorly bonded to another, generally has a larger acoustic
78
reflection coefficient since the transfer of acoustic energy is less efficient on a
contaminated interface.
Figure 4-11. Opto-acoustic Spectrum from Aged Seed Wafers
A second change in reflectivity is noted at 62 picoseconds and is caused by the
reflection of the sound wave off of the tantalum-copper interface (see figure 4-12).
Neglecting a contamination layer, the thickness of the copper seed layer, t, can be
determined from the observed oscillatory behavior of reflectivity change with period, τ,
by
t=
vτ
2
where v is the velocity of sound in the material. The period, τ, is approximately 62
picoseconds and the velocity of sound in copper is 52.5 Å per picosecond. From this
information the copper seed layer thickness is calculated as follows:
79
t=
62 ps * 52.5Å / ps
= 1627 Å of Cu
2
The time interval between successive peaks reveals the thickness of each
successive layer. Therefore, the next echo returns to the surface as identified by a change
in reflectivity at 77 picoseconds is due to the Ta / Oxide interface. The thickness of the
tantalum layer, given the velocity of sound of 41.6 Å/psec in tantalum, is calculated as
follows:
t=
(77 − 62) ps * 41.6Å / ps
= 312Å of Ta
2
The echoes from the Cu-Ta and Ta-oxide interfaces repeat themselves with a
decrease in amplitude. After reflecting off of an ideal interface the amplitude will
decrease by a factor equal to the acoustic reflection coefficient between the film and the
substrate. Amplitude damping in any other form indicates a deviation from an ideal
surface, such as a contamination or oxidation layer.
Cu Seed Layer (1600
(1550 ÅÅ )
Substrate
Ta
(300 Å)
Figure 4-12. Copper Seed Layer Stack
Sheet Resistance Measurement
The sheet resistance of one copper seed sample wafer was measured twice daily
for a period of 14 days. The four-point probe method was used to conduct resistivity
measurements using a 194mm test diameter. Five concentric rings equaling 121 test sites
were measured on each wafer, and the average was recorded. Figure 4-13 shows a plot of
the sheet resistance of the copper surface over time. It was expected that the sheet
resistance would increase over time indicating a contamination layer. However, within
80
the first 100 hours the sheet resistance decreases from l71 to 167 mohms/sq, and then
begins to level out at 165 mohms/sq.
The decrease in sheet resistance of copper has been previously87,88 associated with
a decrease in grain boundary volume. The decrease in grain boundary volume is due to
grain growth during room temperature recrystallization of the copper film. Any sheet
resistance effects caused by a contamination layer could easily be confounded with selfannealing of copper, making sheet resistance measurements an inefficient method to
discern copper seed aging effects.
Sheet Resistance (mohms/sq)
171
170
169
168
167
166
165
0
50
100
150
200
250
300
350
Aging Time (hrs)
Figure 4-13. Copper Seed Sheet Resistance Over Time
Summary and Discussion
Defects after Electroplating
A systematic study of the defects attributed to copper electroplating revealed that
the most common defect type is the “embedded” defect. Of concern, were void and pit
defects, which left the metal interconnects void of copper following chemical mechanical
polishing. Other authors45-48,89 have noted the same defect types following copper
electroplating.
81
However, when copper seed wafers are left in a cassette at room temperature
conditions and then plated after some delay time the defect count and type did not match
the results of the systematic defect study. The overall defect count increased drastically
due to the delay time between PVD copper seed deposition and bulk copper deposition by
electroplating. When the defects were classified using a SEM, it was determined that the
increase in defect count was due to an increase in pits and voids which were often formed
into a “swirl” pattern which matched the arc of rotation of the wafer during
electroplating. J. P Lu et al.45 and T. Cacouris89 also identify the connection between seed
aging and post electroplating defects as being caused by a decrease in wettability of the
copper surface over time due to contamination. Parametric testing of vias at metal level
two indicate a 30% higher contact resistance for wafers which were plated on copper seed
wafers aged for five days versus newly deposited PVD copper seed wafers.
Seed Surface Characterization
To better understand the change in wettability of the surface over time, the
contact angle of one copper seed wafer was measured daily. The contact angle for a
newly sputter deposited copper seed wafer is about 40° as compared to a contact angle of
about 63° after fourteen days of seed aging. Similarly, J. P. Lu45 measured a contact angle
of 65° for a wafer, which was stored in a cassette for 12 days. An increase in contact
angle suggests a decrease in surface wettability. If the surface is not completely wetted by
the electrolyte during electroplating, then the copper deposition process will be hindered,
resulting in copper voids.
The reflectivity of copper seed wafers over time was measured to detect any
surface changes. The results indicate that the surface reflectivity is decreased over time
with respect to incident light wavelengths between 250-650nm. In addition, the surface
82
reflectivity of a copper seed wafer aged for 14 days is similar to a copper seed wafer with
a 30Å layer of copper oxide.
The optoacoustic spectrum of one copper seed wafer was also studied over time.
An increase is amplitude corresponding to the optical reflection coefficient is noted at 10
psec. The increase in amplitude indicates that the sound wave has encountered an
interface, such as an oxidation or contamination layer, and was reflected back to the
wafer surface causing a localized change in reflectivity.
The sheet resistance of one copper seed sample wafer was measured twice daily
for a period of 14 days. It was expected that the sheet resistance would increase due to the
build up of a contamination layer. However, a sharp decrease in resistivity was noted at
early times between 1 and 100 hours of seed aging. The sheet resistance results could be
confounded with the self-annealing of copper, and thus is not an adequate method for
discerning seed aging effects.
The results of this section show that the copper seed surface is changing over
time. The wettability of the surface is decreased, and as a result more pits and voids, due
to incomplete plating in areas of the wafer, are found post-electroplating. The effect of
the pits and voids are apparent by an increase in contact resistance. A critical time limit
between copper seed deposition and electroplating should be set to avoid adverse seed
aging effects. For those wafers, which are beyond the critical time limit, a copper seed
surface treatment is needed to return the wafer to its original surface condition.
CHAPTER 5
POST–ELECTROPLATING DEFECT IMPROVEMENT BY TREATMENT OF
COPPER SEED
Background
Four surface treatments just prior to electroplating were explored to promote
wetting thereby mitigating voids. The first treatment included a reduction of the copper
oxide film (formed over time on the copper seed layer as control wafers are exposed to
the clean room ambient) by hydrogen using a commercially available sputtering tool.
The second treatment involved reverse plating of the copper surface, prior to electrolytic
copper deposition. The third treatment involved rinsing the seed wafer surface with
electrolyte and spin-drying prior to bulk copper deposition. The fourth treatment utilizes
a single wafer-cleaning tool with a proprietary chemical to remove organic and oxide
materials.
Copper Oxide Reduction
The copper oxide reduction by hydrogen was completed in a commercially
available physical vapor deposition tool. Plasma containing hydrogen molecules and an
inert gas was formed above the wafer surface. The hydrogen molecules dissociate and
diffuse to the wafer surface where oxide reduction takes place. The reactions occurring
at the wafer surface are described below:
Cu 2 O + 2 H → 2Cu + H 2 O
CuO + 2 H → Cu + H 2 O
83
84
Reverse Electroplating
The reverse electroplating treatment was carried out using a commercially
available electroplating tool. In this case, the copper wafer acted as the anode when
current was applied and the surface of the wafer dissolved leaving a fresh metallic copper
layer. The reaction at the wafer surface is as follows:
Cu ( s ) → Cu 2 + + 2e − → Cu ( s )
Copper Electrolyte Rinse
The electrolyte rinse treatment was performed in an electroplating tool. The
wafer was lowered into the acidic copper sulphate plating solution and rotated. The
intended reaction is as follows:
CuO + H 2 SO4 (l ) → CuSO4 + H 2 O(l )
Single Wafer Clean Tool
A proprietary chemical composed of triethanolamine (polymer removal) and
ammonium bifluoride (oxide removal) is utilized for the single wafer clean treatment.
The wafer is sprayed with the proprietary chemical while spinnnig at 1500 rpm inside an
enclosed process chamber. This chemical clean is currently used to remove residue on
copper left by the oxide etch process.
Experimental Results
Defect Characterization
Seventy-five wafers were deposited with 500nm CVD oxide layer followed by
sequential sputter deposition of 20nm of tantalum (barrier layer) and 200nm of copper
and stored in a cassette prior to copper electroplating. Following, copper seed deposition,
85
wafers were scanned and sorted for defects to ensure that only wafers with less than 30
defects (> 0.20µm) were utilized for this experiment.
Figure 5-1 displays a flowchart of the experimental design. Two wafers, which
served as a baseline for the experiment, were deposited immediately following PVD
copper deposition of the seed layer. The remaining fifty seed wafers resided in two
cassettes. After three days, ten wafers were removed from the cassette and distributed
into four treatment and one control (no treatment) category. Following treatment, the
wafers were randomized and electroplated. With the remaining forty wafers, this process
was repeated after 6, 9, 12, and 14 days of seed aging. Two wafers were always left
untreated to serve as a control. The single wafer treatment was omitted from day 6 and 9
of the experiment as tooling issues prevented use of the treatment. Following
electroplating, the total defect count was measured using the AITII and characterized
using a SEM.
Table 5-1 shows the resulting defect counts from the experiment. The left-most
column indicates the number of days the copper seed wafer resided in a cassette before
electroplating. The next column describes the defect count for copper seed wafers, which
were left un-treated and subsequently electroplated. The last four columns represent the
defect count following a treatment condition: copper oxide reduction, single wafer clean,
electrolyte rinse, and reverse plating applied to the wafer after seed aging. The control
group shows an increase in defect count from 58 to 550 over the fourteen-day aging
period. However, wafers treated by hydrogen reduction resulted in less than 70 postelectroplating defects over the same fourteen-day aging period. Wafers treated using any
of the methods described resulted in less than 135 (>0.25µm) electroplating defects.
86
Seed Aging
No Treatment
Treatment 1
Treatment 2
Treatment 3
Treatment 4
Electroplating
DAY 0
52 Wafers
Less than 30
defects
(>0.20um)
DAY 3
50 Wafers
DAY 6
40 Wafers
DAY 9
30 Wafers
DAY 12
20 Wafers
DAY 14
10 Wafers
Figure 5-1. Experimental Set-Up
Figure 5-2 shows a graph of the data described in Table 5-1. This figure shows
that the post-electroplating defect count on treated wafers remained stable in comparison
to control group wafers, which showed a steady rise in post-electroplating defects with
seed aging time. Figure 5-3 shows the final defect count from treated wafers only for
scaling purposes. From this graph, it is apparent that the hydrogen reduction treatment is
the most favorable for defect reduction post electroplating. Reverse electroplating,
electrolyte rinse and single wafer clean treatments have relatively the same results with
post-electroplating defects ranging from 40 to 135 over a fourteen-day period. The defect
87
results following treatment by reverse electroplating, electrolyte rinse, and single wafer
clean treatments still appear to be a function of seed aging with a rise in defects with
respect to seed aging time.
Table 5-1. Post-Electroplating Defect Count with Treated Aged Copper Seed Wafers
Day
Control
0
0
3
3
6
6
9
9
12
12
14
14
58
75
158
158
215
241
303
251
342
353
525
550
575
Single
Wafer
Clean
--50
65
----104
121
119
123
Electrolyte
Rinse
Reverse
Plating
--95
93
83
63
81
70
87
125
119
120
--86
81
66
60
51
75
93
103
122
134
Copper Oxide Reduction
Single Wafer Clean
Electrolyte Rinse
Reverse Plating
Control
525
475
425
Defect Count
Copper
Oxide
Reduction
--45
63
39
69
36
45
43
45
24
29
375
325
275
225
175
125
75
25
0
2
4
6
8
10
12
Number of Days Between Copper Seed Deposition and Plating
14
Figure 5-2. Post-Electroplating Defect Count of Aged Copper Seed Wafers
88
150
Copper Oxide Reduction
Single Wafer Clean
Electrolyte Rinse
Reverse Plating
Defect Count
125
100
75
50
25
0
2
4
6
8
10
12
Number of Days Between Copper Seed Deposition and Plating
14
Figure 5-3. Post-Electroplating Defect Count with Treated Aged Copper Seed Wafers
Figure 5-4 displays the post-electroplating wafer defect maps from control group
wafers. The wafers were aged for 0, 3, 6, 9, 12, and 14 days before electroplating. As the
number of post electroplating defects increases with time, a pattern termed the “swirl”
pattern begins to develop. This is a series of voids that follows the arc of rotation of the
wafer during plating.
Day 0
58 Defects
Day 3
158 Defects
Day 6
215 Defects
Day 9
Day 12
Day 14
303 Defects
342 Defects
550 Defects
Figure 5-4. Post-Electroplated Wafer Defect Maps from Aged Control Wafers
89
Figure 5-5 shows the resulting defect maps for electroplated treated and control
wafers following three days of seed aging. All four treatments appear to exhibit a slightly
beneficial effect, reducing defect counts from 158 to less than 100.
Control Wafer
Reverse Plating
158 Defects
Single Wafer Clean
65 Defects
86 Defects
Electrolyte Rinse
Hydrogen Reduction
95 Defects
45 Defects
Figure 5-5. Post-Electroplated Wafer Defect Maps Following Three Days of Seed Aging
Figure 5-6 displays defect maps from seed wafers treated after nine days of seed
aging. The control wafer is drastically different from any of the treated wafers. In fact, a
swirl pattern has become apparent. The pattern is in the same rotational direction as the
wafer rotation during electroplating. Each of the treatments tested are beneficial at
removing post-electroplating defects.
Figure 5-7 displays defect maps from seed wafers treated following fourteen days
of seed aging. Again, the control wafer defect count is drastically greater than treated
wafer defect counts. The swirl pattern becomes more distinct as compared to the pattern
identified following nine days of seed aging. All methods of the treatment are capable of
preventing the swirl pattern of voids. However, the hydrogen reduction treatment appears
to be the most advantageous.
90
Control Wafer
Reverse Plating
303 Defects
75 Defects
Electrolyte Rinse
Hydrogen Reduction
70 Defects
36 Defects
Figure 5-6. Post-Electroplated Wafer Defect Maps Following Nine Days of Seed Aging
Figure 5-8 displays typical post-electroplating defects on treated wafers as well as
control wafers which were plated following three and fourteen days of seed aging. Not
only is there a significant decrease in void count following electroplating but also a
decrease in void size. The swirl effect noted in the fourteen-day aged wafer is also
eliminated by all four treatments methodologies.
Control Wafer
Reverse Plating
550 Defects
Single Wafer Clean
123 Defects
122 Defects
Electrolyte Rinse
119 Defects
Hydrogen Reduction
29 Defects
Figure 5-7. Post-Electroplated Wafer Defect Maps After Fourteen Days of Seed Aging
91
Post-Treatment Defects
3-Day Aged Control Wafers
14-Day Aged Control Wafers
Figure 5-8. Defect Examples from Treated and Control Wafers
Contact Angle Measurements
The contact angle was measured for wafers treated following the twelfth day of
seed aging. The results are compiled into table 5-2 and graphically displayed in figure 59. The columns titled edge 1, center, and edge 2 indicate the wetting angle measured on
the top edge, middle, and bottom edge of the wafer. The contact angle measurements
from a newly sputter deposited seed wafer as well as an untreated wafer aged for fourteen
days is included for comparison. The treated wafers show a significantly lower contact
angle than the aged seed wafer. The copper oxide reduction treated wafers have the same
surface wetting condition as a freshly deposited seed wafer. Wafers treated by electrolyte
rinse, reverse plating, and single wafer treatment result in a wetting angle of 44-48°,
indicating a slightly more hydrophobic surface than newly deposited wafers. This
corresponds with the defect results post-electroplating which are also slightly higher for
treated wafers than newly sputtered seed wafers.
92
Table 5-2. Contact Angle Measurement Results for Treated Wafers
Treatment
Edge 1
Center
Edge 2
Control: Day 0
39.0
40.0
41.0
Copper Oxide
Reduction
42.5
40.0
42.0
Electrolyte Rinse
44.0
47.0
47.0
Reverse Plating
49.0
48.0
47.5
Single Wafer
Treatment
47.0
46.0
46.5
Control: Day 14
62.0
62.5
63.0
65
Edge 1
Center Point
Edge 2
60
Contact Angle °
55
50
45
40
35
Control: Day 0 Copper Oxide
Reduction
Electrolyte
Rinse
Reverse Plating
Single Wafer Control: Day 14
Treatment
Treatments
Figure 5-9. Contact Angle Measurement Following Wafer Treatment
Spectrometry of Treated Aged Seed Wafers
Following the twelfth day of seed aging, each of the four separate treatments was
applied to four individual wafers. The reflectance measurement was made at the center
point of the wafer. The wavelength of incident light was increased in 4 nm increments
from 250-650 nm. The reflectance was measured at each of these increments.
93
A graph of the lower and higher incident light wavelengths is constructed to show
the reflectivity of the copper wafer with respect to the individual treatment applied.
Figure 5-10 shows the reflectance of treated wafers with incident light wavelengths
ranging between 250-350 nm. The wafer treated by hydrogen reduction of copper oxide
is the most highly reflective wafer, followed by wafers treated by the electrolyte rinse and
single wafer clean. The reverse plated wafer has the same reflectivity as the original
reflectivity of the 12-day aged copper wafer.
12-Day Aged Wafer
Copper Oxide Reduction
Reverse Plate
Electrolyte Rinse
Single Wafer Clean
Reflectivity
0.73
0.63
0.53
0.43
250
300
Wavelength (nm)
350
Figure 5-10. Reflectivity of Treated Wafers with Incident Light 250-350nm Wavelength
Figure 5-11 shows the spectra of treated wafers in comparison to the 12-day aged
wafer for higher wavelength incident light between 500-550 nm. Again, the wafer treated
by hydrogen reduction of copper oxide is the most highly reflective wafer, followed by
wafers treated by the electrolyte rinse and single wafer clean. The reverse plate treatment
has a lower reflectivity than the 12-day aged copper wafer measured as a control for the
experiment.
94
The reflectivity measurements directly correspond to the defect results, which
show that hydrogen reduction of copper oxide is the most effective treatment for
reduction of post-electroplating defects. As expected, the electrolyte rinse and single
wafer clean treatment result in reflectivity which is higher than the control wafer but
lower than the hydrogen reduction treated wafer. However, while the reverse
electroplating treatment is effective at minimizing post-electroplating defects the
reflectivity is lower than for the 12-day aged control wafer.
Reflectivity
1.74
12-Day Aged Wafer
Copper Oxide Reduction
Reverse Plate
Electrolyte Rinse
Single Wafer Clean
1.64
1.54
500
520
Wavelength (nm)
540
Figure 5-11. Reflectivity of Treated Wafers with Incident Light 500-550nm Wavelength
Opto-Acoustic Spectra of Treated Aged Seed Wafers
The opto-acoustic spectra of wafers aged for 12 days and then treated was
measured to discern surface changes and identify any changes in copper thickness
resulting from wafer treatment. Figure 5-12 shows the opto-acoustic spectra from a
copper seed wafer aged 12 days and then measured again on the same wafer following
electrolyte rinse treatment. The spectra have been overlaid as a comparison to identify
any significant deviations. At approximately 10 picoseconds, a difference in the change
95
in reflectivity is noted. Following treatment, only a slight change in reflectivity is noted.
The larger amplitude prior to treatment indicates the sound wave has encountered an
interface, such as an oxidation or contamination layer, and was reflected back to the
wafer surface causing a localized change in reflectivity. However, in the case of the
electrolyte rinse treated wafer, the spectrum is nearly flat at 10 psec indicating that an
interface is not encountered. This suggests that the surface condition is improved.
Figure 5-12. Opto-Acoustic Spectra from Electrolyte Rinse Treatment
Figure 5-13 and figure 5-14 display the overlay of optoacoustic spectra from a
copper seed wafer aged 12 days then measured again following single wafer clean and
copper oxide reduction treatments, respectively. At approximately 10 picoseconds, a
difference in the change in reflectivity between the two spectrums is noted. As in the
case for the electrolyte rinse, the reflectivity change following treatment is no longer
noted. The spectrum becomes flat over the first twenty-five picoseconds. In fact, for these
two treatments the change in reflectivity is closer to zero than for the electrolyte rinse
96
treated wafers. Again this suggests that a contamination interface is not encountered and
the surface condition is improved following treatment.
Figure 5-13. Opto-Acoustic Spectra from Single Wafer Clean Treatment
Figure 5-14. Opto-Acoustic Spectra from Copper Oxide Reduction Treatment
Lastly, figure 5-15 displays the overlay of opto-acoustic spectra from a copper
seed wafer aged 12 days then measured again following reverse electroplating treatment.
Following treatment, the spectrum appears to be shifted to the left. This indicates that the
copper layer is thinner than prior to reverse plating. For the 12-day aged wafer, prior to
97
treatment, a change in reflectivity is noted at 62 picoseconds indicating that the sound
wave has reflected off of the copper seed-barrier layer interface. The copper seed layer
thickness, t, can be determined from the observed oscillatory behavior of reflectivity
change with period, τ, by
t=
vτ
2
where v is the velocity of sound. The period, τ, is approximately 62 picoseconds and the
velocity of sound in copper is 52.5 Å per picosecond. From this information the copper
seed layer thickness is calculated as follows:
t=
62 ps * 52.5Å / ps
= 1627 Å of Cu
2
Following the reverse plating treatment the sound wave encounters the copper
seed-barrier layer interface at 57.2 picoseconds. Therefore, the copper seed layer
thickness can be calculated as follows:
t=
57 ps * 52.5Å / ps
= 1496Å of Cu
2
The reverse plating treatment causes a 130Å loss of copper seed. In addition, the
amplitude of change in reflectivity measured at ten picoseonds remains the same before
and after treatment unlike in the cases of the other treatments.
Table 5-3 shows the thickness of the 12-day aged copper seed control wafer as
well as for treated wafers, as measured by their optoacoustic spectrum. Wafers treated by
98
the electrolyte rinse, copper oxide reduction, and single wafer clean do not exhibit a
significant change in thickness. However, as discussed previously, wafers treated by
reverse plating have a 130Å decrease in copper seed following treatment.
Figure 5-15. Opto-Acoustic Spectra from Reverse Plate Treatment
Table 5-3. Thickness Results following Wafer Treatment
Single
Electrolyte
Wafer
Control
Rinse
Clean
Thickness (Å)
1634
1625
1630
Copper
Oxide
Reduction
1627
Reverse
Plate
1496
Sheet Resistance
The sheet resistance of wafers aged for 12 days and then treated was measured to
discern surface changes and identify any changes in copper thickness resulting from the
treatment. The sheet resistance of each wafer was measured using the four-point probe
method and a 194mm test diameter. Five concentric rings equaling 121 test sites were
measured on each wafer both pre and post wafer treatment, and the average was recorded
and is displayed in table 5-4.
99
The sheet resistance change for both pre and post wafer treatment for the
electrolyte rinse, single wafer clean, and copper oxide reduction is unremarkable.
However, in the case of the reverse plate treatment, the post treatment sheet resistance
results is higher than prior to treatment. This is due to the decrease in thickness of the
copper film which is related to the sheet resistance as follows:
ρ
Rs =  
t 
Therefore, as the thickness is decreased the sheet resistance is increased proportionally.
Table 5-4. Sheet Resistance Results following Wafer Treatment
Copper
Single
Electrolyte
Oxide
Wafer
Rinse
Reduction
Clean
PreTreatment
0.16758
0.16666
0.16679
(mohms/sq)
Post
Treatment
0.16788
0.16787
0.16637
(mohms/sq)
Reverse
Plate
0.16742
0.19933
Discussion
The post-electroplating defects for wafers plated following one versus fourteen
days of seed aging increases by five orders of magnitude. All four treatments applied
were advantageous in significantly reducing defect counts and eradicating the “swirl”
defect. The copper oxide reduction by hydrogen plasma proved to be the most useful
treatment, maintaining defects at their original defect level prior to seed aging.
In addition to the treatments employed in this section, other researchers,90-91 have
tried laser removal of oxide from copper. They found that successful oxide removal was
achieved at 1064, 532, and 266nm of a Q-switched Nd : YAG radiation laser. Jae Jeong
100
Kim et al.81 was successful at removing copper oxide films using a wet cleaning mixture
of 1:200 NH4OH and coulometric reduction. In addition, organic inhibitors of copper
corrosion are being utilized to prevent the growth of copper oxide.92-93 However, none of
these researchers tested the efficacy of their treatment with respect to post-electroplating
copper defects. A follow-up study should include treatments of these types as a
comparison for the improvement of post-electroplating defects.
The copper seed surface shows a decrease in wettability over time by an increase
in contact angle from 40 to 63° over a fourteen day period. The contact angle after
hydrogen reduction treatment of a twelve-day aged copper wafer is 42° as compared to
the contact angle following reverse plating, electrolytic rinse and single wafer treatment
which are about 48-50°. This indicates that a greater degree of wetting results after
hydrogen reduction treatment versus any other treatment.
In addition to the increase in wettability of the aged copper surface following
hydrogen reduction treatment, an increase in reflectivity is also noted. Again, the
hydrogen reduction treatment increases the surface reflectivity to a greater degree than
any of the other treatments. This indicates that the surface contaminants are removed
from the copper surface leaving a pristine copper layer.
A change in the optoacoustic spectra, obtained by capturing surface reflectivity,
changes caused by a traveling soundwave, is noted on aged versus treated copper wafers.
Wafers, which were treated, exhibit a smaller amplitude or smaller change in reflectivity
than wafers left untreated. The largest reduction in amplitude is noted for wafers treated
by hydrogen reduction treatment. Again, a change in amplitude indicates that a
101
soundwave has encountered a contaminated interface. Therefore the surface is improved
following treatment.
In addition to information about the surface condition of treated wafers, the
optoacoustic spectra shows that copper was not removed from surfaces treated by
hydrogen reduction, electrolyte treatment, and the single wafer treatment. However, the
reverse plating treatment, as expected, removed about 130Å of copper as can be noted
noted by an overall shift in the optoacoustic spectra. In addition, only the reverse plate
treatment appears to affect the sheet resistance measurements. The reverse plating
treatment increases the sheet resistance due to the removal of copper.
To better understand the affects of the treatments on the sputtered copper surface,
this study should be followed by an evaluation of the films using surface analytical
techniques to obtain a fundamental understanding of barrier/seed and electroplated
copper film behavior as a function of time and treatment. In addition, films with known
copper oxide thickness should be treated to determine which treatment is most effective.
CHAPTER 6
CONCLUSION
When copper seed wafers are left in a cassette at room temperature and then
plated, after a delay time between process steps, the defect count and type are drastically
different from wafers, which were immediately electroplated following PVD copper seed
deposition. The overall defect count is significantly increased due to the delay time
between PVD copper seed deposition and bulk copper deposition by electroplating. When
the defects were classified using a SEM, the increase in defect count was found to be due
to an increase in pits and voids formed a “swirl” pattern, matching the arc of rotation of
the wafer during electroplating.
The copper voids were postulated to be due to a lack of wetting of the electrolyte
on the copper seed surface. The plating solution must wet the seed surface uniformly
during copper plating initiation. Any incomplete wetting of the surface by the electrolyte
can result in the absence of plating in that area. In addition to the decrease in wettability,
copper oxide formation or any contamination of the wafer surface can cause poor
electrical conduction. A localized decrease in electrical conduction, or current carrying
capability of the seed layer, can cause void formation during the electroplating process.
To better understand the change in wettability of the surface over time, the contact
angle of one copper seed wafer was measured daily. The contact angle for a newly sputter
deposited copper seed wafer is about 40° as compared to a contact angle of about 63°
after fourteen days of seed aging. An increase in contact angle suggests a decrease in
surface wettability. The reflectivity of copper seed wafers was also found to decrease
102
103
over the same fourteen-day aging period with respect to incident light wavelengths
between 250-650nm. Opto-acoustic spectrum changes were monitored over time. A
reflectivity change, dependent on an traveling sound wave, corresponds to an oxidation or
contamination layer. This change became more apparent over a 14-day aging period.
The post-electroplating defects for wafers plated following one versus fourteen
days of seed aging increases by five orders of magnitude. However, all four treatments
applied were advantageous in significantly reducing the defect count and eradicating the
“swirl” defect. The copper oxide reduction by hydrogen plasma proved to be the most
useful treatment, maintaining defects at their original defect level prior to seed aging.
The copper seed surface shows a decrease in wettability over time by an increase
in contact angle from 40 to 63° over a fourteen day period. The contact angle after
hydrogen reduction treatment of a twelve-day aged copper wafer is 42° as compared to
the contact angle following reverse plating, electrolytic rinse and single wafer treatment
which are about 48-50°. This indicates that a greater degree of wetting results after
hydrogen reduction treatment versus any other treatment.
In addition to the increase in wettability of the aged copper surface following
hydrogen reduction treatment, an increase in reflectivity is also noted. Again, the
hydrogen reduction treatment increases the surface reflectivity to a greater degree than
any of the other treatments. This indicates that the surface contaminants are removed
from the copper surface leaving a pristine copper layer.
A change in the optoacoustic spectra, obtained by capturing surface reflectivity
changes caused by a traveling soundwave, is noted on aged versus treated copper wafers.
104
Wafers, which were treated, exhibit a smaller amplitude or smaller change in
reflectivity than wafers left untreated. The largest reduction in amplitude is noted for
wafers treated by hydrogen reduction treatment. Again, a large amplitude indicates that a
soundwave has encountered a contaminated interface. Therefore the surface is improved
following treatment.
In addition to information about the surface condition of treated wafers, the
optoacoustic spectra shows that copper was not removed from surfaces treated by
hydrogen reduction, electrolyte treatment, and the single wafer treatment. However, the
reverse plating treatment, as expected, removed about 130Å of copper as can be noted
noted by an overall shift in the optoacoustic spectra. In addition, only the reverse plate
treatment appears to affect the sheet resistance measurements. The reverse plating
treatment increases the sheet resistance due to the removal of copper.
The hydrogen reduction treatment appears to be the most advantageous treatment
for reducing post-electroplating defects. It has been proven to increase the wettability of
the copper surface as well as increase the copper reflectivity. Although all four treatments
applied were successful at removing post-electroplating defects, the reverse plating
treatment has negative effects, which include a decrease in reflectivity and copper
thickness, and an increase in sheet resistance. If copper is removed from the bottom and
sidewalls of vias during the reverse plating process, this will cause insufficient coverage
for the subsequent copper deposition by electroplating.
Applying any of the tested treatments to wafers, processed in a batch and stored
for a period of time, prior to use as a process monitoring aid, is critical to prevent
105
confounding of intrinsic process defects from those induced externally by seed aging
effects.
LIST OF REFERENCES
1. Quality Metal Finishing Guide 1, No. 1-B "Decorative Precious Metal Plating,"
Metal Finishing Suppliers Association, Potomac Falls, Virginia, 206 (1998).
2. D.C. Edelstein, Electron Devices Meeting, 1997 Technical Digest, Proceedings of
the IEEE, Washington, DC, 773–76 (1997).
3. S. Ventakesan, AV Gelatos, V. Misra, B. Smith, and R. Islam, Electron Devices
Meeting, 1997 Technical Digest, Proceedings of the IEEE International,
Washington, DC, 769 (1997).
4. J. Lu, L. Chen, D. Gonzalez, H.L. Guo, and D.J. Rose, Interconnect Technology
Conference, Proceedings of the IEEE 2001 International, Burlingame, California,
280 (2001).
5. P.R. Morris, A History of the World Semiconductor Industry, Peter Peregrinus
Ltd, New York, 52 (1990).
6. Subash Mahajan and K.S. Sree Harsha, Principles of Growth and Processing of
Semiconductors, McGraw-Hill, Boston, 165-66 (1999).
7. Stephen A. Campbell, The Science and Engineering of Microelectronic
Fabrication, Oxford University Press, New York, 7-9 (1996).
8. S. Wolf and R. Tauber, Silicon Processing for the VLSI Era, Lattice Press,
California, 330-335 (1986).
9. S. Bothra, Subhas, Pramanik, and Dipu, Solid State Technology 40, 77 (1997).
10. S. Muraka, VLSI Technology, McGraw-Hill, New York, 375 (1988).
11. D. Pramanikm and V. Jian, Solid State Technology 21, 73 (1993).
12. C.A. Martin, J.C. Ondrusek, and J.W. McPherson, Reliability Physics
Symposium, 1990. 28th Annual Proceedings, IEEE International, New Orleans,
Louisiana, 31-36 (1990).
13. P. Riley, S. Peng, and L. Fang, Solid State Technology 13, 47 (1993).
14. J. Aronson, Microelectronics Manufacturing and Testing 7, 22 (1987).
106
107
15. Kasturi L. Chopra, Thin Film Phenomena, Krieger Publishing Company, New
York, 52 (1979).
16. J. Baliga, Semiconductor International 20, 80 (1997).
17. M. Biberger, S. Jackson, G. Tkach, J. Schlueter, B. Jones, C.K. Huang, and Luc
Ouellet, Thin Solid Films 270, 522-525 (1995).
18. Dipankar Pramanik and Arjun Saxena, Solid State Technology 33, 73-79 (1990).
19. S. Q. Wang, MRS Bulletin 8, 30 (1994).
20. Stephen A. Campbell, The Science and Engineering of Microelectronic
Fabrication, Oxford University Press, New York, 410-411 (1996).
21. F. Braud, G. Tartavel, J. Palleau, J. Torres, A. Persico, and G. Reimbold, Quality
and Reliability Engineering International 12, 305-308 (1996).
22. J.R. Black, IEEE Trans. Electron. Dev. 16, 338 (1969).
23. S. Dietrich, M. Schneegans, M. Moske, and K. Samwer, Thin Solid Films 275,
159-163 (1996).
24. DC Edelstein, GA Sai-Halasz, and Y-J. Mii, IBM J. Res. Dev. 39, 383 (1995)
25. C-K Hu, KY Lee, C. Uzoh, K Chan, and S Rossnagel, Proc. Mater. Res. Soc.
Symp., 507 (1998).
26. K. Wakasugi, M. Tokunaga, T. Sumita, H. Kubota, M. Nagata, and Y. Honda,
Physica B. 239, 29 (1997).
27. James A. Cunningham, Semiconductor International 22, 97-99 (May 2000).
28. Peter Singer, Semiconductor International 20, 79-80 (August 1997).
29. Ruth DeJule, Semiconductor International 23, 94-96 (June 2000).
30. Shi-Qing Wang, Ivo Raaijmakers, Brad J. Burrow, Saliesh Suthar, Shailesh
Redkar, and Ki-Bum Kim, J. Appl. Phys. 68 (10), 521-22 (November 1990).
31. Shi-Qing Wang, MRS Bulletin 8, 98 (1994).
32. J. M. Poate, K. N. Tu, and J. W. Mayer, Thin Film—Interdiffusion and Reactions
Wiley & Sons, New York, 376 (1978).
33. Jon Reid, Steve Mayer, Eliot Broadbent, Erich Klawuhn, and Kaihan Ashtiani,
Solid State Technology 43, 86-88 (July 2000).
108
34. W.H. Li, J. H. Ye, and S.F.Y. Li, Journal of Applied Electrochemistry 31, 139597 (December 2001).
35. Allen J. Bard and Larry R. Faulkner, Electrochemical Methods: Fundamentals
and Applications, John Wiley & Sons, New York, 2nd edition, 5-40 (December
2000).
36. Rolf E. Hummel, Understanding Materials Science, Springer-Verlag, New York,
159-160 (1998).
37. Kobayashi, A. Sano, H. Akahoshi, T. Itabashi, T. Haba, S. Fukada, and H.
Miyazaki, IITC Conference, 34–36 (2000).
38. P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, J. Res.
Dev. 42, 567 (1998).
39. S. Y. Chiu, J. M. Shieh, S. C. Chang, K. C. Lin, B. T. Dai, C. F. Chen, and M. S.
Feng, J. Vac. Sci. Technol. B 18, 2835 (2000).
40. C. Ogden and D. Tench, Plating & Surface Finishing 66, 30 (September 1979).
41. J. Reid, PC Fab, 10, 65 (November 1987).
42. Jon Reid, Steve Mayer, and Eliot Broadbent, Journal of Solid State Technology,
512 (July 2000).
43. T.C. Franklin, Surface and Coatings Technology 30, 415 (1987).
44. L. Oniciu and L. Muresan, Journal of Applied Electrochemistry 21, 565 (1991).
45. J.P. Lu, L. Chen, D. Gonzalez, H. L. Guo, D.J. Rose, M. Marudachalam, W.Y.
Hsu, H.Y. Liu, F. Cataldi, B. Chatterjee, P.B. Smith, P. Holverson, R.L. Guldi,
N.M. Russell, G. Shinn, and S. Zuhoski, Proc. IEEE-IITC, 280 (2001).
46. S. Parikh, J. Educato, J. Wang, B. Zheng, K. Wijekoon, J. Chen, V. Rana, R.
Cheung, and G. Dixit, 2001 Interconnect Technology Conference, Proceedings of
the IEEE 2001 International, 183-185 (2001).
47. Minseok Oh, Deepak A. Ramappa, Daniele Contestable-Gilkes, Sailesh
Merchant, Douglas E. Jones, Karthikeyan Subramanian, Steve Lytle, and Isaiah
Oladeji, Advanced Metallization Conference (AMC), 85-89 (2001).
48. Richard L. Guildi, Judy B. Shaw, Jeffry Ritchison, Steve Oesterich, Kara Davis,
and Robert Fiordalice, IEEE International Symposium on Semiconductor
Manufacturing Conference, 351-355 (2002).
49. H. K. Liou, J.S. Huang, and K.N. Tu, Journal of Applied Physics 77, 5443 (1995).
109
50. A. J. Griffen, S.E. Hernandez, and F.K. Brotzen, Journal of Electrochemical
Society 141, 807 (1994).
51. N. Cabrera and N.F. Mott, Rep. Prog. Phys. 12, 163 (1948).
52. I. Ishikawa, Thin Film Solids 281-282, 117-119 (1996).
53. A.T. Fromhold Jr., Theory of Metal Oxidation, Vol. 1 Fundamentals, NorthHolland Publishing Company, Amsterdam (1976).
54. M. Martin and E. Fromm, Journal of Alloys and Compounds 258, 7-16 (1997).
55. S.Y. Liem, G. Kresse, and J.H.R. Clarke, Surface Science 415, 194-200 (1998).
56. J. Buisset, H.-P. Rust, E.K. Schweizer, L. Cramer, and A.M. Bradshaw, Surface
Science 349, 147 (1996).
57. M. Kittel, M. Polcik, R. Terborg, J.-T. Hoeft, P. Baumgartel, and A.M. Bradshaw,
Surface Science 470, 311-324 (2001).
58. M. O’Reilly, Applied Surface Science 91, 152-156 (1995).
59. G. Schwalbe , J. Baumann , C. Kaufmann , T. Gessner , H. Koenigsmann ,A.
Bartzsch, and P. Gilman, Microelectronic Engineering 55, 341-348 (2001).
60. N.D. McCusker, H.S. Gamble, and B.M. Armstrong, Microelectronics Reliability
40, 69-76 (2000).
61. WM Kuschke, A Kretschmann, and RM Keller, Journal of Materials Research 13,
2962-8 (1998).
62. Hoo-Jeong Lee, Kee-Won Kwon, Changsup Ryu, and Robert Sinclair, Acta
mater. 47, 3965-3975 (1999).
63. S.-Y. Lee, S.-H. Choi, and C. O. Park, Thin Film Solids 359, 261-267 (2000).
64. J. McDonnell and D.P. Woodruff, Surface Science 46, 505 (1974).
65. F. Besenbacher and J.K. Norskov, Progressive Surface Science 44, 1243 (1993).
66. S.M. Thurgate and P.J. Jennings, Surface Science 131, 309 (1983).
67. T. Matsumoto, R.A. Bennett, P. Stone, T. Yamada, K. Domen, and M. Bowker,
Surface Science 471, 225-245 (2001).
68. F. M. Chua, Y. Kuk, and P. J. Silverman, Physics Review Letters 63, 1575
(1989).
110
69. D. Coulmann, J. Wintterlin, R. J. Behm, and G. Wertl. Physics Review Letters 64,
1761 (1990).
70. F. Jensen, F. Besenbacher, E. Laesgaard, and I. Stensgaard, Physics Review
Letters 41, 1223 (1990).
71. P.C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, IBM
Journal of Research and Development 42, 567 (1998).
72. K.E. Huester, Silikat Journal 15, 350 (1976).
73. R.R. Dogonadze, A.M. Kuznetsov, and J Ulstrup, Electrochim. Acta 22, 967
(1977).
74. Akira Furuya, Masayoshi Tagami, Kazutoshi Shiba, Kuniko Kikuta, and
Yoshihiro Hayashi, IEEE Transactions on Electron Devices 49-50, 733-739
(2002).
75. R.E. Thomas, M.J. Mantini, R.A. Rubber, D.P. Malta, S.V. Hattangady, and R. J.
Markunas, Journal of Vacuum Science and Technology 10, 817 (1992).
76. R. Kroor, Japanese Journal of Applied Physics 36, 5068 (1997).
77. J. E. Parmeter, R.J. Shul, A.J. Howard, and P.A. Miller, Journal of Vacuum
Science and Technology B 14, 3563 (1996).
78. T. Belmonte, J. M. Thie´ baut, H. Michel, R. P. Cardoso, and A. Maliska, Journal
of Vacuum Science Technology A 20 (4), 1347-51 (2002).
79. Z. Falkenstein, M. Hakovirta, and M. Nastasi, Thin Solid Films 381, 84-87
(2001).
80. Woong Park and Chongmu Lee, Materials Science and Engineering B 85, 80-84
(2001).
81. Jae Jong Kim and Soo-Kil Kim, Applied Surface Science 183, 311-318 (2001).
82. T.C. Chang, Y.S. Mor, P.T. Liu, S.M. Sze, Y.L. Yang, M.S. Tai, and C.Y. Chang,
Thin Solid Films 355-56, 451-455 (1999).
83. E. Klawuhn, G. C. D’Couto, K. A. Ashtiani, P. Rymer, M. A. Biberger, and K. B.
Levy, J. Vac. Sci. Technol. A 18 (4), 1546-1549 (2000).
84. Zhehui Wang and Samuel A. Cohen, J. Vac. Sci. Technol. A 17, 77 (1999).
85. S. Wilson, C. R. Brundle, and C. Evans, Encyclopedia of Materials
Characterization: Surfaces, Interfaces, Thin Films, Butterworth-Heinemann, New
York (1985).
111
86. H. Maris, Scientific American 278, 64-67 (1998).
87. C.-K. Hu, R. Rosenberg, and K.Y. Lee, Appl. Phys. Lett. 74, 2945 (1999).
88. D. Walther, M.E. Gross, K. Evans-Lutterodt, W. L. Brown, M. Oh, S. Merchant,
and P. Naresh, MRS Symposium, 514 (Spring 2000).
89. Ted Cacouris, Sesha Varadarajan, and Dinesh Kalakkad, SEMICON,
Semiconductor Equipment and Materials International, Taiwan (2001).
90. A. Kearns, C. Fischer, K.G. Watkins, M. Glasmacher, H. Kheyrandish, A. Brown,
W.M. Steen, and P. Beahan, Applied Surface Science 127–129, 773–780 (1998).
91. S.M. Bedair, H.P. Smith, J. Appl. Phys. 40 (12), 4776 (1969).
92. G. P. Cicileoa, B.M. Rosalesa, F.E. Varelab, and J.R. Vilcheb, Corrosion Science
30, 1359-1375 (1999).
93. E.Szocsi, G.Vastag, A.Shaban, G. Konczos, and E. Kalman, Journal of Applied
Electrochemistry 29, 1339-1345 (1999).
BIOGRAPHICAL SKETCH
Daniele Gilkes was born in Piscataway, New Jersey. She attended Winter Park
High School in Florida. Following high school, she attended the University of Florida,
obtaining a Bachelor of Science in Chemical Engineering in December 1999. After
graduation, she had the opportunity to work in research and development at Bell
Laboratories. Her main interest at Bell Laboratories was copper electroplating process
development for metal interconnect fabrication. During this time, she began her work
towards a Master of Science in materials science and engineering through the University
of Florida’s Educational Delivery System, FEEDS. She incorporated a project intended to
eradicate defects found in copper films as part of her research towards a Master of
Science under the supervision of Dr. David Norton. Her work was undertaken to try to
further the understanding of new processes that are integral to the future of
semiconductor development.
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