CPSC 313 Sample Test 1 Summer 2011 Name: Signature: Student ID: – You have 40 minutes to write the 4 questions on this examination. A total of 25 marks are available. – No notes, books or electronic devices are allowed. – Justify all of your answers. – Keep your answers short. If you run out of space for a question, you have written too much. – The number in square brackets to the left of the question number indicates the number of marks allocated for that question. Use these to help you determine how much time you should spend on each question. Question Marks 1 2 3 4 Total – Use the back of the pages for your rough work. – Good luck! UNIVERSITY REGULATIONS: – Each candidate should be prepared to produce, upon request, his/her library card. – No candidate shall be permitted to enter the examination room after the expiration of one half hour, or to leave during the first half hour of the examination. – CAUTION: candidates guilty of any of the following, or similar, dishonest practices shall be immediately dismissed from the examination and shall be liable to disciplinary action. 1. Having at the place of writing, or making use of, any books, papers or memoranda, electronic equipment, or other memory aid or communication devices, other than those authorised by the examiners. 2. Speaking or communicating with other candidates. 3. Purposely exposing written papers to the view of other candidates. The plea of accident or forgetfulness shall not be received. – Candidates must not destroy or mutilate any examination material; must hand in all examination papers; and must not take any examination material from the examination room without permission of the invigilator. page 2 out of 4 [6] 1. Consider the following Y86 Assembly-language program: .pos 0x12345676 xorl %edx, %edx here: mrmovl here(%edx), %esi halt What value will be in register %esi once the program terminates? If you need them, you can find the numbers of each register and the instructions’ encodings on the last page of the test. Justify your answer. [3] 2. The sequential Y86 implementation discussed in class has Fetch, Decode, Execute, Memory, Write-back and PC-update stages, in this order. List one Y86 instruction that could not be executed if the Write-back stage came before the Memory stage, and explain why. [4] 3. In the sequential Y86 implementation discussed in class and drawn on the last page of this test, most of the rounded rectangles (for instance, those labeled dstE, dstM, aluA, aluB, Addr and Data) are multiplexers. (a) Where does the select signal (the signal that determines which one of the inputs becomes the output) come from? (b) How is each multiplexer implemented in the Java simulator? page 3 out of 4 [12] 4. Accessing an array requires both a pointer to the first element of the array, and the array index (or the difference in addresses between the element we want to access and the first element). One instruction that might be useful for that purpose would be an instruction like dmrmovl (rA, rB) whose semantics is R[rB] ← M4 [R[rA] + R[rB]] Suppose that this instruction’s memory format is 0 C 0 1 rA rB (a) Use the notation described in class (and the book) to document each stage’s role in implementing the instruction. That is, use the signal names (i.e., PC, valC, etc), and the notation R[x] for access to register number x and Mb [a] for access to b bytes of memory starting at address a. List the behaviour of each stage separately: Fetch, Decode, Execute, Memory, Write-back and PC-update. (b) This instruction would be even more useful if we could store the result in a register other than rA or rB (i.e. mrmovl (rA,rB), rX), and avoid clobbering either the array address or the index. Briefly describe the changes we would need to make to the design of our Y86 CPU to make such an instruction possible. page 4 out of 4 Register Names 0 %eax %esp 1 %ecx %ebp 2 %edx %esi 3 %ebx %edi 4 5 6 7 Instructions Encoding Byte halt nop rrmovl rA, rB cmovXX rA, rB irmovl V, rB rmmovl rA, D(rB) mrmovl D(rB), rA OPl rA, rB jXX Dest call Dest ret pushl rA popl rA 0 0 1 2 2 3 4 5 6 7 8 9 A B CPU hardware structure 1 0 0 0 fn 0 0 0 fn fn 0 0 0 0 rA rA F rA rA rA 2 3 rB rB rB rB rB rB V D D Dest Dest rA rA F F 4 5