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2. electronic components

DESIGNfeature
BY JOHAN STRYDOM PHD,
Director of Application Engineering, Efficient Power Conversion (EPC) Corporation
eGaN
N -Silicon Power Shoot-Out:
Comparing Figure of Merit (FOM)
TM
O
FOM (Figure-of-Merit) is a
useful method to compare
power devices and has been
used by MOSFET manufacturers to show both generational
improvements and competitive devices.
Drain
LD
Controller
Input
Gate
Driver
Gate
RG
CGD
CDS
CGS
LS
Source
Fig. 1. eGaN parasitic reactances
www.powerelectronics.com
ne yardstick to compare enhancement mode GaN (eGaN)
power devices with state-of-the-art silicon MOSFETs is FOM.
However, beyond these pure mathematical numbers, there are
other device and package related parameters that significantly
influence in-circuit performance. To compare devices we will
restrict ourselves to commercially available eGaN devices. We
shall also limit the MOSFET’s voltage range to between 40 and
200V as to make direct comparisons without extrapolation.
FOM is useful because no matter what the die size is, the FOM is almost constant
for a given technology or device generation (under certain assumptions). To understand the derivation of FOM, we have to look at the GaN’s parasitic reactances, as
shown in Fig. 1. In addition, we must identify the GaN’s parameters, which are listed
in Table 1. Now we can look at the two distinct FOMs:
1)Switching FOM (lower is better): For measuring switching performance (RDS(ON)
x QGD) is used as QGD plays a dominant role in switching loss, and it is impossible
to reduce this number without increasing RDS(ON) for a given technology. This is
considered a good measure of switching performance, although the use of QSW
W (QGD
+ QGS2) instead of QGD would be better, but these values are not always given in
datasheets.
2)Rectifier FOM (lower is better): This is the traditional MOSFET FOM, and determines rectifier performance in terms of conduction and gate drive power loss (RDS(ON)
x QG). For a “soft” switching device, where QGD is not important, you would like to
lower RDS(ON) to improve efficiency, but this increases QG and thereby increases gate
drive losses and overdrive time. It would be better to include QOSS and QRRR together
with QG for evaluating performance, but while RDS(ON) and QG have
reasonable standard conditions, QRRR has no standard, and is frequently
specified at unrealistic di/dt and current levels. Variation with conditions
is also absent from datasheets. QOSS is also omitted in many cases or
sometimes combined with QRR. Its conditions also do not have a standard
(eGaN transistors have no measurable QRR, and low QOSS per-unit-area
when compared with silicon MOSFETs, but have been omitted from this
analysis).
Of these two FOMs, the switching performance is more important in
Body
“hard switching” converter circuits. Fig. 2 plots RDS(ON) vs. QGD for eGaN
Diode
power transistors as well as for different equivalent silicon MOSFETs. We
can see that, based on switching FOM, the eGaN transistors offer a distinct advantage over any equivalent voltage rated silicon device, as shown
in some general observations:
•The 40V eGaN transistors are comparable to the current state of the
art 25V lateral silicon devices.
•For comparison, some original 100V devices from around the start of
theMOSFET revolution (circa~1980) are also included. These show that
September 2010 | Power Electronics Technology
23
GALIUMNITRIDEtransistors
FOMs as the best 100V silicon available today,
this is a very exciting prospect indeed!
100
The rectifier FOM is shown in Fig. 3 RDS(ON)vs.
QG for the eGaN power transistors as well as for
different equivalent silicon MOSFETs. From this
we can draw a number of conclusions:
10
• Although the improvement in conduction FOM
is not nearly as dramatic as for switching FOM, it
still delivered a 20X improvement over the last
40X in 30 years
25V Si
30 years. This lower increase in performance can
30V Si
be
explained by considering that the develop1
40V Si
100V Si
ment of technologies to improve the more criti200V Si
cal switching performance (such as trench) has
40V Si
Lower is better
caused a relative rise in input capacitance, which
100V EPC
adversely affects the rectifier FOM.
200V EPC
0.1
•eGaN power transistors show an even stronger
1
10
100
1000
Rdson (mOhm)
improvement over equivalent silicon devices.
•Zero QRRR and lower QOSS significantly favor
100V MOSFET FOM circa 1980 (~2000pC.Ohm)
Current 100V MOSFET FOM (~50pC.Ohm)
eGaN
transistors as well, but have been omitted
Current 200V MOSFET FOM (~400pC.Ohm)
Current 40V MOSFET FOM (~20pC.Ohm)
in this comparison as they are poorly characterized in silicon.
Although FOM is a useful tool for comparing
Fig. 2. RDS(ON) vs. QGD for different power transistors
switching power devices, there are a number of
other parameters of equal importance that also need to be
during the past 30 years of MOSFET improvement, the
considered. To discuss each of these in detail, they will be
switching FOM has gone down by a factor of 40! However,
divided into two sections:
as silicon is starting to approach its theoretical limits it
1) Device / Die related parameters
seems unlikely that the next 30 years will see a further 40X
2) Package related issues
improvement.
•In contrast though, it does seem likely that eGaN transistors will have a 40 times mprovement in an even smaller
DEVICE RELATED PARAMETERS
amount of time. With 200V devices already having similar
With synchronous rectification much of the traditional
diode conduction losses have been eliminated,
Conduction FOM
but there is a price to be paid for doing this.
100
Since the MOSFET must turn off before voltage
commutation, the body diode must also conduct
current for a small period of time. This in itself is
not that significant, but the MOSFET body diode
typically has very poor reverse recovery charac20X in 30 years
10
teristics (high QRR) that must now be recovered
once it has conducted current. Attempts to commutate the current to an external Schottky, or
25V Si
30V Si
other high performance diode, has been limited
1
40V Si
by the lack of commutation voltage (body diode
100V Si
forward drop), and the large loop inductance
200V Si
between the devices that limits the di/dt, and
40V Si
Lower is better
100V EPC
therefore lengthens the commutation time. This
200V EPC
can be partially overcome through cellular inte0.1
1
10
100
1000
gration of the Schottky or deliberate improveRdson (mOhm)
ment of the MOSFETís parasitic body diode.
Current 200V MOSFET FOM (~1400pC.Ohm)
100V MOSFET FOM circa 1980 (~4000pC.Ohm)
The actual extent of the QRRR losses is difficult to
Current 100V MOSFET FOM (~220pC.Ohm)
Current 40V MOSFET FOM (~90pC.Ohm)
predict and compare as datasheet test conditions
vary widely between parts and manufacturers.
Some example conditions and results are shown
Fig. 3. RDS(ON) vs. QG for different power transistors
Qg (nC)
Qg (nC)
Switching FOM
24
Power Electronics Technology
y | September 2010
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GALIUMNITRIDEtransistors
in Table 2. Note that higher initial current should result in a
much larger QRRR and reverse recovery time (tRR) values.
As seen in Fig. 4, EPCís eGaN transistor structure is a
lateral device, absent of the parasitic bipolar junction common to silicon MOSFETs. As such, body diode operation
has a different mechanism, but similar function. With zero
bias from gate to source, there is an absence of electrons
under the gate region (device is off). As the drain voltage is
decreased, a positive bias on the gate is created relative to
the drift region, injecting electrons under the gate. Once the
gate threshold is reached, there will be sufficient electrons
under the gate to form a conductive channel. The benefit
of this mechanism is that there are no minority carriers
involved in conduction, and therefore no reverse recovery
losses. As it takes a threshold voltage to turn on an eGaN
transistor in the reverse direction, the forward voltage of the
ëbody diodeí is higher than silicon transistors (about 1.8V
for a typical eGaN device1). As with silicon MOSFETs, care
should be taken to minimize body diode conduction.
the past, this loss component was negligible compared to the
actual switching loss, but, as device switching FOM keeps
improving, this component is becoming more important. In
fact, a few manufacturers (including EPC) are starting to add
typical QOSS numbers to their datasheets. Alternatively this
can be estimated by integrating the COSS vs. voltage curve.
In Fig. 5, the COSS vs. voltage for 100 V and 200 V eGaN
transistor and silicon MOSFETs is compared. (All devices
have been normalized to 25 mΩ). Since the area under the
curve is important, both the initial (near zero bias) value
and the final high bias value affect the total QOSS. Due to
the inherently smaller lateral structure, eGaN devices have
much lower initial COSS values. At high bias, however, COSS
does not drop away as quickly as with silicon. Overall, the
total QOSS losses are much lower than comparable silicon as
evident when plotting QOSS vs. voltage for the same devices
as in Fig. 6. At half rated voltage, the eGaN parts show
between two thirds and half the QOSS losses of comparative
90
80
During “hard” switching (device turning on with full bias
voltage across drain-source) of a half-bridge, energy equal
to that stored in the COSS of both devices is dissipated. In a
typical buck converter, one of the switching edges is “soft”
switching (device turn-on with no voltage across drain-source
while its own body diode is conducting prior to turn-on). In
Total Qoss charge (nC)
OUTPUT CAPACITANCE LOSSES
70
60
200V devices
50
40
30
100V devices
20
10
AlGaN Electron Generating Layer
0
0
Dielectric
40
60 80 100 120 140 160 180 200
Drain-Source Voltage (V)
D
G
S
20
100V
100V
100V
200V
GaN
Aluminum
Nitride
Isolation
Layer
Si
EPC1007 x 6/5
Scaled MOSFET A
Scaled MOSFET B
EPC1010
200V Scaled MOSFET C
200V Scaled MOSFET D
200V Scaled MOSFET E
Fig. 6. QOSS vs VDS normalized to 25 mΩ
Coss Capacitance (pF)
10,000
100V
100V
100V
200V
200V
200V
200V
1000
EPC1007 x 6/5
Scaled MOSFET
Scaled MOSFET
EPC1010
Scaled MOSFET
Scaled MOSFET
Scaled MOSFET
A
B
C
D
E
200V devices
100
0
100V devices
20
40
60
80
100 120 140 160 180 200
Normalized On-state Resistance RDS(ON)
Fig. 4. EPC’s eGaN power transistor structure
2.0
1.8
>20%
RDS(ON)
1.6
1.4
1.2
1.0
0.8
0
20
40
60
80
Die temperature (ºC)
100
120
Drain-Source Voltage (V)
Fig. 5. COSS vs. VDS normalized to 25 mΩ
26
Power Electronics Technology
y | September 2010
Fig. 7. Comparison between eGaN and Silicon normalized RDS(ON) versus temperature
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GALIUMNITRIDEtransistors
silicon devices.
PARAMETER TEMPERATURE DEPENDENCE
One of the main advantages of eGaN
over silicon is the lower increase in onresistance (RDS(ON)) with temperature,
as shown in Fig. 7. Whereas silicon
has >70% increase in RDS(ON) between
25°C and 100°C, eGaN shows a 40%
increase. This translates into more than
20% lower RDS(ON) at a typical 100°C
die temperature assuming the same
initial RDS(on) at 25°C.
It is well known that, unlike minority
carrier devices, silicon MOSFETs have a
positive RDS(ON) temperature coefficient, making them ideal for paralleling
with no thermal run-away. What is
less known is that, due to the negative
temperature coefficient on the voltage
threshold, this does not translate into
dynamic current sharing. This can also
TABLE 1. GAN
PARAMETERS
Parameter
Description
CDS
Capacitance from drain-tosource
CGD
Capacitance from gate-todrain
CGS
Capacitance from gate-tosource
COSS
Output capacitance
RDS(ON)
On-resistance
QG
Total gate charge
QGS2
Gate charge between threshold voltage and Miller plateau
QGD
Gate-to-drain charge
QOSS
Output charge
QRR
Reverse recovery charge
QSW
Total switch charge
tRR
Reverse recovery time
LD
Drain lead inductance
LS
Source lead inductance
be an issue for linear amplifiers or similar applications where the MOSFETs
are normally run in saturation. For a
typical 200V MOSFET, this temperature coefficient is 0.325%/°C. eGaN
devices also have a negative temperature coefficient to the voltage threshold, but it is less than 300ppm/°C and
will therefore dynamically share for all
but the smallest of drain currents.
As low-voltage silicon MOSFET performance has improved over the last
number of years, the need for high
performance packaging has become a
major limiting factor in overall device
performance. This has lead to the development of such innovative packages
as the DirectFET2, or PolarPak
k3. But,
what exactly are the requirements of a
high performance package?
In general, semiconductor devices
are packaged to improve robustness
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September 2010 | Power Electronics Technology
27
GALIUMNITRIDEtransistors
and ease of handling. In addition, at
higher voltages some package forms
TABLE 2: COMPARATIVE DATASHEET QRR MEASUREMENTS
are required to meet voltage clearance
FOR DIFFERENT 200V PARTS SIMILAR TO EPC1010
and creepage requirements that might
Recovery
di/dt (A/
Final
Recovery
Example
Initial
not be possible without some form of
time, tRR
us)
reverse
charge, QRR
Current
bias (V)
(A)
(ns)
(nC)
encapsulation. In doing so, however,
A
17
100
100
110
500
the packaged device’s characteristics are
degraded compared to the bare semiB
20
100
NA
145
NA
conductor die. This performance degC
62
100
NA
145
810
radation comes in the form of increased
D
50
100
NA
130
520
cost, increased on-resistance, increased
E
46
100
50
100
430
lead inductance and reduced thermal
same is true during turn-off where the induced voltage adds
performance.
to the gate drive voltage, thus trying to keep the device on. It
What sets high performance packaging apart is being able
is therefore critical to minimize common source impedance
to realize the required advantages of device packaging while
for optimum switching performance.
minimizing the drawbacks: in other words less is more. With
The need to minimize both package resistance and comlow voltage, leadless dual-side-cooled packaging such as
mon source inductance are well known to silicon device
DirectFET, PolarPak or flip-chip becomes an elegant solumanufactures and has lead to inventions such as the ribbon
tion. Here the choice of package is largely dictated by the
bonds, copper clip/strap5, etc to reduce package resisdevice terminal structure; vertical vs. lateral. A lateral device
lends itself to easy flip-chip packaging (e. g. Greatwall BGA
tance and adding separate driver source pins such as IXYS
MOSFETs4), while a vertical, “flipped” device needs to bring
DE-Series6 and ThinPak7 that reduces common source
the “back” terminal down to the printed circuit board (such
inductance or PolarPAk8, DirectFet9 which reduces both.
as DirectFET or PolarPak). In a similar fashTABLE 3: PACKAGED DEVICE SIZE COMPARISON BETWEEN
ion, eGaN devices are flip-chip packages with
EGAN DEVICES AND BEST EQUIVALENT SILICON MOSFETs
bar grid arrays rather than ball grids where the
interdigitation of source and drain terminals
Device
EPC
Equivalent MOSFET packages*
package*
is used to minimize both on-resistance and
40V, 4mΩ
4.1 x 1.6mm
6.3 x 5mm
5 x 6mm
parasitic inductance.
max
DirectFET
PolarPak
PACKAGE RESISTANCE, INDUCTANCE
In Fig. 8 the estimated packaging resistance of
different standard power packages is shown
alongside the eGaN flip-chip parts.
The addition of package inductance can
have varied effects, depending on which terminal of the die the package inductance is
added. Overall package inductance comparison are shown in Fig. 9 for the eGaN flip-chip
die compared to estimated values for some
standard power packages. Common source
inductance (inductance inside the package
connected to the source terminal that carry
both drain and gate return currents) can
significantly increase switching losses by slowing down device switching through induced
opposition of the applied gate voltage.
Consider the turn-on of a device, as shown
in Fig. 10. In simple terms, as it reaches
threshold voltage and starts to carry increasing
current, this dI/dt induces a voltage across the
source inductance that opposes the gate drive
voltage, trying to turn the device back off. The
28
Power Electronics Technology
y | September 2010
40V, 16mΩ
max
1.7 x 1.1mm
100V, 7mΩ
max
4.1 x 1.6mm
100V, 30mΩ
max
1.7 x 1.1mm
200V,
100mΩ max
1.7 x 0.9mm
200V, 25mΩ
max
3.6 x 1.6mm
4.8 x 3.9mm
5 x 6mm
PQFN
DirectFET
4.8 x 3.9mm
DirectFET
6.3 x 5mm
DirectFET
5 x 6mm
PolarPak
10 x 15mm D2Pak
*Packages not drawn to scale
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GALIUMNITRIDEtransistors
Estimated Package Resistance
6
Package Inductance (mH)
Package Resistance (mΩ)
Estimated Package Resistance
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
SO
-8
DP
AK
D2
Po
5
5
D
E
la F PC
PA wi x6 P Cu x6 P irec
rP lip
tF
K re b QF cl QF
a
ch
E
k
ip N
T
on N
ip
+
d +
SO
-8
DP
AK
Po
5
5
D
E
la F PC
PA wi x6 P Cu x6 P irec
rP lip
tF
K re b QF cl QF
ak ch
ET
ip N
on N
ip
+
d +
D2
Fig. 8. Estimated die free package resistance for different power packages
Fig. 9. Estimated die free package inductance for different power packages
As end products face the pressures of lower cost and
smaller size, the size of the power devices has become of
increasing importance. In general, a smaller size is desirable
as long as the thermal requirements can be met. The act of
encapsulating a device inside a package will alMost always
deteriorate thermal and electrical performance. eGaN
devices allow a much lower on-resistance per unit area for
the same voltage rating, which in turn reduces die and package size. Table 3 compares eGaN devices to the smallest
packaged silicon device with similar RDS(ON) specifications.
Apart from an improved Figure of Merit, today’s eGaN
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September 2010 | Power Electronics Technology
29
GALIUMNITRIDEtransistors
Drain
Current
Gate
Drive
Gate
Current
Drain
Current
Gate
Drive
+
Gate
Current
+
–
FUTURE DEVELOPMENTS
–
Common source
inductance
flip-chip packaging, which is a very high performance packaging solution due to the minimal increase in on-resistance
and terminal inductance. Add to this a distinct die area
advantage over silicon, and the resultant solution is a superior power device in a high performance package that is
significantly smaller than anything available today.
dI/dt induced voltage
opposes gate drive
Fig. 10. Equivalent circuit of device at turn-on showing dI/dt induced voltage
generated by the common source inductance.
devices other advantages over silicon. Most notable is the
lack of diode reverse recovery losses (QRR), which is significant at higher voltage. Other advantages are lower QOSS
and better RDS(ON) vs. temperature. On the balance side,
the losses from the higher eGaN “body diode” forward drop
– important at lower voltages only - need to be minimized
through the proper timing of the gating signals.
The eGaN device’s lateral structure also lends itself to
In a future issue, we will discuss the requirements on getting
the most out of these eGaN devices. This will cover both
the electrical aspects such as gate driver requirements and
proper device rating; and mechanical requirements including device footprint, proper layout, assembly and thermal
requirements.
REFERENCES:
1. http://epc-co.com/epc/documents/datasheets/EPC1001_datasheet_final.pdf
2. http://www.irf.com/product-info/hexfet/directfet.htm
3. http://www.vishay.com/company/press/releases/2005/051214mosfets/
4. http://www.greatwallsemi.com/AppNotes/BGAMounting.pdf
5. IR patent 6,040,626
6. http://www.ixysrf.com/pdf/diodes/app_notes/kelvin_lead.pdf
7. http://www.infineon.com/cms/en/product/promopages/IMM/ThinPAK/
index.html
8. Vishay patent 7,476,978
9. IR patent 7,119,447
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