1. No category

Seamless Refinement from
Transaction Level to RTL
Using SystemVerilog Interfaces
Jonathan Bromley
Doulos Ltd, Ringwood, UK
[email protected]
2
Outline
• Introduction: refinement steps and verification
• Modeling styles and the need for partial refinement
• Use of SV interfaces in RTL and abstract modeling
• Interfaces to adapt between levels of abstraction
• Results and performance
• Summary
3
Example System Model
arbitrating (master) bus interfaces
bus
bus fabric
fabric
CPU
CPU
masters
DMA
slaves
ROM
ROM
peripheral
peripheral
control
RAM
RAM
simple (slave)
bus interfaces
4
Refinement Steps and Verification
• Abstract model is attractive early in the project:
– easier to write correct functionality than in RTL
– simulates faster
– ideal vehicle for debugging your verification environment
• Abstract model is progressively replaced by RTL
implementation
During development, abstract model is an
ideal testbed for individual RTL components
5
Outline
• Introduction: refinement steps and verification
• Modeling styles and the need for partial refinement
• Use of SV interfaces in RTL and abstract modeling
• Interfaces to adapt between levels of abstraction
• Results and performance
• Summary
6
RTL Connection
• Module-to-module connections use ports and wires
module
module sender
sender ((
output
output reg
reg data
data
);
);
...
...
data
data == new_value;
new_value;
...
...
wire W;
module
module receiver
receiver ((
input
input test
test
);
);
always
always @(test)
@(test)
...;
...;
– Complete decoupling of connected modules
– Slow simulation (processes sensitive to events)
– Synthesizable
7
TLM Connection
• Communication by subroutine call
module
module tlm_send;
tlm_send;
initiator
...
...
send(new_value);
send(new_value);
...
...
module
module tlm_receive;
tlm_receive;
task
task accept(byte
accept(byte b);
b);
...;
...;
target
– Much faster simulation (one call can send lots of data)
– Not synthesizable (cross-module subroutine call)
– Decoupling of connected modules is more difficult
– The whole idea of connection is much less obvious
8
Mixed Modeling Styles
• I want to ...
CPU
CPU
bus
bus fabric
fabric
memory
memory
peripheral
peripheral
– freely mix RTL and TLM styles in one system model
– mix modeling styles on a single component
– swap models without disturbing the rest of the system
9
Outline
• Introduction: refinement steps and verification
• Modeling styles and the need for partial refinement
• Use of SV interfaces in RTL and abstract modeling
• Interfaces to adapt between levels of abstraction
• Results and performance
• Summary
SystemVerilog Interfaces Support
RTL and TLM Connection Styles
• Well-known, synthesizable RTL usage:
Interface as a bundle of wires
RTL
RTL initiator
initiator
RTL
RTL target
target
• Less familiar, but fully supported:
Interface redirects a subroutine call
TLM
TLM initiator
initiator
TLM
TLM target
target
10
11
Subroutine Import
module
module tlm_sender
tlm_sender (( tlm_intf.sender_mp
tlm_intf.sender_mp send_port
send_port );
);
...
...
send_port.put
send_port.put
...
...
endmodule
endmodule
module does not know interface instance name
(( nn );
);
instances
tlm_sender
tlm_sender
tlm_intf
tlm_intf
interface
interface tlm_intf
tlm_intf ();
();
task
task put
put (input
(input byte
byte b);
b);
...;
...;
endtask
endtask
modport
modport sender_mp
sender_mp (( import
import task
task put
put (input
(input byte
byte b)
b) );
);
endinterface
endinterface
provide task to a connected module
12
Subroutine Export
get task from a connected module
interface
interface tlm_intf
tlm_intf ();
();
modport
modport receiver_mp
receiver_mp (( export
export task
task put
put (input
(input byte
byte b)
b) );
);
...
...
initial
initial
tlm_receiver
tlm_receiver
put
put (( "A"
"A" );
);
tlm_intf
tlm_intf
endinterface
endinterface
module
module tlm_receiver
tlm_receiver ((
tlm_intf.receiver_mp
tlm_intf.receiver_mp receive_port
receive_port );
);
task
task receive_port.put
receive_port.put (( input
input byte
byte bb );
);
$display("I
$display("I got
got data=%0d",
data=%0d", b);
b);
endtask
endtask
module does not know interface instance name
endmodule
endmodule
13
TLM-Style Connection
Through an Interface
module
module tlm_sender
tlm_sender (( tlm_intf.sender_mp
tlm_intf.sender_mp send_port
send_port );
);
initial
initial call redirected to connected target
initiator
send_port.put
initiator
send_port.put (( nn );
);
interface
interface
endmodule
endmodule
target
target
interface
interface tlm_intf
tlm_intf ();
();
modport
modport sender_mp
sender_mp (( import
import task
task put
put (input
(input byte
byte b)
b) );
);
modport
modport receiver_mp
receiver_mp (( export
export task
task put
put (input
(input byte
byte b)
b) );
);
endinterface
endinterface
interface is only a connection
module
module tlm_receiver
tlm_receiver (( tlm_intf.receiver_mp
tlm_intf.receiver_mp receive_port
receive_port );
);
task
task receive_port.put
receive_port.put (( input
input byte
byte bb );
);
$display("I
$display("I got
got data=%0d",
data=%0d", b);
b);
called by connected initiator
endtask
endtask
endmodule
endmodule
14
Example System Model
arbitrating (master) bus interfaces
bus
bus fabric
fabric
CPU
CPU
masters
DMA
slaves
ROM
ROM
peripheral
peripheral
control
RAM
RAM
simple (slave)
bus interfaces
15
Multiple Exports Problem
bus
bus fabric
fabric
ROM
ROM
RAM
RAM
interface
interface tlm_sbi
tlm_sbi ();
();
modport
modport fabric_mp
fabric_mp (( import
import task
task write
write ...
... );
);
modport
modport slave_mp
slave_mp (( export
export task
task write
write ...
... );
);
endinterface
endinterface
module
module tlm_ROM
tlm_ROM (tlm_sbi.slave_mp
(tlm_sbi.slave_mp SBI);
SBI);
task
task SBI.write
SBI.write (...);
(...);
$display("error,
$display("error, write
write to
to ROM
ROM %m");
%m");
endtask
endtask
module
module tlm_RAM
tlm_RAM (tlm_sbi.slave_mp
(tlm_sbi.slave_mp SBI);
SBI);
...
...
task
task SBI.write
SBI.write (input
(input [15:0]
[15:0] addr,
addr, data);
data);
mem[addr]
mem[addr] == data;
data;
...
...
VCS error: tlm_sbi.write double-defined
16
Multiple Exports Solution
bus
bus fabric
fabric
ROM
ROM
RAM
RAM
interface
interface tlm_sbi
tlm_sbi ();
();
modport
modport fabric_mp
fabric_mp (( import
import task
task write
write ...
... );
);
modport
modport slave_mp
slave_mp (( export
export task
task write
write ...
... );
);
endinterface
endinterface
module
module tlm_ROM
tlm_ROM (interface.slave_mp
(interface.slave_mp SBI);
SBI);
task
task SBI.write
SBI.write (...);
(...);
port has generic
$display("error,
$display("error, write
write to
to ROM
ROM %m");
%m");
interface type
endtask
endtask
module
module tlm_RAM
tlm_RAM (interface.slave_mp
(interface.slave_mp SBI);
SBI);
...
...
task
task SBI.write
SBI.write (input
(input [15:0]
[15:0] addr,
addr, data);
data);
mem[addr]
mem[addr] == data;
data;
...
...
Generic port can be connected to any interface that has the correct modport
17
Outline
• Introduction: refinement steps and verification
• Modeling styles and the need for partial refinement
• Use of SV interfaces in RTL and abstract modeling
• Interfaces to adapt between levels of abstraction
• Results and performance
• Summary
18
Mixed Modeling Styles
• I want to ...
CPU
CPU
bus
bus fabric
fabric
memory
memory
peripheral
peripheral
– freely mix RTL and TLM styles in one system model
– mix modeling styles on a single component
– swap models without disturbing the rest of the system
19
Abstraction Adapter Interface
CPU
CPU
bus
bus fabric
fabric
• Interface provides a task
that manipulates signals
interface
interface tlm_to_rtl_abi
tlm_to_rtl_abi (input
(input logic
logic clk);
clk);
logic RE, WE;
logic [15:0] addr, wdata, rdata;
RTL-like signals
and modport
modport rtl_fabric (
output rdata, input wdata, addr, RE, WE );
task write ( input [15:0] A, D );
@(posedge clk) addr = A; WE = 1; RE = 0; wdata = D;
@(posedge clk) WE = 0;
this is simply a BFM
endtask
modport tlm_master ( import task write ... );
endinterface
endinterface
20
Swapping-in a Modified Model:
Use an Adapter Interface
• The interface's name changes ...
interface
interface tlm_abi
tlm_abi ...
...
CPU
CPU
bus
bus fabric
fabric
interface
interface tlm_to_rtl_abi
tlm_to_rtl_abi ...
...
CPU
CPU
bus
bus fabric
fabric
• so the unaltered module's port list must change ...
module
module tlm_CPU
tlm_CPU ((
tlm_abi.tlm_master
tlm_abi.tlm_master ABI,
ABI,
...
...
• This is unacceptable!
module
module tlm_CPU
tlm_CPU ((
tlm_to_rtl_abi.tlm_master
tlm_to_rtl_abi.tlm_master ABI,
ABI,
...
...
21
Swapping-in a Modified Model:
Generic Interface Ports
• The interface's name changes ...
interface
interface tlm_abi
tlm_abi ...
...
CPU
CPU
bus
bus fabric
fabric
interface
interface tlm_to_rtl_abi
tlm_to_rtl_abi ...
...
CPU
CPU
bus
bus fabric
fabric
• and with generic interface ports ...
module
module
module tlm_CPU
tlm_CPU ((
module tlm_CPU
tlm_CPU ((
interface.tlm_master
interface.tlm_master
interface.tlm_master ABI,
ABI,
interface.tlm_master ABI,
ABI,
...
...
...
...
the unaffected module's port list can remain the same!
22
Outline
• Introduction: refinement steps and verification
• Modeling styles and the need for partial refinement
• Use of SV interfaces in RTL and abstract modeling
• Interfaces to adapt between levels of abstraction
• Results and performance
• Summary
23
Results and Performance
• Example system modeled with various combinations
of TLM and RTL:
modeling style
simulation run time (seconds)
all TLM 8
> 1 000 000
all TLM except
14
RTL RAM
all TLM except
RTL RAM and ROM
all RTL
simulated CPU instructions
per second of simulation
650 000
48
194 000
732
12 800
24
Further Opportunities
• Exported/imported tasks
can be implemented by DPI:
initiator
initiator
interface
interface
target
target
interface
interface tlm_intf_SV_to_SV
tlm_intf_SV_to_SV ();
();
modport
modport sender_mp
sender_mp (( import
import task
task put
put (...)
(...) );
);
modport
modport receiver_mp
receiver_mp (( export
export task
task put
put (...)
(...) );
);
endinterface
endinterface
Target is a SystemVerilog module
interface
interface tlm_intf_SV_to_C
tlm_intf_SV_to_C ();
();
modport
modport sender_mp
sender_mp (( import
import task
task put
put (...)
(...) );
);
import
import "DPI-C"
"DPI-C" context
context task
task put
put (...);
(...);
endinterface
endinterface
Target is a function written in C
25
Summary
• Subroutine import/export in interfaces facilitates
high-level modeling in a static RTL-like architecture
– Less versatile than true TLM using SystemC etc
• Interface can be used as RTL-to-TLM adaptor
• All within a single-language environment
– Existing Verilog behavioral models easily integrated
– Familiar, static style of instantiation and connection
Thanks for your attention!
Questions?
Jonathan Bromley
Doulos Ltd, Ringwood, UK
[email protected]