EMP ISAE-ENSMA LSI-USTHB
Antinomy between Schedulability
and Quality of Control using
a Feedback Scheduler
RTNS’2014
Authors
Zakaria Sahraoui
Emmanuel Grolleau
Mohamed Ahmed Nacer
Dris Mehdi
EMP
LIAS ISAE-ENSMA
LSI USTHB
LIAS ISAE-ENSMA
Algeria
France
Algeria
France
LIAS ISAE-ENSMA
France
Speaker
Henri Bauer
Outline
Introduction
Antinomy in co-design
Scheduling artifacts characterization
Conclusion
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Why should we care ?
Traditional real-time scheduling
models give poor support for
scheduling/control co-design...
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Off-line optimization
M peak
E ss
M peak = f M (period, latency)
T rise
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T set
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E ss
= f E (period, latency)
T rise
= f r (period, latency)
T set
= f s (period, latency)
[Seto '96, Ryu '97]
4
Experimental settings
RM scheduled periodic tasks with implicit deadlines
shape factor = 3
scale = 0.15
localization = 2ms
Maximal
observed
execution
time
Minimal
observed
execution
time
Best
case
WCET
Execution times distribution following a Weibull law (given: best and WCET)
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The feedback scheduler
processor
utilization
bound
+
Scheduler
Manager
estimated
execution
time
plant
ref.
Scheduler
Filter (aging factor)
error
+
periods
-
Task i
Regulator
observed
execution
time
sampling period
control
D/A
measure
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Process
G(s)
A/D
6
Processor utilization bounds
[Liu & Layland '73]
1
n
∑ U i⩽n (2 −1)
[Bini '03] (hyperbolic condition)
∏ (U i +1)⩽2
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Timings and delays
Task period
Next task period
I/O latency
Exec. time
tk
measure
control
next I/O latency
Samp. latency
t k+1
measure
control
t k+2
Control latency
Sampling latency: higher priority task execution
I/O latency: execution time + higher priority preemption
Scheduling artifacts: latencies and jitters...
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Two study cases
●
●
Three servo-motors with a PID regulator
–
Well known study case from [Åström & Hägglund]
–
Adaptive samples: backward difference for derivative
–
Controlled by a single processor computer
Three inverted pendulums with cart
–
Another well studied benchmark [Åström & Furuta]
–
Strongly non linear three order coupled system
–
With cart: only horizontal moves
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Three servo-motors example
1000
G(s)=
s (s +1)
PID CONTROL
FUNCTION
Controller performance parameters: (ω 0, ξ)=(20, 0.707)
●
Use of adaptive samples in the PID
●
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Simulation setup
COST
CONTROL
OUTPUT
Tsim
SCHEDULING
ERROR COST FUNCTION:
∫ |ref −output|dt
0
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Assumption
Minimizing tasks' period
improves quality of control...
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Performance analysis
●
●
●
Three periodic tasks: nominal period hinom → task priority (RM)
Feedback scheduling: hik+1 = α hik → reach the utilization bound
Execution time: 3 ≤ Ci ≤ 5 ms (Weibull distribution)
Bound L&L test (U < 0.69)
h inom =
Hyperbolic test
Threshold (U = 0.5)
τ1
τ2
τ3
τ1
τ2
τ3
τ1
τ2
τ3
Error
0.063
0.065
0.64
0.060
0.062
1.35
0.088
768.7
>108
Sampling
period (ms)
12.52
15.55
18.79
12.40
15.51
18.60
19.43
24.24
29.15
I/O latency
(ms)
3.88
5.24
7.32
3.88
5.09
7.93
3.87
4.84
5.28
(4, 5, 6)
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The antinomy
Scheduling artifacts (response time and jitter)
increase when processor utilization increases
(controller tasks periods decrease).
The degradation caused by these phenomena on
a PID controller can be greater than the gain
generated by the increase in sampling rate.
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The antinomy illustrated
●
Three servo-motors: periodic tasks τ1, τ2,
●
Scheduled with RM
Ci
h inom
τ1
8.85
17.7
τ2
8.85
17.7
τ3
8.85
17.7
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τ3
(tie breaker: smallest task index)
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The antinomy illustrated
Ci
h inom
τ1
4.6
17.7
Same Ui but...
τ2-τ3
4.6
17.7
doubled pace for
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τ1
Ci
h inom
τ1
2.3
8.85
τ2-τ3
4.6
17.7
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Artifact characterization
●
Three servo-motors example
Ci
τ1
τ2
τ3
3.4
h inom Mode
k
µ
λ
6
3.2
3.1 0.2 3
13
3.2
3.1 0.2 3
14
3.2
3.1 0.2 3
mean sample period
Error cost function of
mean sample periods
for task τ3
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Artifact characterization
I/O latency
sampling latency
Error cost function of IO and
control jitter
Error cost function of
sampling latencies for τ3
control jitter for τ3
Linear correlation (SRS):
0.95 (I/O) and -0.81 (Samp)
Linear correlation (SRS):
-0.88
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Artifact characterization
●
Three inverted pendulum example
Ci
τ1
τ2
3.4
τ3
h inom Mode
k
µ
λ
6
3.2
3.1 0.2 3
13
3.2
3.1 0.2 3
14
3.2
3.1 0.2 3
I/O latency
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sampling latency
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mean sample period
control jitter
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Conclusion & perspectives
●
Do not (always) trust intuitive assumptions
●
Impact of scheduling artifacts on QoC
–
●
Contribution
–
●
Try to keep I/O latency low...
Identify scheduling parameters that deteriorate a real-time
control when the lower priority task's frequency tends
toward the closed-loop system bandwidth
Perspective: guidelines for better co-design...
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EMP ISAE-ENSMA LSI-USTHB
Thank you for your attention