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Lecture 23: Oxidation
Contents
1 Introduction
1
2 Oxidation types
2
3 Oxide growth model and parameters
4
4 Oxide furnaces
11
5 Thermal nitridation
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1
Introduction
Oxidation refers to the conversion of the silicon wafer to silicon oxide (SiO2
or more generally SiOx ). The ability of Si to form an oxide layer is very
important since this is one of the reasons for choosing Si over Ge. The Horni
transistor design which was used in the first integrated circuit by Robert
Noyce was made of Si and the formation of SiOx helped in fabricating a planar device.
Si exposed to ambient conditions has a native oxide on its surface. This is
usually around 3 nm thick. But the native oxide is too thin for most applications and hence a thicker oxide needs to be grown. This is usually done
by consuming the underlying Si to form SiOx . This is a grown layer. It is
also possible to grow SiOx by a chemical vapor deposition process using Si
and O precursor molecules. In this case the underlying Si in the wafer is not
consumed. This is called a deposited layer.
SiOx helps in protecting the wafer from contamination, both physical and
chemical. Thus, it acts as a surface passivating layer. The hard oxide layer
protects the wafer surface from scratches and it also acts as a contamination
layer by by preventing dust from interacting with the wafer surface. The
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Table 1: Silicon oxide thickness chart
Thickness, in ˚
A
60-100
150-500
200-500
2000-5000
3000-10000
Application
Tunneling gates
Gate oxides, capacitor dielectrics
LOCOS pad oxide
Hard masks, surface passivation
Field oxides
oxide layer also protects the wafer from chemical contaminant, mainly electrically active contaminants. SiOx also acts as a hard mask for doping and
as a etch stop during patterning. The original gate oxide in MOSFET was
made of SiOx . SiOx was also used as the inter-layer dielectric separating the
different metallization layers, though this is usually a deposited layer. SiO2
is also used to prevent induced charge due to the metal layers, this is called
a field oxide. In all of these forms different thickness of the oxide layer are
required. These are summarized in table 1.
2
Oxidation types
In the case of grown oxide layers there are two main growth mechanisms
1. Dry oxidation - The Si reacts with O2 to form SiO2 .
Si (s) + O2 (g) → SiO2 (s)
(1)
2. Wet oxidation - The Si reacts with water (steam) to form SiO2 .
Si (s) + 2H2 O (g) → SiO2 (s) + 2H2 (g)
(2)
In both cases the Si is supplied by the underlying wafer. Dry and wet oxidation need high temperature (900 - 1200 ◦ C) for growth though the kinetics
are different, that’s why this is called thermal oxidation. Since the underlying Si is consumed the Si/SiO2 interface moves deeper into the wafer. The
movement of the interface is shown in figure 1.
There is also a volume expansion since the densities of the oxide layer and
silicon are different. Thus the final thickness is higher than the initial Si
thickness. Consider the oxide layer silicon interface as shown in figure 2.
Here d is the thickness of the original Si layer that has been consumed in
forming the oxide layer of thickness d0 . Si has a density of 2.33 gcm−3 (ρSi )
and an atomic weight of 28.08 gmol−1 (ZSi ) while SiO2 has a density of 2.65
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Figure 1: Movement of the silicon-oxide interface as oxide thickness grows.
Taken from Fundamentals of semiconductor manufacturing and process control - May and Spanos.
Figure 2: Schematic cross section of the Si oxide interface.
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Figure 3: One dimensional growth model for oxide formation.
gcm−3 (ρSiO2 ) and a molecular weight of 60.08 gmol−1 (ZSiO2 ). Given that
the cross section area, A, is the same it is possible to use the law of molar
conservancy to derive the relation between d and d0 . This is given by
d0 AρSiO2
dAρSi
=
ZSi
ZSiO2
(3)
Substituting the values in equation 3 gives the relation that
d0 = 1.88 d
(4)
Hence the thickness of the oxide layer is larger than the thickness of the Si
that is consumed to form that oxide. To grow 100 nm of oxide 53.2 nm of
Si needs to be consumed.
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Oxide growth model and parameters
Consider the oxide growth model shown in figure 3. There is an oxide layer
of a certain thickness, d0 , already formed on the semiconductor. There are
also oxidizing species present in the gas phase that can cause further growth
of the oxide layer. The are three fluxes present in the system.
1. Flux, F1 , corresponds to the oxidizing species transported from the
bulk of the gas phase to the surface of the oxide layer, i.e. oxide-gas
interface.
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2. Flux, F2 , corresponds to the transport of the oxidizing species through
the oxide layer to the oxide-Si interface. For simplicity it can be assumed that there is no dissociation of the oxidizing species within the
oxide layer.
3. Flux, F3 , which is the reaction of the oxidizing species with Si to form
a new oxide layer.
When the system is in steady state
F1 = F2 = F3
(5)
Consider transport through the gas phase. This flux, F1 , can be written in
terms of concentration as
F1 = hG (CG − CS )
(6)
where hG is the mass transfer coefficient in the gas phase and CG and CS are
concentrations in the bulk of the gas phase and at the oxide/gas interface,
see figure 3. This can also be rewritten in terms of the concentration of the
oxidizing species within the oxide layer as
F1 = h (C ∗ − C0 )
(7)
where h is related to hc by
hG
(8)
HkB T
where H is the Henry’s law constant and T is the temperature. C∗ is the
equilibrium bulk concentration of the oxidizing species within the oxide and
C0 is the concentration at the surface.
The flux of the oxidizing species within the oxide layer, F2 , is given by
h =
F2 =
D (C0 − Ci )
d0
(9)
where D is the diffusion coefficient and C0 and Ci are the concentrations of
the oxide species at the oxide surface and oxide Si interface respectively. d0
is the thickness of the oxide layer, see figure 3. The diffusion coefficient is
given by an Arrhenius type expression
D = D0 exp(−
Ea
)
kB T
(10)
where Ea is the activation energy and D0 is the pre-exponent factor. These
values depend on the oxidizing species and the Si planes through which diffusion is happening, typically i.e. (100) or (111).
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The last flux term, F3 , refers to the reaction of the oxidizing species with Si
to form the oxide. This can be written as
F3 = ks Ci
(11)
where ks is the rate constant for the conversion of Si to SiO2 . In steady state
all three fluxes are equal, see equation 5, and this can be used to calculate
expressions for Ci and C0 .
These can be solved to write a general equation for the growth of an oxide
layer (with a starting oxide layer)
d20 + Ad0 = B (t + τ )
(12)
where d0 is the thickness of the oxide layer at time t. A, B, and τ are
constants that are given by
1
1
+ ]
ks
h
2DC ∗
B =
N1
2
d + Adi
τ = i
B
A = 2D [
(13)
where di is the initial oxide thickness (at t = 0). The values of A and B and
hence τ depend on the type of oxidation (wet or dry) and also the Si surface
plane i.e. (100) or (111). This data is summarized in figure 4. While the
general equation can be solved it is more instructive to consider two limiting
cases.
1. In the diffusion limited case the supply of the oxidizing species to the
Si-SiO2 interface is the rate limiting step. This determines the growth
rate of the oxide layer. The diffusion limiting case occurs when there
is a thick oxide layer, or at long oxidation time i.e. t τ . Consider
equation 12. This can be re-written as
t+τ
d0
= [1 + 2
] − 1
A/2
A /4B
(14)
when t τ , it also means that t A2 /4B, this means that equation
14 reduces to
d20 = Bt
(15)
This is a parabolic rate law that predicts that as the oxide thickness increases the time increases as the square of the thickness. The parabolic
rate constant B as a function of temperature is shown in figure 5.
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Figure 4: Linear rate constants, A and B, for different types of oxide, as
a function of temperature. Taken from VLSI fabrication principles - S.K.
Ghandhi
Figure 5: Rate constant, B, for thick oxide growth. Taken from VLSI fabrication principles - S.K. Ghandhi
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Figure 6: Thin oxide growth rate for Si (100) at different temperatures.
Taken from VLSI fabrication principles - S.K. Ghandhi.
2. When D is large or when the oxide thickness is small growth is controlled by the formation of the oxide layer, reaction controlled case.
For short oxidation times (or thin oxides) (t + τ ) A2 /4B. This
means that equation 12 can be simplified to
d0 =
B
(t + τ )
A
(16)
This is a linear rate law so that for thin oxides the thickness increases
linearly with time. This is shown in figure 6.
Consider dry oxidation (using O2 gas) at a temperature of 1000 ◦ C. For
Si(100) the value of B is 0.017 µm2 /hr. To grow an oxide layer of thickness
(d0 ) 100 nm (thick oxide), using the parabolic rate law, equation 15, gives a
growth time of 51 min. To grow 200 nm the corresponding time is 3 hr and
25 min. Thus to grow thick oxides using dry oxides the temperature should
be higher, to increase D and hence B. The oxide thickness as a function of
time for dry ox is shown in figure 7.
Instead of dry oxidation consider wet oxidation under the same temperature, 1000 ◦ C. The value of B for wet ox is 0.287 µm2 /hr. Using the same
parabolic rate law, equation 15, the time to grow 100 nm is only 2 min while
for 200 nm time is 8 min. These times are much smaller than dry ox but
2 min would be too short a growth time to get uniformity across the wafer,
i.e. process control will be difficult. Also, electrical properties of the silicon
oxide growth by wet oxide are different from that grown by dry oxide. The
oxide thickness vs. time for wet ox is shown in figure 8.
Oxide growth rate is also affected by the dopant concentration. Heavily
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Figure 7: Oxide thickness for Si (100) and (111) at different temperatures
for dry oxidation. Taken from VLSI fabrication principles - S.K. Ghandhi.
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Figure 8: Oxide thickness for Si (100) and (111) at different temperatures
for wet oxidation. Taken from VLSI fabrication principles - S.K. Ghandhi.
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doped Si oxidizes at a faster rate than lightly doped Si. Since the oxide
forms by consuming the underlying Si the dopant concentration in the Si
layer adjacent to the oxide is also altered. For n-Si (P, As, Sb) as the oxide
grows the dopants get ejected into the underlying Si. This leads to pile-up
of dopants at the interface which will affect the electrical properties. On
the other hand, for p-Si (B) the oxide layer draws in the dopants so that
the concentration is lowered near the interface. This has implications for
performance of devices. A pn junction fabricated in Si can have its junction potential altered during oxide formation on its surface (for patterning
to make contacts or when forming inter layer dielectrics). Also, the transport
properties through the junction could be altered leading to change in device
performance speed. These become important considerations during circuit
design.
Thermal oxides are formed at temperatures in the range 900 - 1200 ◦ C (depending on thickness and type of oxide). Most oxides grown on Si have thicknesses greater than 30 nm (gate oxides are replaced by high-k dielectrics).
But with scaling thin oxides, 5 - 20 nm (or 50-200 ˚
A) are required for certain applications. Also, for oxide growth during later stages of fabrication it
might not be feasible to go to high temperatures since this could damage the
rest of the device (e.g. doping concentrations would get affected at high temperatures due to diffusion). Some applications also require thin films of oxide
and nitride growth together (oxynitrides). In such applications the growth
rate must be slow to get uniformity. This required new growth techniques
and chemicals. Ultra thin oxides (20 nm or less) can be grown on Si by using
nitric acid at 100 ◦ C. Because of low temperature this can be integrated with
conventional lithography as well.
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Oxide furnaces
Thermal oxides are generally grown using tube furnaces. This is an example
of a batch process, i.e. multiple wafers can be processed at the same time.
This becomes important in the context of process control since if there is any
deviation from required conditions it would affect multiple wafers and hence
lead to overall cost increase.
For small wafer sizes, typically 3” and 4” wafers, horizontal tube furnaces
are used for oxidation. A schematic of this furnace is shown in figure 9. The
furnace is typically divided into 3 zones - source zone, center zone, and load
zone. The source zone is used for introducing the gases required for oxidation.
Typically this is oxygen (dry ox) or steam (wet ox) at the appropriate partial
pressure (concentration). Sometimes chlorinated oxide layers are also grown.
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Figure 9: Schematic of a horizontal diffusion furnace. The furnace is typically
divided into 3 zones, with the process wafers loaded in the center zone. Taken
from Microchip fabrication - Peter van Zant.
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Figure 10: Schematic of a commercial horizontal diffusion furnace. Taken
from Microchip fabrication - Peter van Zant.
The chlorine incorporated in the oxygen reduces mobile ions in the oxide layer
and also reduces charges at the oxide-Si interface. This improves cleanliness
and device performance. The chlorine is usually introduced in the form of
Cl2 , hydrogen chloride gas (HCl), trichloroethylene (lq), or trichloroethane
(lq). Gaseous sources are usually mixed with the oxygen source while for liquid sources the gas is bubbled through the precursor. Usually there are a few
purge and pup steps to reduce contamination in the furnace before oxygen is
introduced. Commercial tube furnaces also have loading zones (for loading
wafers) and cleaning stations, and stations for storing wafers. A schematic
of a commercial horizontal furnace is shown in figure 10.
The process wafers (wafers that are used to fabricate the integrated circuits)
are loaded in the center zone. Usually baffle plates are loaded at the ends
(these are usually made of quartz). Bare wafers, called fillers, are also loaded
along with the process wafers. These help in regulating gas flow through the
furnace so that oxide growth is uniform in the process wafers. Thus, not all
wafers in the furnace are process wafers. Higher the ratio of process wafers to
blank wafers that can be loaded in the furnace higher is the process throughput (number of wafers processed per hour). Temperatures are also constantly
maintained and regulated within the furnace during oxidation.Typical temperature profile during oxidation is shown in figure 11.
The idle temperature is usually not temperature but some elevated temperature, typically 300-400 ◦ C, to minimize total oxidation time.
For larger wafers (typical process wafers are now 12” or 300 mm wafers)
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Figure 11: Temperature profile in a tube furnace during oxidation. Taken
from Microchip fabrication - Peter van Zant.
horizontal furnaces are not practical and also occupy a lot of space. Diffusion furnaces are now vertical, called vertical diffusion furnaces (VDF). A
schematic of a VDF is shown in figure 12. The furnace consists of a loading
station and space for storing wafers (before and after processing). The boat
(where wafers are loaded for processing) moves vertically into the furnace,
see figure 12. VDF are more compact than horizontal furnaces. Gas flow is
also more uniform, less turbulence. The boat is also rotated during operation
to ensure uniformity. This is especially true for mixed gases since the gases
move parallel to gravity and hence do not get separated. The operation of
the VDF is similar to the horizontal tube furnace. There are also baffles
and blanks. Typically a 125 wafer boat can hold a maximum of 75 product
wafers, the rest are fillers, baffles, and monitor wafers (for measuring oxide
thickness and uniformity for process control).
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Thermal nitridation
Nitridation is the growth of silicon nitride (Si3 N4 or more generally SiNx ) by
consuming the underlying Si. This is typically carried out by exposing Si to
ammonia gas at temperatures of around 950-1200 ◦ C (similar to oxidation
temperatures). Nitrogen gas is not used (like dry ox) since the activation
energy is much higher due to the stable N-N bond in nitrogen gas. Nitridation process and kinetics are similar to oxidation. Figure 13 shows nitride
thickness vs. time for different temperatures. Typically nitride thickness is
smaller than oxides (for same time and temperature). This is because the
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Figure 12: Vertical diffusion furnace schematic. Taken from Microchip fabrication - Peter van Zant.
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Figure 13: Nitride thickness vs time for different temperatures. Taken from
Microchip fabrication - Peter van Zant.
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nitride layer is denser and diffusion of the reaction species through the nitride layer is usually the rate limiting step, parabolic rate law, equation 15.
Thus growing thick nitride layers is an issue. Nitride layers also have larger
stresses than oxide and can delaminate at higher thickness. Special low pressure processes are required to minimize the stress. Sometimes oxynitrides
or ONO (oxide/nitride/oxide) layers are also grown. These were originally
used as gate oxides, replacing pure silicon oxide, since they have a higher
dielectric constant.
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