MRAM : Materials and Devices Current--induced Domain Wall Motion Current High--speed MRAM High N. N Ishiwata NEC Corporation A portion of this study was supported by NEDO. Page 1 Outline ▐ Introduction Positioning and direction of MRAM High speed MRAM cell ▐ Domain wall motion cell for high g speed p MRAM Device structure and materials Writing properties and memory operation ▐ Summary Page 2 Comparison of novel and conventional memories MRAM FeRAM PRAM FLASH SRAM DRAM Mechanism Magnetic Tunnel J Junction ti FerroFerroelectric Phase change Floating gate Transistor Capacitor Non--volatile Non ○ ○ ○ ○ × × Endurance Unlimited (>10 ( 1015) Limited (<10 ( 1013) Limited (<10 ( 109) Limited (<10 ( 106) Unlimited (>10 ( 1015) Unlimited (>10 ( 1015) Access time Very Fast (~10ns) Fast (50~100ns) Medium (>100ns) Fast (read) Slow (write) Very fast (~10ns) Fast (~50ns) Refresh No No No No No Yes Cell size Medium Large Small Very Small Large Small Low voltage ○ ○ ○ △ ○ ○ High temperature operation ○ × × △ ○ △ Application Work memory Work memory? Storage Storage Work memory Work memory ▐ MRAM has great potential for use as non-volatile working memory. Page 3 Perfformance e Frequency (Hz) DWM--MRAM cell is located at … DWM DWM-MRAM DWM12 F2 >200 MHz High-speed HigheSRAM 1G eSRAM 100M eDRAM eFLASH DRAM 10M 1st-MRAM Cost FLASH 100 10 1 Relative cell size (F2) ▐ 12F2 & 200MHz cell has the features of eSRAM & eDRAM eDRAM. ▐ Very useful for future high-speed embedded memory in SoC. Page 4 2Tr--1MTJ cell for high2Tr high-speed MRAM operation 2Tr--1MTJ cell 2Tr BL GND /BL Read MTJ 250 MHz (ASSCC 2007) WL Write 3-terminals magnetic element 32 Mbit (ISSCC 2009) ▐ No problem with either write disturbance or read one ֜ Great advantage for high-speed operation Page 5 1 01 0.1 Low w cost Iwritee (mA A) Key issue : Reduction of writewrite-current (Iwrite) Field-writing SoC 0.2 mA STT writing STT-writing 100 W (nm) 1000 ▐ <0.2 mA ֜ 2Tr-1MTJ cell has higher cost performance than conventional memories used in SoC. ▐ Spin-transfer torque switching is promising for lowering write-current. Page 6 Spin transfer torque switching ▐ Conventional Spin transfer torque switching F.J.Albert F J Albert et al al., Appl Appl. Phys Phys. Lett Lett., 77-23 77-23, 3809 3809, 2000 2000. ▐ Current-induced domain wall motion ((DWM)) A.Yamaguchi et al., Phys. Rev. Lett. 92, 077205, 2004. • NiFe (in-plane) M. Yamanouchi et al., NATURE, 428, P.539, 2004. • GaMnAs (perpendicular) Page 7 Positive characteristics of DWM elements ▐ Suitable for 2Tr-1MTJ cell ▐ Scalable write-current write current & write-speed write speed ▐ Sufficient thermal stability without write current increase ▐ Suppression for read disturbance & tunneling barrier damage in write process ▐ CMOS process compatibility Page 8 Minimum cell layout for 2Tr2Tr-1MTJ DWM cell Plan--view Plan Cross--sectional Cross sectional--view 12 F2 4F 4F BL /BL M5 GND. 3F M6 Memory element Tr1 Tr2 WL Gnd. BL /BL M4 n+ n+ Criterion: Iwrite < 0.2 mA ▐ 12F2 0.1 0 1 m2 @ 90 90-nm nm rule ▐ 12F2 is possible only when the write-current is < 0.2 mA Page 9 Device structure for minimum cell layout Gnd. Reference layer Fixed region “0”-state Tunnel barrier Free layer Pinning y layer Data region i WL BL Tr1 Tr2 e “1”-write “1”-state DW /BL DW Pinning sites Page 10 DW e- “0”-write What kind of material should be chosen ? St bl Stable IMA 10 In-plane magnetic anisotropy DW PMA 1 Perpendicular magnetic anisotropy 0.1 01 1-D model 10 100 Critical field, Hc (Oe) Small S sity, Critica al curren nt dens jc (x108 A A/cm2) LLG (3(3-D) Simulation DW 1000 Tatara et al. JPSJ, 75, 064708, 2006. Suzuki et al. JAP, 103, 113913, 2008. ▐ Using PMA, much smaller cell area with much better stability can be achieved. Page 11 DWM materials Material Anisotropy Temp. (K) Minimum Jth (A/m2) Pinning field (Oe) Velocity (m/sec ) (m/sec.) [Co/Ni]N Perpendicular R.T. 0.3x1012 200 60 [Co/Pt]N Perpendicular R.T. 1.8x1012 500 - CoCrPt Perpendicular R.T. 1.0x1012 500 - GaMnAs Perpendicular 100 8.0x108 40 22 NiFe In-plane In plane R.T. 1.0x1012 5 110 ▐ Co/Ni is the best material for DWM, because of its small Jth with large pinning field and high velocity. Page 12 Write--current, Iwrite Write 1.2 Iwritee (mA) 1.0 Fi d Fixed 0.8 Fi Fixed d W 0.6 0.4 [Co/Ni] 0.2 02 0.0 DWM 0 100 200 W (nm) ▐ At less than 100 nm width,, the write-current becomes less than 0.2 mA. ֜ The most important criterion is satisfied. Page 13 Write--time, twrite Write Swittching p probab ility Proba ability Fi d Fixed Fi d Fixed 200 nm 1.0 10 ns 5 ns 3 ns 133 nm 0.5 DW V VDWM > 50 m/s 0.0 0 100 200 Voltage (mV) Pulse Voltage (mV) twrite < 2 ns @ ℓ ~ 90 nm >200 MHz ▐ More than 200 MHz operation is promising. Page 14 DWM Memory operation : 4 Kbit array 4 Kbit array MRAM Frequency (%) CMOS -I 60 40 +I R0 R1 20 0 RMTJ (a.u.) ▐ The two resistance states of the MTJ are clearly separated. ▐ The change of resistance is consistent with current direction. Page 15 Rmtj RMTJ (a.u.) (a.u.))) Repeat test for write and read operation R1 R0 0101… 1 0000… 51 1111… 101 00001111… 151 # of W/R ▐ Good reproducible switching and overwrite properties are confirmed confirmed. Page 16 Summary ▐ DWM MRAM with 2Tr-1MTJ high-speed cell 12 F2 (0.1 m2 @ 90 nm rule), >200 200 MHz Scalable write-current & write-speed with sufficient thermal stability 4 kbit memory array operation has been demonstrated ▐ Co/Ni multilayer film with perpendicular magnetic anisotropy is the answer for DWM MRAM Page 17 Th k you Thank y Page 18
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