1. No category

ＬＲ３８６０３
10
5. DSP register table
Address
Name
Bit
00
STOP_EEPROM
[7:0]
Stop reading from EEPROM, only when EEPROM data is FF.
01
LPF_TH
CCD_SEL
[7]
[6:5]
H: Luminance signal processing without LPF (When using BW-CCD)
00: 27-million pixel CCD(NTSC) 01: 41-million pixel CCD(NTSC)
10: 32-million pixel CCD(PAL) 11: 47-million pixel CCD(PAL)
ADTI
[4:3]
SEL_CDS
[2]
[1:0]
Input data timing adjustment
00: Reference 01: 1CK delay 10:1CK forward 11: 2CK forward
1: Latch with inverted clock
Select CDS IC 00: IR3Y38M 01: IR3Y48M
1X: IR3Y48A
0: Interlace 1: Non-interlace
Select output mode.
000: analog video output
EXCKI: vertical reset pulse input
001: analog video output
EXCKI: 8fsc clock input
010: analog video output
EEMD2: horizontal reset pulse input
EEMD3: vertical reset pulse input
100: YUV digital video output: clock rate of video data pixel-CK
101: YUV digital video output: clock rate of video data EXCKI
110: UYVY digital video output: clock rate of video data EXCKI
011, 111 is prohibited.
Shutter speed at power-on, 0: minimum 1: maximum
AGC control, 0: Auto 1: Fixed
Carrier balance control, 0: Auto 1: Fixed
Select output signal from HD pin
00: HD output(CCD drive timing)
01: HD output(Video output timing)
10: BELL pulse(in analog video output), HREF(in digital video output)
11: Fixed to L level
02
NI
[6]
[5:3]
MODE_OUT_SIG
03
START_EE
AGC_FIX
OB_SEL
HD_SEL
[2]
[1]
[0]
[6:5]
VD_SEL
[4:3]
DCK1_SEL
[2:1]
DCK2_SEL
[0]
Function
Select output signal from VD pin
00: VD output(CCD drive timing)
01: VD output(Video output timing)
10: Fixed to L level (in analog video output),VS(in digital video output)
11: Fixed to L level (in analog video output),CSYNC(in digital video
output)
Select output signal from DCK1 pin(in analog video output)
00: CSYNC 01:CBLNK 1x: Fixed to L level
Select output signal from DCK2 pin(in analog video output)
0: fluorescent signal 1: Fixed to L level
ＬＲ３８６０３
Address
Name
Bit
Function
When digital video output, selected by MODE_OUT_SIG(add02), this
register is adapted instead of pin setting.
And, this register is adapted to EEMD2 and EEMD3, even when
analog video output
MIR(MSB),EEMDS,EEMD1,EEMD2,EEMD3,BLC,WB2,WB1(LSB)
Select minimum shutter speed 0: 1/60(1/50) 1: 1/100(1/120)
Restriction to maximum shutter speed
(When EEMDS,EEMD1,EEMD2,EEMD3=4'b1110)
Reference of exposure
Outside range of error of exposure reference
(Hysterisis range of IRIS, AGC tweaking range)
Inside range of error of exposure reference
(Exposure control is stopped in REF_IRIS±CTLD_0）
Exposure reference in condition against light(When BLC=H)
Ceiling clip in accumulate exposure data
Downward weight factor 1 in calculation of exposure(upper of screen)
Downward weight factor 2 in calculation of exposure.
Downward weight factor 3 in calculation of exposure.
Downward weight factor 4 in calculation of exposure.
Downward weight factor 5 in calculation of exposure.
Downward weight factor 6 in calculation of exposure.
Downward weight factor 7 in calculation of exposure.
Downward weight factor 8 in calculation of exposure. (lower of screen)
Sum of UW_E1～UW_E8 must be 256d.
Ration of downward IRIS against center
Center point, position of left-upper area.
Center point, size of area.
Select dividing value of shutter speed control.
Select LPF of IRIS data in AGC normal adjustment.
Select LPF of IRIS data in AGC tweak.
Ration of luminance H peak of IRIS data
Ration of luminance L peak of IRIS data
Select peak accumulation. 0: Avg. of 8 pixels 1: Avg. of 4 pixels.
Reduction of IRIS control in normal operation. Operating
00: Always 01: each 2VD 10: each 4VD 11: each 8VD
Reduction of IRIS control in AGC tweak. Operating
00: Always 01: each 2VD 10: each 4VD 11: each 8VD
Select dividing value of AGC control.
Number of steps in AGC gain
Upper limitation of AGC control.
04
SW_CTRL
[7:0]
05
MIN_SH_SEL
MAX_SH
[7]
[6:0]
06
07
REF_IRIS1
CTLD_AGC
[7:0]
[7:0]
08
CTLD_0
[7:0]
09
0A
0B
0C
0D
0E
0F
10
11
12
REF_IRIS2
CLIP_IRIS
UW_E1
UW_E2
UW_E3
UW_E4
UW_E5
UW_E6
UW_E7
UW_E8
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
13
14
15
16
CW_E
CWP_E
CWA_E
EE_DIV_STP
LPFE_O
LPFE_I
P_HEE
P_LEE
MOD8
IRIS_DLY
[6:0]
[5:0]
[5:0]
[6:4]
[3:2]
[1:0]
[7:0]
[7:0]
[4]
[3:2]
IRIS_DLY
[1:0]
AG_DIV_STP
AG_GAIN
MAX_AGC
[7:5]
[4:0]
[7:0]
17
18
19
1A
1B
11
ＬＲ３８６０３
Address
Name
Bit
1C
1D
1E
REF_AGC
S_38M_GA
S_38M_GA_U
S_38M_MX
[7:0]
[7:0]
[3]
[2:0]
1F
S_38M_OFS
[7]
[6:0]
20
21
22
23
24
CSEPR
CSEPB
CB_R
CB_B
C_GAM
YL_SEL
[7:0]
[7:0]
[7:0]
[7:0]
[5:3]
[2:1]
C1_RB_SEL
[0]
26
MODE_MAT
LC_ON_RB
YL_SUB
UV_CTRL1
SEL_RB
SEL_RB2
SPCTRL
IDCO
MAX_WBR
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
27
MIN_WBR
[7:0]
28
MAX_WBB
[7:0]
29
MIN_WBB
[7:0]
2A
JMP_OFF
AWB_HIGH
MAX_IQAREA
25
[4]
[3]
[2]
IQ_LPF
[1:0]
2B
2C
2D
2E
2F
30
K_WBR_H
K_WBB_H
CMP_CT
AWB_HCL
AWB_LCL
REF_WBPK
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
31
K_CL
[7:0]
12
Function
Lower limitation of AGC control (initial value of AGC at power-on).
Fixed AGC gain [7:0 (LSB) ]
Fixed AGC gain in using IR3Y48M,IR3Y48A [8(MSB)]
IR3Y38M variable gain width. 000: (12~22dB) ~ 111: (12~40dB)
IR3Y48A minimum gain [1:0] 00:0 01:+6dB 10:+12dB 11:-2dB
IR3Y48M minimum gain 000: +0dB~111: +11.8dB
Offset auto adjustment. 0: Auto
1: Fixed(When using IR3Y48M,IR3Y48A)
Factor in fixed offset mode
Fixed 40h in using IR3Y48M,IR3Y48A
R side factor of color separation (positive value)
B side factor of color separation (positive value)
R side factor of carrier balance (complement of 2)
B side factor of carrier balance (complement of 2)
Select characteristics of color gamma.
Manner of YL signal production ([2:1])
00: Avg. of 3 lines 01:each R,B line 1X: fixed ration
Manner of RG signal production
0: use color separation factor(address 20,21)
1: use fixed color separation factor.
Matrix factor 0: unsigned 1: signed
1: Operation against line crawl in color processing.
1: Make YL 0 in chrominance generation.
Switch order of UV digital output
Swap R and B after color separation.
Swap R-Y and B-Y in output
Switch attribute of SP1 and SP2.
Switch attribute of color separation HG.
Upper limit of R side range of AWB gain (9 bits data which includes 1
at LSB)
Lower limit of R side range of AWB gain (9 bits data which includes 1
at LSB)
Upper limit of B side range of AWB gain (9 bits data which includes 1
at LSB)
Lower limit of B side range of AWB gain (9 bits data which includes 1
at LSB)
0: normal 1: Suppress AWB skipping
0: normal 1: Force fast processing in small frame
0: address36-3D 1: Fix WB frame to maximum.
Select LPF of AWB I, Q.
00: Avg. of 4 V 01: Avg. of 2 V 1X:Non
R side multiplier of capture speed in AWB fast processing.
B side multiplier of capture speed in AWB fast processing.
Number of operations of white balance(each CMP_CT x VD)
Initial value of AWBHCL
Initial value of AWBLCL
Reference data in calculation of intercept level of AWB accumulated
luminance
H peak ration in calculation of intercept level of AWB accumulated
luminance
ＬＲ３８６０３
Address
Name
32
K_WBCL
33
INT_I_R_Y
CW_IQ
CWPA_IQ
CTLD_AW0
AWB_IP_L
AWB_IM_L
AWB_QP_L
AWB_QM_L
AWB_IP_S
AWB_IM_S
AWB_QP_S
AWB_QM_S
AWB_IW_L
AWB_QW_L
AWB_IW_S
AWB_QW_S
AWB_C_I
AWB_C_Q
WBR1
WBB1
WBR2
WBB2
WBR3
WBB3
Bit
Function
[7:0]
Multiplier in calculation of intercept level of AWB accumulated
luminance
AWB detected data
0:I, Q 1:R-Y,B-Y
Ration of AWB weighted center and downward.
Position and area of AWB center.
Reset range of WB frame (compared with IRIS)
Outside, I-axis positive of AWB detect area (in fast processing)
Outside, I-axis negative of AWB detect area (in fast processing)
Outside, Q-axis positive of AWB detect area (in fast processing)
Outside, Q-axis negative of AWB detect area (in fast processing)
Inside, I-axis positive of AWB detect area (in normal processing)
Inside, I-axis negative of AWB detect area (in normal processing)
Inside, Q-axis positive of AWB detect area (in normal processing)
Inside, Q-axis negative of AWB detect area (in normal processing)
Determinate white area, I-axis, outside (for hysterisis).
Determinate white area, Q-axis, outside (for hysterisis).
Determinate white area, I-axis, inside (for determinate white area).
Determinate white area, Q-axis, inside (for determinate white area).
WB convergence orientation, I-axis coordinate (complement of 2)
WB convergence orientation, Q-axis coordinate (complement of 2)
WB1 R side constant (9 bits data which includes 0 at MSB)
WB1 B side constant (9 bits data which includes 0 at MSB)
WB2 R side constant (9 bits data which includes 0 at MSB)
WB2 B side constant (9 bits data which includes 0 at MSB)
WB3 R side constant (9 bits data which includes 0 at MSB)
WB3 B side constant (9 bits data which includes 0 at MSB)
Chrominance gain of R-Y negative direction when WB1 is fixed or auto
control (present WBR factor ≤ WBR1).
Chrominance gain of B-Y negative direction when WB1 is fixed or auto
control (present WBR factor ≤ WBR1).
Chrominance gain of R-Y positive direction when WB1 is fixed or auto
control (present WBR factor ≤ WBR1).
Chrominance gain of B-Y positive direction when WB1 is fixed or auto
control (present WBR factor ≤ WBR1).
Chrominance gain of R-Y negative direction when WB2 is fixed or auto
control (present WBR factor ≤ WBR2).
Chrominance gain of B-Y negative direction when WB2 is fixed or auto
control (present WBR factor ≤ WBR2).
Chrominance gain of R-Y positive direction when WB2 is fixed or auto
control (present WBR factor ≤ WBR2).
Chrominance gain of B-Y positive direction when WB2 is fixed or auto
control (present WBR factor ≤ WBR2).
[7]
42
43
44
45
46
47
48
REF_GA_R1M
[6:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0]
[6:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
49
REF_GA_B1M
[7:0]
4A
REF_GA_R1P
[7:0]
4B
REF_GA_B1P
[7:0]
4C
REF_GA_R2M
[7:0]
4D
REF_GA_B2M
[7:0]
4E
REF_GA_R2P
[7:0]
4F
REF_GA_B2P
[7:0]
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
13
ＬＲ３８６０３
Address
Name
14
Bit
Function
Chrominance gain of R-Y negative direction when WB3 is fixed or auto
control (present WBR factor ≤ WBR3).
Chrominance gain of B-Y negative direction when WB3 is fixed or auto
control (present WBR factor ≤ WBR3).
Chrominance gain of R-Y positive direction when WB3 is fixed or auto
control (present WBR factor ≤ WBR3).
Chrominance gain of B-Y positive direction when WB3 is fixed or auto
control (present WBR factor ≤ WBR3).
Chrominance gain slope of R-Y negative direction in WB auto control
(WBR1 < present WBR < WBR2)
Chrominance gain slope of B-Y negative direction in WB auto control
(WBR1 < present WBR < WBR2)
Chrominance gain slope of R-Y positive direction in WB auto control
(WBR1 < present WBR < WBR2)
Chrominance gain slope of B-Y positive direction in WB auto control
(WBR1 < present WBR < WBR2)
Chrominance gain slope of R-Y negative direction in WB auto control
(WBR2 < present WBR < WBR3)
Chrominance gain slope of B-Y negative direction in WB auto control
(WBR2 < present WBR < WBR3)
Chrominance gain slope of R-Y positive direction in WB auto control
(WBR2 < present WBR < WBR3)
Chrominance gain slope of B-Y positive direction in WB auto control
(WBR2 < present WBR < WBR3)
Matrix correction factor of R-Y negative direction when WB1 is fixed or
auto control (present WBR factor ≤ WBR1).
Matrix correction factor of B-Y negative direction when WB1 is fixed or
auto control (present WBR factor ≤ WBR1).
Matrix correction factor of R-Y positive direction when WB1 is fixed or
auto control (present WBR factor ≤ WBR1).
Matrix correction factor of B-Y positive direction when WB1 is fixed or
auto control (present WBR factor ≤ WBR1).
Matrix correction factor of R-Y negative direction when WB2 is fixed or
auto control (present WBR factor = WBR2).
Matrix correction factor of B-Y negative direction when WB2 is fixed or
auto control (present WBR factor = WBR2).
Matrix correction factor of R-Y positive direction when WB2 is fixed or
auto control (present WBR factor = WBR2).
Matrix correction factor of B-Y positive direction when WB2 is fixed or
auto control (present WBR factor = WBR2).
50
REF_GA_R3M
[7:0]
51
REF_GA_B3M
[7:0]
52
REF_GA_R3P
[7:0]
53
REF_GA_B3P
[7:0]
54
K_GA_R1M
[6:0]
55
K_GA_B1M
[6:0]
56
K_GA_R1P
[6:0]
57
K_GA_B1P
[6:0]
58
K_GA_R2M
[6:0]
59
K_GA_B2M
[6:0]
5A
K_GA_R2P
[6:0]
5B
K_GA_B2P
[6:0]
5C
REF_MAT_R1M
[5:0]
5D
REF_MAT_B1M
[5:0]
5E
REF_MAT_R1P
[5:0]
5F
REF_MAT_B1P
[5:0]
60
REF_MAT_R2M
[5:0]
61
REF_MAT_B2M
[5:0]
62
REF_MAT_R2P
[5:0]
63
REF_MAT_B2P
[5:0]
ＬＲ３８６０３
15
Address
Name
Bit
Function
64
REF_MAT_R3M
[5:0]
65
REF_MAT_B3M
[5:0]
66
REF_MAT_R3P
[5:0]
67
REF_MAT_B3P
[5:0]
68
K_MAT_R1M
[7:0]
69
K_MAT_B1M
[7:0]
6A
K_MAT_R1P
[7:0]
6B
K_MAT_B1P
[7:0]
6C
K_MAT_R2M
[7:0]
6D
K_MAT_B2M
[7:0]
6E
K_MAT_R2P
[7:0]
6F
K_MAT_B2P
[7:0]
70
71
72
73
74
75
CKIL_OFF
COL_Y
COL_S
COL_H
CKI_HCL
CKI_LCL
CKI_HLGA
76
CKI_HLTI
77
78
79
CKI_HECL
CKI_EVCL
CKI_EGA
[6]
[5:0]
[7:0]
[5:0]
[7:0]
[7:0]
[7:4]
[3:0]
[5:3]
[2:0]
[7:0]
[7:0]
[7:4]
[3:0]
Matrix correction factor of R-Y negative direction when WB3 is fixed or
auto control (present WBR factor = WBR3).
Matrix correction factor of B-Y negative direction when WB3 is fixed or
auto control (present WBR factor = WBR3).
Matrix correction factor of R-Y positive direction when WB3 is fixed or
auto control (present WBR factor = WBR3).
Matrix correction factor of B-Y positive direction when WB3 is fixed or
auto control (present WBR factor = WBR3).
Matrix correction slope factor of R-Y negative direction in WB auto
control (WBR1 < present WBR < WBR2)
Matrix correction slope factor of B-Y negative direction in WB auto
control (WBR1 < present WBR < WBR2)
Matrix correction slope factor of R-Y positive direction in WB auto
control (WBR1 < present WBR < WBR2)
Matrix correction slope factor of B-Y positive direction in WB auto
control (WBR1 < present WBR < WBR2)
Matrix correction slope factor of R-Y negative direction in WB auto
control (WBR2 < present WBR < WBR3)
Matrix correction slope factor of B-Y negative direction in WB auto
control (WBR2 < present WBR < WBR3)
Matrix correction slope factor of R-Y positive direction in WB auto
control (WBR2 < present WBR < WBR3)
Matrix correction slope factor of B-Y positive direction in WB auto
control (WBR2 < present WBR < WBR3)
1: color killer OFF
Start point of luminance of color suppression in maximum AGC.
Start point of low luminance color suppression (AGC gain).
Low luminance color suppression gain.
Start level of high luminance color suppression.
Start level of low luminance color suppression.
High luminance color suppression gain.
Low luminance color suppression gain.
Timing adjustment of high luminance color suppression: -2 to 2
Timing adjustment of low luminance color suppression: -2 to 2
Start point of horizontal edge color suppression.
Start point of vertical edge color suppression.
Gain of horizontal edge color suppression.
Gain of vertical edge color suppression.
ＬＲ３８６０３
Address
Name
16
Bit
Function
NSUP_R
NSUP_B
LC_ON_YL
Y_GAM
SEL_LPF_Y
Y_SEL
[7:4]
[3:0]
[7]
[6:4]
[3]
[2]
7C
VAPT_OFF
HAPT_OFF
HAPT_SEL
[1]
[0]
[7]
7D
7E
7F
80
81
82
APT_HTIM
APT_HGA
APT_HCL
APT_VGA
APT_VCL
APT_S
APT_H
APT_Y
[6:5]
[4:0]
[6:0]
[4:0]
[6:0]
[7:0]
[5:0]
[5:0]
83
84
CKI_HCL2
CKI_ETI
85
86
87
88
LC_K1
LC_K2
LC_MAX
SETUP
89
BAS_R
8A
BAS_B
8B
OUTGA
8C
8D
SYNCLEV
MUTE_OUT
8E
SEL_FH
SEL_FR
SEL_ADCK
[7:0]
[6]
[5:3]
[2:0]
[7:0]
[7:0]
[7:0]
[6]
[5:0]
[7]
[6:0]
[7]
[6:0]
[6]
[5]
[4:0]
[7:0]
[7]
[6:0]
[7]
[6]
[5:3]
R-Y signal low level suppression
B-Y signal low level suppression
1: Execute measure against line crawl in processing luminance signal.
Select characteristics of luminance gamma.
Select characteristics of luminance LPF.
Switch luminance signal processing 0: Use only 1H 1:3 line
process
1: Vertical aperture is OFF
1: Horizontal aperture is OFF
Switch characteristics of horizontal aperture.
0:(-1+Z1)(1-Z2) 1:(-1+Z1)(1-Z1)
Timing of horizontal aperture: -1 to 1
Initial value of APT_HGA (gain of horizontal edge signal)
Suppression level of horizontal edge signal.
Initial value of APT_VGA (gain of vertical edge signal)
Suppression level of vertical edge signal.
Start point of edge signal suppression (AGC gain).
Gain of edge signal suppression.
Start point of edge signal suppression in maximum AGC gained
luminance.
Luminance suppression point of high luminance aperture.
Select level of edge signal, used in internal calculation. 1: 1/4 times
Delete timing of horizontal edge: -2 to 2
Delete timing of vertical edge: -2 to 2
Difference of 0H,2H signal allowed level, for judgment of line crawl.
Difference of R, B signal allowed level, for judgment of line crawl.
Judgment of luminance level, for judgment of line crawl.
Switch CBLK level.
Adjustment of setup level (complement of 2).
Sign of burst level R-Y 1: - direction 0: + direction
Burst level R-Y.
Sign of burst level B-Y 1: - direction 0: + direction
Burst level B-Y (sign + absolute value).
1: Mute in encoder.
1: Stop SYNC addition to analog output.
Gain of analog output (1 time at 10h).
Adjustment of SYNC level.
1: Disable output mute at power-on.
Period of mute (MUTE_OUT x 2 vertical period)
Switch attribute of FH 1: Inverted
Switch attribute of FR 1: Inverted
ADCK phase adjustment
(In using 27-million, 32-million pixels CCD 000: standard~101:300°)
(In using 41-million, 47-million pixels CCD 000: standard~101:270°）
SEL_FS
[2:0]
7A
7B
FS phase adjustment (000: standard ~ 111: 14ns delay）
ＬＲ３８６０３
Address
Name
Bit
8F
SEL_FH2
[7:6]
90
SEL_FCDS
SEL_RS
STANDBY
VARI_ENC
[5:3]
[2:0]
[6]
[5:0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
[3]
[2]
[1:0]
ANA_VARI
[6:4]
VARI_Y
[3:0]
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
KNEE
INV_DCK2
INV_DCK1
BUSY_SEL
EI_ON_SEL
HRI_SEL
VRI_SEL
IN_VRES
KEI_KEISU
ENCIN_PH
BUNSYU8_SEL
TEST
STDBY
CHG_CKIL
CHG_WB
CHG_MTX
CHG_CCD4
HG_YL_SEL
REF_AW
REF_BW
REF_CW
REF_DW
REF_AB
REF_BB
REF_CB
REF_DB
AWNC_SEL
APT_O_LIM
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[5:0]
[7:0]
17
Function
FH2 phase adjustment
(00: standard 01:1ns delay 10: 2ns delay 11: 3ns delay)
FCDS phase adjustment (000: standard ~ 111: 14ns delay)
RS phase adjustment (000: standard ~ 111: 14ns delay)
1: Standby
Period of return from standby (STANDBY x vertical period)
1: Invert OBCP clock
1: Invert DCK2
1: Invert DCK1
1: Reset auto control factor, when EEPSL is H.
1: Enable KEI pulse function.
1: Invert HRES (minus attribute)
1: Invert VRES (minus attribute)
0: Multiply VRES with CSYNC.
Gain of AGC which produce KEI pulse.
Latch encoder clock inverted.
1: Enable DFF.
Delay adjustment of addition of luminance and color modulation.
(Delay of color signal)
00: 0ck delay ~ 11: 3ck delay 1ck: original clock
Delay adjustment of addition of luminance and color modulation.
(Delay of luminance signal)
101: -3ck delay ~ 011: 3ck delay 1ck: pixel CK (complement of 2)
Timing adjustment of luminance processing.
1001: -7ck delay ~ 0111: 7ck delay 1ck: pixel CK (complement of 2)
Output 1/8 of original clock from DCK1.
Test mode. Set 0 in normal operation.
(LSI does not read EEPROM and registers are set by serial data)
Make D/A converter stanby.
Swap R and B of color killer.
Swap R and B of white balance.
Swap R and B of matrix input.
Swap U and V of digital output.
Swap YL line selection for each R and B.
Factor for white defect detection.
Factor for white defect detection.
Factor for white defect detection.
Factor for white defect detection.
Factor for black defect detection.
Factor for black defect detection.
Factor for black defect detection.
Factor for black defect detection.
ON/OFF control signal for each conditions.
Limiter of aperture output.
ＬＲ３８６０３
Address
Name
Bit
A0
A1
A2
WN00H
WN00V
WN00HV
[7:0]
[7:0]
[3:0]
A3
A4
A5
WN01H
WN01V
WN01HV
[7:0]
[7:0]
[3:0]
A6
A7
A8
WN02H
WN02V
WN02HV
[7:0]
[7:0]
[3:0]
A9
AA
AB
WN03H
WN03V
WN03HV
[7:0]
[7:0]
[3:0]
AC
AD
AE
WN04H
WN04V
WN04HV
[7:0]
[7:0]
[3:0]
AF
B0
B1
WN05H
WN05V
WN05HV
[7:0]
[7:0]
[3:0]
B2
B3
B4
WN06H
WN06V
WN06HV
[7:0]
[7:0]
[3:0]
B5
B6
B7
WN07H
WN07V
WN07HV
[7:0]
[7:0]
[3:0]
18
Function
Lower byte of horizontal coordinate 1 of white defect.
Lower byte of vertical coordinate 1 of white defect.
[3:2] Upper of vertical coordinate 1 of white defect.
[1:0] Upper of horizontal coordinate 1 of white defect.
Lower byte of horizontal coordinate 2 of white defect.
Lower byte of vertical coordinate 2 of white defect.
[3:2] Upper of vertical coordinate 2 of white defect.
[1:0] Upper of horizontal coordinate 2 of white defect.
Lower byte of horizontal coordinate 3 of white defect.
Lower byte of vertical coordinate 3 of white defect.
[3:2] Upper of vertical coordinate 3 of white defect.
[1:0] Upper of horizontal coordinate 3 of white defect.
Lower byte of horizontal coordinate 4 of white defect.
Lower byte of vertical coordinate 4 of white defect.
[3:2] Upper of vertical coordinate 4 of white defect.
[1:0] Upper of horizontal coordinate 4 of white defect.
Lower byte of horizontal coordinate 5 of white defect.
Lower byte of vertical coordinate 5 of white defect.
[3:2] Upper of vertical coordinate 5 of white defect.
[1:0] Upper of horizontal coordinate 5 of white defect.
Lower byte of horizontal coordinate 6 of white defect.
Lower byte of vertical coordinate 6 of white defect.
[3:2] Upper of vertical coordinate 6 of white defect.
[1:0] Upper of horizontal coordinate 6 of white defect.
Lower byte of horizontal coordinate 7 of white defect.
Lower byte of vertical coordinate 7 of white defect.
[3:2] Upper of vertical coordinate 7 of white defect.
[1:0] Upper of horizontal coordinate 7 of white defect.
Lower byte of horizontal coordinate 8 of white defect.
Lower byte of vertical coordinate 8 of white defect.
[3:2] Upper of vertical coordinate 8 of white defect.
[1:0] Upper of horizontal coordinate 8 of white defect.
ＬＲ３８６０３
Address
Name
Bit
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
TST_SEL31
TST_SEL32
TST_SEL33
TST_SEL1A
TST_SEL1B
TST_SEL1C
TST_SEL1D
TST_SEL1V1
TST_SEL1V2
TST_SEL1V3
TST_SEL1V4
TST_C2_OB3
TST_C2_OB4
TST_C2_DL1
TST_C2_DL2
TST_C2_YL
[7:0]
[7:0]
[0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0]
[6:0]
[7:0]
[7:0]
[5:0]
[7:0]
[2]
[1:0]
[7:0]
[7:0]
[6:0]
[7:0]
[4:0]
[7:0]
[7:0]
[7:0]
[0]
[7:0]
[7:0]
[5:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
TST_C2_GAMMA1
TST_SSG_SEL
TST_C2_GAMMA2
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
TST_C6_00
TST_C6_01
TST_C6_02
TST_C4_IO0
TST_C4_IO1
TST_C4_IO2
TST_C4_S0
TST_C4_S1
TST_C4_S2
TST_C5_T0
TST_C5_T1
TST_C5_T2
TST_SEL71
TST_SEL72
TEST_C8_00
TEST_C8_01
TEST_C8_02
TEST_C8_03
TEST_C8_04
TEST_C8_05
TEST_C8_06
19
Function
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
ＬＲ３８６０３
Address
Name
Bit
E7
E8
E9
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
TEST_C8_07
TEST_C8_08
TEST_C8_09
TST_REG1
TST_REG2
TST_REG3
TST_REG4
TST_REG5
TST_REG6
TST_REG7
TST_REG8
TST_REG9
TST_REGA
TST_REGB
TST_SEL_REG
WT_DAT30
WT_DAT31
TST_C5_WT3
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[5:0]
[7:0]
[7:0]
[7:0]
[7:0]
[5:0]
[7:0]
[6:0]
[5:0]
20
Function
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)
Test address (Set 00h)