1. technology and computing
2. electronic components

Patented July 7, 1953 I
2,644,896
UNITED STATESVPAITENT OFFICE ~
Arthur W. Lo, Haddonñeld, N. J., 'assignor to
Radio Corporation ofAmerica, a, corporation of
Delaware
i
Application July 29, 1952, serial No. 301,557
9 Claims.
1
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(c’l. soi-ss)
f
This invention relates generally to triggered
circuits, and particularly relates to a bistable
of the defects of prior art bistable transistor cir
cuits. By providing substantially zero impedance
transistor circuit employing a single currentmultiplication
transistor.
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in the external base circuit during the low cur
rent conduction state, the emitter current-emitter
voltage curve is caused to pass through the origin
of the coordinates.A However, this circuit is com
`
Various transistor circuits are known which
employ a single current-multiplication transis
paratively complicated and'may still require ad
justment of the circuit parameters to compensate
tor to provide, for example, bistable triggered cir
cuits.
Such a circuit `has been disclosed and
claimed in the patent to Eberhard 2,533,001. The
for the differences of the characteristics of indi
patent to Rack 2,579,336 discloses and claims‘a 10 vidual transistors.
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stabilized transistor triggered circuit which’rnay
It is accordingly an object of the present inven
be operated so as to have two 'stable states of
tion to provide a bistable transistor triggered cir
cuit employing a. 'single current-multiplication
transistor which is highly reliable in operation.
The latter `patent indicates that available
transistors exhibit considerable diiïerences in 15~ A furth-er object of the invention is to provide
their characteristics such, for example, as the
a; bistable transistor circuit of the `type referred
emitter current vs. emitter voltage characteris
to which will operate with ñxed `circuit constants
tic. Consequently, many of the prior art transis
regardless of differences of the characteristics of
tor triggered circuits require adjustment of the
individual transistors used therein.
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circuit constants to compensatefor the different 20
Another object of the invention is to provide
operation.
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characteristics of each individual transistor. V`The
bistable operation of a single transistor triggered
circuit depends on the negative resistance char
acteristic which appears looking into the emit
ter. The emitter characteristic contains a nega
a bistable transistor circuit which is non-critical
as to the power supply voltages and which eiîec
tively provides a high impedance in the emitter
circuit so that trigger pulses may readily be im
25 pressed on the emitter.V
tive resistance portion bounded at either end by
a positive resistance portion. ' In order to obtain
`
The bistable circuit of the present invention in
cludes a current-multiplication transistor, that is,
a circuit having two stable states of operation, it
a transistor where the collector current incre
is necessary to provide a resistor load in the
ments are larger than corresponding emitter cur
emitter circuit which may be represented as a 30 rent increments. An external network intercon
load line intersecting the emitter characteristic
nects the transistor electrodes with a common
junction point such as ground and includes a base
Consequently, in order to operate transistors of
impedance element and a collector impedance
widely varying characteristics so as to provide two
element which serves as the output load. The
stable states of current conditions thefcircuit 35 base impedance element may be a resistor and
provides for regeneration as explained in the
parameters must usually be selected so .thatthe
individual emitter current vs. emitter voltage
Eberhard patent referred to.
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once in each region, that is, three times.
A
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curves match each other as closely as possible.
In accordance with the present invention, the
The external emitter resistance must be chosen to
emitter is connected to the common junction
obtain a load line intersecting the characteristic 40 point through a non-linear resistance device such,
at three points. The load line may be shifted
for example, as a rectiñer. The rectifier is poled
without changing its slope by providing a suit
in such a manner that it is biased in the non
able emitter bias voltage. :From these consider- ‘
conducting direction when the circuit is infits
ations it will be obvious that the external emitter
state of low current conduction and is biased in
resistance must be smaller than the greatest slope 45 the conducting direction when the circuit is in
of the negative portion of the emitter character
its state of high current conduction. Conse
istic andv that the emitter bias voltage must also
quently, a load line, representing an operation
be properly selected. Hence, normallythe exter
characteristic ina graph, approaches infinity for
nal emitter resistance must be small and the value
the state of low current conduction and assumes
of the emitter bias voltage is critical. Frequent 50 a small positive value for the high current kcon
ly, it is desired to impress the'trigger pulse on
duction state, ` Thus, it is made possible that
the emitter and to that end, the emitter cir
the load line may intersect practically any tran
cuit should present a high impedance rather than
sistor characteristic at three points, `to assure
a low impedance.
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The Rack circuit is intended to overcome some 55
bistable operation.
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.
Preferably, the emitter bias is provided by ap
2,644,896
plying a voltage to the base so that the load line,
in the graph referred to, intersects the origin
of the coordinates of the emitter' characteristic.
The novel features that are considered charac
teristic of this invention are set forth, with par
ticularity in the appended claims. The invention
itself, however, both as to its organization and
method of operation, as well as additional objects
and advantages thereof, will best be understood
from the following description when read in oon
nection with the accompanying drawing in
which:
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v
Figure 1 is a circuit diagram of a bistable
transistor triggered circuit embodying the present
invention;
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Figure 2 is a graph illustrating the emitter
voltage plotted as a function of rthe emitter cur
rent; and
4
poled to become conducting upon the arrival of
a positive trigger pulse 26. A succeeding negative
trigger pulse shown at 30 is applied to input ter
minals 3l, one of which is connected to base I4
through crystal rectifier 32. Rectifier 32 is poled
to become conducting upon the arrival of a nega
tive trigger pulse 30.
,
The operation of the bistable circuit of Figure
l’will now be explained in connection with Figure
2. Curve 35 of Figure 2 illustrates a representa
tive characteristic of a transistor and shows the
emitter voltage Ve plotted as a function of the
emitter current Ie both of which have been in
dicated in Figure 1. A study of a number of
15 representative transistors has revealed that their
characteristics generally fall into the shaded area
contained between curves 35 and 38.
Conse
quently, in order to obtain bistable operation it is
necessary to provide a load line which will inter
Figure 3 is a circuit diagram of a modified
triggered circuit in accordance with the inven 20 sect either curve 35 or curve 36 at three points.
In accordance with the present invention, the
tion. v
load line is represented by the straight lines 31
Referring now to the drawing in which like ele
and 38. Line 31 represents a very high resistance,
ments are designated by the same reference
which is determined by that of rectifier 25 when
characters throughout the figures, and particu
larly to Figure l, there is illustrated' a bistable 25 biased in the non-conducting direction. On the
other hand, line 38 represents a very low resist
triggered circuit including a transistor I0. Tran
ance, which is determined by the resistance of
sistor I0 should be a current-multiplication tran
rectifier 25 when biased in the conducting direc
sistor and may, for example, be a point contact
tion.
It will now be seen that load line 31, 38 in.
transistor, that is, a transistor of the type where
the emitter and collector electrodes are both in 30 tersects curve 35 at points A and B, which repre
sent stable operation as well as at point C repre
rectifying contact with the semi-conducting
senting an unstable point of operation. The same
body II. The body I I may consist of a semi-con
load line 31, 38 intersects curve 36 at the stable
ducting material such as germanium and pref
points D and E and at the unstable point F.
erably is of the N type as will be assumed in the
Hence, it will be obvious that for any transistor,
following discussion. Emitter I2, collector I3
whose characteristic falls between curves 35. and
and base I4 are in contact with body II. The
36, bistable operation may be obtained by means
details of manufacture and the mode of opera
of the load line 31, 3B.
tion of a point contact transistor are well known
Let it be assumed, for example, that the tran
and need not be further described here.
Base resistor I5 is connected between base I4 40 sistor circuit of Figure 1 is in its stable state of
and a source of voltage such as battery IS having
its negative terminal grounded. Battery IB may
be bypassed for alternating currents by bypass
capacitor I1. Collector resistor I8 is connected
between collector I3 and another suitable source
of voltage such as battery 20 having its positive
terminal grounded. Battery 20 may also be by
passed for alternating current by capacitor 2I.
Battery 20 is poled to apply a bias voltage in the
reverse direction between collector I3 and base
low current conduction.
Let it further be as
sumed that its characteristic is represented by
curve 35. The stable low-current operation is
determined by point A. In order to trigger the
circuit into its other stable state of high current
conduction, it is necessary to apply a positive
trigger pulse to the emitter, which must be of
sufficient amplitude to carry the circuit beyond
the point G. Instead of applying a positive pulse
to the emitter, it is feasible to apply a negative
trigger pulse such as shown at 30 to base I4 or
to apply a negative trigger pulse to collector I3.
I4, while battery I6 is poled to apply a bias volt
age in the forward direction between emitter I2
As soon as the emitter voltage or current passes
and base I4.
beyond the point G, the circuit will snap over to
An output signal may be derived across collec
tor resistor I8. To this end, a pair of output 55 its other stable point B.
It may be noted from Figure 2 that during the
terminals 22 is provided, one of which is grounded,
state of low current conduction the emitter volt
while the other one is coupled through coupling
age Ve is positive with respect to ground. How
capacitor 23 to collector I3.
The transistor circuit described so far is con
ventional. In accordance with the present in
vention, the emitter I2 is grounded through a
non-linear resistance device such as rectiñer 25
which may, for example, be a crystal rectifier as
shown. Rectiñer 25 should be poled in such a
manner that it is nonconducting when emitter
I2 is positive with respect to ground, which oc
curs during the low conduction state of the cir
cuit.
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ever, on the other hand, due to the small collector
current which flows at that time, the base voltage
Vb is still more positive with respect to ground so
that the emitter voltage is actually negative with
respect to that of the base. Consequently, during
the state of low current conduction, rectifier 25
is biased in the non-conducting direction.
During the state of high current conduction
corresponding to point B on curve 35 the emitter
voltage Ve becomes negative with respect to
ground so that rectifier 25 is biased in the con
As will be more fully explained hereinafter, the
circuit may, for example, be triggered by apply 70 ducting direction. At the same time, due to the
large collector current flow, the base voltage Vb
ing trigger pulses of alternately opposite polarity
has a larger negative value so that the emitter
to the base I4. To this end, a positive trigger
has a positive voltage with respect to the base.
pulse illustrated at 26 may be applied to input
The circuit of Figure l may be triggered back
terminals 21, one of which is connected to base
I4 through a crystal rectifier 28. Rectifier 28 is 75. into its state of low current conduction by the
*2,644,89e
5
application of a negative »pulse> to the emitter.
from a high current conduction state toa low
current conduction state.- A succeeding trigger
Alternatively, a positive pulse such as pulse 26
may be applied to the base or a positive pulse
can then be triggered again into its state of high
pulse of negative polarity applied to base I4 vor
to collector I3 will then- trigger the circuit from
low current conduction’to high current conduc
tion. Hence, the circuit of the Vinvention may be
triggered either by applying trigger pulses of
alternately opposite polarity to the same elec
trode or by steering pulses of the same 'polarity
current conduction either by applying a positive 10
in succession to different electrodes.
may be applied to the collector.
rIl‘hev trigger
pulse must have such an amplitude that it will
trigger the circuit past point I-I representing the
minimum of curve 35 whereupon the circuit
snaps back to its starting point A. tThe circuit
pulse to emitter I2 or a negative pulse to the
base I4. vThe operation of the circuit is exactly
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¿bistable circuit which maybe triggered fromone
’state of stable operation` toA the ,other by means
of trigger pulses. " The vcircuit is »substantially
15 insensitive to variations of the- supply voltages
the same as described herein when the transistor
characteristic corresponds to' curve 36 instead
of to curve 35.
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There has thus -been disclosed a-‘transistor
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While it will be understood that the circuit
and may be operated with fixed circuit param
speciiications of the bistable triggered circuit of
the invention may vary according to the design
for any particular application, the following cir
eters in spite of widely varying characteristics»
of individual transistors.
The circuit of the
invention is extremely simple and reliable in
cuit speciñcations for the circuit of Figure 1 are 20 operation.
included by way of example only:
What isclaimed is: _
1. A bistable triggered circuit comprising a
Base resistor I5 _______________ __ohms__ 18,000
current-multiplication transistor including a
Collector resistor I8 ____________ __do____ 5,600
semi-conducting body, a base electrode, an`
Battery I6 _____________________ __volts__ +45
Battery 2D _____________________ __do____
-45 25 emitter electrode anda collector electrode in
Representative values of the emitter current
Ie, collector current Ic, base current Ib, emitter
voltage Ve, collector voltage Vc and base voltage
Vb (as indicated in Figure 1) are given below for 30
contact with said body, an external circuit net-.
Work interconnecting said electrodes with a com
mon junction joint and including a ñrst imped-`
ance element connected between said base elec
trode and said junction point, any output sec
high current conduction state.
ond impedance element connected between Said
collector electrode and said junction point,
both the low current conduction state and the '
High Current Con-
Low Our~
rent Con
duction .
duction
State
State
means serially connected with said first and sec
ond impedance elements for applying a bias
35 voltage in the reverse direction between said
collector and base electrodes, a non-linear re
sistance device connected between said-emitter
Emitter current L, _________________ _.ma..
+5. 2
-0. 0l
Collector current Ic ________________ __ma..
Base current Ib ____________________ ._ma__
_7. 8
+2. 4
_2.1
Y +2. 0
Emitter Voltage VB .............. __volts._
Collector Voltage Vo ._
_._do___
-l. 0
_2. 8
+3. 6
-33. 0
Base Voltage Vb __________ __
do-.__
-1. 5
+5. 5
Collector-to Base Dissipation
Einitter-to-Base Dissipation.
_mw._
_mw_-
14
1
70
0
electrode and said junction point, and means
connected between said emitter and collector
40 electrodes for applying a bias voltage in the vfor- j
ward direction between said emitter and» base
electrodes, said circuit thereby having a stable '
state of low current conduction and another
Collector Power Supply_ _ __ _
__ _mw_ _
350
90
stable state of high current conduction, and said
Base Power Supply ________________ ._mw__
110
90
device being connected so as to have a relatively
45 high resistance while said circuit is in said state
Instead of: applying alternately positive and
of low current conduction and to have a rela
negative pulses to one of the electrodes of the
tively low resistance while said circuit is in said
transistor, it is also feasible to apply pulses of
state of high current conduction.
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the same polarity alternately to different elec
2. A triggered circuit as defined in
trodes. This will now be explained in connection 50 wherein said ñrst impedance element
with Figure 3. To this end, input terminals 40
may be provided, one of which is grounded, while
3. A triggered circuit as deñned in
the other one is coupled to emitter I2 through"
wherein said output second impedance
sistor.
coupling capacitor 4I.
Another pair of input
is a resistor.
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claim .1
is a. re
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claim 1
element
l
terminals 42 may be provided, one of which is 55
4. A triggered circuit as de?ned in claim 1
grounded, while the other one is coupled through
wherein means is provided for applying trigger
capacitor 43 to base I4. Finally, input terminals
pulses to at least one of said electrodes.
44 may be provided, one of which is grounded,
5. A triggered circuit as deñned in claim 1
while the other one is coupled to collector I3
wherein said non-linear vresistance device isa
60 rectifier.
through coupling capacitor 45.
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As explained hereinbefore, a »positive pulse
6. A bistable triggered circuit comprising a
applied through terminals 40 tofemitter I2 will
current-multiplication transistor including a
trigger the circuit of the invention from .the state
semi-conducting body, a base electrode, an emit
of low current conduction to the state of high ' ter electrode and a collector electrode in contact
If a succeeding trigger 65 with said body, an external network intercon
current conduction.
pulse of positive polarity is applied to input ter
minals 42, a positive pulse is applied to base I4
which will trigger the circuit from a state of high
necting said electrodes with a junction point and
including a resistor connected between said base
electrode and said junction point, an output
impedance element connected between said col`
current conduction to a state of low current con
duction. The same result is obtained ii“ a posi-- 70 lector electrode and said junction" point, a first y
_ tive trigger pulse is applied through input termi
source ofv voltage'serially connected with said
impedance element between said collector elec
trode and said junction point for applying a
bias voltage in the reverse direction between said
viously explained, this will trigger the circuit 75 collector and base electrodes, a second source of
nals 44 to collector I3.
_
On the other hand, it is also feasible to apply
a negative trigger pulse to emitter I2. As pre
2,644,896
7
voltage serially connected with said resistor be
tween said base electrode and said junction point
for applying a bias voltage in the forward direc
tion between said emitter and base electrodes, a
rectifier connected between said emitter elec
trode and said junction point, said circuit there
by having a stable state 0f low current conduc
tion and another stable state of high current
conduction, said rectifier being poled so as to
7. A triggered circuit as defined in claim 6
wherein said rectifier is a crystal rectiñer.
8. A triggered circuit as defined in claim 6
wherein means are provided to apply trigger
pulses of alternately opposite polarity to one of
said electrodes.
9. A triggered circuit as deñned in claim 6
wherein means are provided to apply trigger
pulses of the same polarity alternately to two
be non-conducting when said circuit is in said 10 different ones of said electrodes.
stable state of low current conduction and so
as to be conducting when said circuit is in said
stable state of high current conduction, and a
pair of output terminals coupled across said im
15
Dedance element.
>ARTHUR W. Lo.
No references cited.