www.fairchildsemi.com
UC3842/UC3843/UC3844/UC3845
SMPS Controller
Features
Description
•
•
•
•
The UC3842/UC3843/UC3844/UC3845 are fixed
frequencycurrent-mode PWM controller. They are specially
designed for Off-Line and DC to DC converter applications
with minimum external components. These integrated
circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain
error amplifier, current sensing comparator and a high
current totempole output for driving a Power MOSFET. The
UC3842 and UC3844 have UVLO thresholds of 16V (on)
and 10V (off). The UC3843 and UC3845 are 8.5V(on) and
7.9V (off). The UC3842 and UC3843 can operate within
100% duty cycle. The UC3844 and UC3845 can operate
with 50% duty cycle.
Low Start up Current
Maximum Duty Clamp
UVLO With Hysteresis
Operating Frequency up to 500KHz
8-SOP
8-DIP
1
1
14-SOP
1
Internal Block Diagram
* NORMALLY 8DIP/8SOP PIN NO.
* ( ) IS 14SOP PINNO.
* TOGGLE FLIP FLOP USED ONLY IN UC3844, UC3845
Rev. 1.0.1
©2002 Fairchild Semiconductor Corporation
UC3842/UC3843/UC3844/UC3845
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply Voltage
VCC
30
V
Output Current
IO
±1
A
V(ANA)
-0.3 to 6.3
V
Analog Inputs (Pin 2.3)
ISINK (E.A)
10
mA
Power Dissipation at TA≤25°C (8DIP)
PD(Note1,2)
1200
mW
Power Dissipation at TA≤25°C (8SOP)
PD(Note1,2)
460
mW
Power Dissipation at TA≤25°C (14SOP)
PD(Note1,2)
680
mW
Storage Temperature Range
TSTG
-65 ~ +150
°C
Lead Temperature (Soldering, 10sec)
TLEAD
+300
°C
Error Amp Output Sink Current
Note:
1. Board Thickness 1.6mm, Board Dimension 76.2mm ×114.3mm, (Reference EIA / JSED51-3, 51-7)
2. Do not exceeed PD and SOA (Safe Operation Area)
Power Dissipation Curve
1200
8DIP
POWER DISSIPATION (mW)
1100
1000
900
14SOP
800
700
8SOP
600
500
400
300
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140 150
AMBIENT TEMPERATURE (℃)
Thermal Data
Characteristic
Thermal Resistance Junction-ambient
Symbol
8-DIP
8-SOP
14-SOP
Unit
Rthj-amb(MAX)
100
265
180
°C/W
Pin Array
8DIP,8SOP
COMP 1
8
VREF
COMP 1
VFB 2
7
VCC
N/C
3
6
OUTPUT
CURRENT SENSE
RT/ CT 4
2
14SOP
5 GND
14 VREF
2
13
N/C
VFB 3
12
VCC
N/C 4
11 PWR VC
CURRENT SENSE
5
10 OUTPUT
N/C
6
9
GND
RT/C T 7
8
PWR GND
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics
(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
TJ = 25°C, IREF = 1mA
4.90
5.00
5.10
V
REFERENCE SECTION
Reference Output Voltage
VREF
Line Regulation
∆VREF
12V ≤ VCC ≤ 25V
-
6
20
mV
Load Regulation
∆VREF
1mA ≤ IREF ≤ 20mA
-
6
25
mV
ISC
TA = 25°C
-
-100
-180
mA
f
TJ = 25°C
47
52
57
kHz
12V ≤ VCC ≤ 25V
-
0.05
1
%
VOSC
-
-
1.6
-
VP-P
IBIAS
-
-
-0.1
-2
µA
Short Circuit Output Current
OSCILLATOR SECTION
Oscillation Frequency
Frequency Change with
Voltage
∆f/∆VCC
Oscillator Amplitude
ERROR AMPLIFIER SECTION
Input Bias Current
Input Voltage
Open Loop Voltage Gain
VI(E>A)
GVO
Vpin1 = 2.5V
2.42
2.50
2.58
V
2V ≤ VO ≤ 4V (Note3)
65
90
-
dB
Power Supply Rejection Ratio
PSRR
12V ≤ VCC ≤ 25V (Note3)
60
70
-
dB
Output Sink Current
ISINK
Vpin2 = 2.7V, Vpin1 = 1.1V
2
7
-
mA
-0.6
-1.0
-
mA
Output Source Current
ISOURCE
Vpin2 = 2.3V, Vpin1 = 5V
High Output Voltage
VOH
Vpin2 = 2.3V, RL = 15kΩ to GND
5
6
-
V
Low Output Voltage
VOL
Vpin2 = 2.7V, RL = 15kΩ to Pin 8
-
0.8
1.1
V
GV
(Note 1 & 2)
2.85
3
3.15
V/V
Vpin1 = 5V(Note 1)
0.9
1
1.1
V
CURRENT SENSE SECTION
Gain
Maximum Input Signal
VI(MAX)
Power Supply Rejection Ratio
PSRR
Input Bias Current
IBIAS
12V ≤ VCC ≤ 25V (Note 1,3)
-
70
-
dB
-
-3
-10
µA
ISINK = 20mA
-
0.08
0.4
V
ISINK = 200mA
-
1.4
2.2
V
-
OUTPUT SECTION
Low Output Voltage
High Output Voltage
VOL
VOH
ISOURCE = 20mA
13
13.5
-
V
ISOURCE = 200mA
12
13.0
-
V
Rise Time
tR
TJ = 25°C, CL= 1nF (Note 3)
-
45
150
ns
Fall Time
tF
TJ = 25°C, CL= 1nF (Note 3)
-
35
150
ns
UC3842/UC3844
14.5
16.0
17.5
V
UC3843/UC3845
7.8
8.4
9.0
V
UC3842/UC3844
8.5
10.0
11.5
V
UC3843/UC3844
7.0
7.6
8.2
V
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold
Min. Operating Voltage
(After Turn On)
VTH(ST)
VOPR(MIN)
3
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics (Continued)
(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
PWM SECTION
Max. Duty Cycle
Min. Duty Cycle
D(Max)
UC3842/UC3843
95
97
100
%
D(Max)
UC3844/UC3845
47
48
50
%
D(MIN)
-
-
-
0
%
IST
-
-
0.45
1
mA
-
14
17
mA
30
38
-
V
TOTAL STANDBY CURRENT
Start-Up Current
Operating Supply Current
ICC(OPR)
Zener Voltage
VZ
Vpin3=Vpin2=ON
ICC = 25mA
Adjust VCC above the start threshould before setting at 15V
Note:
1. Parameter measured at trip point of latch
2. Gain defined as:
∆V pin1
A = ----------------- ,0 ≤ Vpin3 ≤ 0.8V
∆V pin3
3. These parameters, although guaranteed, are not 100 tested in production.
UC3842
Figure 1. Open Loop Test Circuit
High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors
should be connected close to pin 5 in a single point ground. The transistor and 5kΩ potentiometer are used to sample the
oscillator waveform and apply an adjustable ramp to pin 3.
4
UC3842/UC3843/UC3844/UC3845
UC3842/44 UC3843/45
Figure 2. Under Voltage Lockout
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with
a bleeder resistor to prevent activating the power switch with output leakage current.
Figure 3. Error Amp Configuration
Figure 4. Current Sense Circuit
Peak current (IS) is determined by the formula:
1.0V
I S ( MAX ) = -----------RS
A small RC filter may be required to suppress switch transients.
5
UC3842/UC3843/UC3844/UC3845
Figure 5. Oscillator Waveforms and Maximum Duty Cycle
Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the
discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both
oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:
tc = 0.55 RT CT
0.0063RT – 2.7
t D = R T C T I n  ----------------------------------------
0.0063R T – 4
Frequency, then, is: f=(tc + td)-1
1.8
ForRT > 5KΩ ,f = --------------RT CT
Figure 6. Oscillator Dead Time & Frequency
Figure 7. Timing Resistance vs Frequency
(Deadtime vs CT RT > 5kΩ)
Figure 8. Shutdown Techniques
6
UC3842/UC3843/UC3844/UC3845
Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two
diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The
PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins
1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be
reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
UC3842/UC3843
Figure 9. Slope Compensation
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch
spikes.
Temperature (°C)
Figure 10. Temperature Drift (Vref)
Temperature (°C)
Figure 11. Temperature Drift (Ist)
Temperature (°C)
Figure 12. Temperature Drift (Icc)
7
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
PARAMETER
Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the
UC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0 °C ≤ TA ≤ 70°C for the 384X; V CC = 15V
(Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5
UC2842/3/4/5
TEST CONDITIONS
UC3842/3/4/5
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
4.95
5.00
5.05
4.90
5.00
5.10
V
Reference Section
Output Voltage
TJ = 25°C, I
Line Regulation
12 ≤ VIN ≤ 25V
6
20
6
20
mV
Load Regulation
1 ≤ I0 ≤ 20mA
6
25
6
25
mV
Temp. Stability
(Note 2) (Note 7)
0.2
0.4
0.4
mV/°C
Total Output Variation
Line, Load, Temp. (Note 2)
5.18
V
O
= 1mA
4.9
5.1
Output Noise Voltage
10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2)
50
Long Term Stability
TA = 125°C, 1000Hrs. (Note 2)
5
Output Short Circuit
0.2
4.82
µV
50
25
5
25
mV
-30
-100
-180
-30
-100
-180
mA
47
52
57
47
52
57
kHz
1
%
Oscillator Section
Initial Accuracy
TJ = 25°C (Note 6)
Voltage Stability
12 ≤ VCC ≤ 25V
Temp. Stability
TMIN ≤ TA ≤ TMAX (Note 2)
Amplitude
VPIN 4 peak to peak (Note 2)
0.2
1
0.2
5
5
%
1.7
1.7
V
Error Amp Section
VPIN 1 = 2.5V
Input Voltage
2.45
Input Bias Current
2 ≤ VO ≤ 4V
AVOL
Unity Gain Bandwidth
(Note 2) TJ = 25°C
PSRR
12 ≤ VCC ≤ 25V
65
0.7
60
Output Sink Current
VPIN 2 = 2.7V, VPIN 1 = 1.1V
Output Source Current
VPIN 2 = 2.3V, VPIN 1 = 5V
VOUT High
VPIN 2 = 2.3V, RL = 15k to ground
VOUT Low
VPIN 2 = 2.7V, RL = 15k to Pin 8
2.50
2.55
-0.3
-1
90
2.42
65
1
0.7
70
60
2.50
2.58
V
-0.3
-2
µA
90
dB
1
MHz
70
dB
2
6
2
6
mA
-0.5
-0.8
-0.5
-0.8
mA
5
6
5
6
V
0.7
1.1
0.7
1.1
V
Current Sense Section
Gain
(Notes 3 and 4)
2.85
3
3.15
2.85
3
3.15
V/V
Maximum Input Signal
VPIN 1 = 5V (Note 3)
0.9
1
1.1
0.9
1
1.1
V
PSRR
12 ≤ VCC ≤ 25V (Note 3) (Note 2)
Input Bias Current
Delay to Output
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
VPIN 3 = 0 to 2V (Note 2)
70
70
dB
-2
-10
-2
-10
µA
150
300
150
300
ns
These parameters, although guaranteed, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 2 = 0.
Gain defined as
∆ VPIN 1
A=
, 0 ≤ VPIN 3 ≤ 0.8V
∆ VPIN 3
Adjust VCC above the start threshold before setting at 15V.
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
V
(max ) − VREF (min)
Temp Stability = REF
TJ (max ) − TJ (min)
VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate
temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
3
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
PARAMETER
Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for the
UC184X; −40°C ≤ TA ≤ 85°C for the UC284X; 0 °C ≤ TA ≤ 70°C for the 384X; V CC =
15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5
UC2842/3/4/5
TEST CONDITION
MIN
UC3842/3/4/5
TYP
MAX
0.1
0.4
1.5
2.2
MIN
UNITS
TYP
MAX
0.1
0.4
1.5
2.2
Output Section
Output Low Level
ISINK = 20mA
ISINK = 200mA
Output High Level
ISOURCE = 20mA
13
13.5
ISOURCE = 200mA
12
13.5
13
13.5
12
13.5
V
V
V
V
Rise Time
TJ = 25°C, C
L
= 1nF (Note 2)
50
150
50
150
ns
Fall Time
TJ = 25°C, C
L
= 1nF (Note 2)
50
150
50
150
ns
14.5
16
17.5
V
Under-voltage Lockout Section
Start Threshold
Min. Operating Voltage
After Turn On
X842/4
15
16
17
X843/5
7.8
8.4
9.0
7.8
8.4
9.0
V
X842/4
9
10
11
8.5
10
11.5
V
X843/5
7.0
7.6
8.2
7.0
7.6
8.2
V
PWM Section
Maximum Duty Cycle
X842/3
95
97
100
95
97
100
%
X844/5
46
48
50
47
48
50
%
0
%
0.5
1
mA
11
17
mA
Minimum Duty Cycle
0
Total Standby Current
Start-Up Current
Operating Supply Current
VPIN 2 = VPIN 3 = 0V
0.5
1
11
17
VCC Zener Voltage
ICC = 25mA
30
34
Note 2:
These parameters, although guaranteed, are not 100% tested in production.
Note 3:
Parameter measured at trip point of latch with VPIN 2 = 0
.
∆ VPIN 1
Note 4:
Gain defined as: A =
; 0 ≤ VPIN 3 ≤ 0.8V .
∆ VPIN 3
Note 5:
Adjust VCC above the start threshold before setting at 15V.
Note 6:
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA
4
30
34
V
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output driver is
biased to sink minor amounts of current. Pin 6 should
be shunted to ground with a bleeder resistor to prevent
activating the power switch with extraneous leakage
currents.
CURRENT SENSE CIRCUIT
Peak Current (IS) is Determined By The Formula
1.0V
ISMAX ′
RS
A small RC filter may be required to suppress switch transients.
OSCILLATOR SECTION
5
UC1842/3/4/5
UC2842/3/4/5
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
OUTPUT SATURATION CHARACTERISTICS
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a
single point ground. The transistor and 5k potentiometer
are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two
methods; either raise pin 3 above 1V or pull pin 1 below
a voltage two diode drops above ground. Either method
causes the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next
clock cycle after the shutdown condition at pin 1 and/or
3 is removed. In one example, an externally latched
shutdown may be accomplished by adding an SCR
which will be reset by cycling VCC below the lower
UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
6
APPLICATION NOTE
UC3842 PROVIDES LOW-COST CURRENT-MODE CONTROL
The fundamental challenge of power supply design
is to simultaneously realize two conflicting objectives : good electrical performance and low cost. The
UC3842 is an integrated pulse width modulator
(PWM) designed with both these objectives in mind.
This IC provides designers an inexpensive controller with which they can obtain all the performance
advantages of current-mode operation. In addition,
the UC3842 is optimized for efficient power sequencing of off-line converters and for driving increasingly popular POWERMOS.
This application note gives a functional description
of the UC3842 and suggests how to incorporate the
IC into practical power supplies. A review of currentmode control and its benefits is included and me-
thods of avoiding common pitfalls discussed. The final section presents designs of two power supplies
utilizing UC3842 control.
CURRENT-MODE CONTROL
Figure 1 shows the two-loop current-mode control
system in a typical buck regulator application. A
clock signal initiates power pulses at a fixed frequency. The termination of each pulse occurs when an
analog of the inductor current reaches a threshold
established by the error signal. In this way the error
signal actually controls peak inductor current. This
contrasts with conventional schemes in which the
error signal directly controls pulse width without regard to inductor current.
Figure 1 : Two-loop Current-mode Control System.
AN246/1188
1/16
APPLICATION NOTE
Several performance advantages result from the
use of current-mode control. First, an input voltage
feed-forward characteristic is achieved ; i.e., the
control circuit instantaneously corrects for input voltage variations without using up any of the error amplifier’s dynamic range. Therefore, line regulation is
excellent and the error amplifier can be dedicated to
correcting for load variations exclusively.
For converters in which inductor current is continuous, controlling peak current is nearly equivalent
to controlling average current. Therefore, when
such converters employ current-mode control, the
inductor can be treated as an error-voltage-controlled-current-source for the purposes of small-signal
analysis. This is illustrated by figure 2. The two-pole
control-to-output frequency response of these converters is reduced to a single pole (filter capacitor in
parallel with load) response.
One result is that the error amplifier compensation
can be designed to yield a stable closed-loop converter response with greater gain-bandwidth than
would be possible with pulse-width control, giving
the supply improved small-signal dynamic response
to changing loads. A second result is that the error
amplifier compensation circuit becomes simpler and
better behaved, as illustrated in figure 3. Capacitor
Ci and resistor Riz in figure 3a add a low frequency
zero which cancels one of the two control-to-output
poles of non-current-mode converters. For large-si-
gnal load changes, in which converter response is
limited by inductor slew rate, the error amplifier will
saturate while the inductor is catching up with the
load. During this time, Ci will charge to an abnormal
level. When the inductor current reaches its required
level, the voltage on Ci causes a corresponding error
in supply output vol-tage. The recovery time is Riz Ci,
which may be milleseconds. However, the compensation network of figure 3b can be used where current-mode control has eliminated the inductor pole.
Large-signal dynamic response is then greatly improved due to the absence of Ci.
Figure 2 : Inductor Looks Like a Current Source to
Small Signals.
Figure 3 : Required Error Amplifier Compensation for Continuous Inductor Current Designs using (a) Dutycycle Control and (b) Current-mode Control.
(a)
(b)
2/16
APPLICATION NOTE
Figure 4 : UC3842 Block Diagram.
Current limiting is simplified with current-mode control. Pulse-by-pulse limiting is, of course, inherent in
the control scheme. Furthermore, an upper limit on
the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power
semiconductor elements while ensuring reliable
supply operation.
Finally, current-mode controlled power stages can
be operated in parallel with equal current sharing.
This opens the possibility of a modular approach to
power supply design.
FUNCTIONAL DESCRIPTION
A block diagram of the UC3842 appears in figure 4.
This IC will operate from a low impedance DC source of 10 V to 30 V. Operation between 10 V and 16
V requires a start-up bootstrap to a voltage greater
than 16 V in order to overcome the undervoltage lockout. VCC is internally clamped to 34 V for operation
from higher voltage current-limited sources
(ICC ≤ 30 mA).
stage. Figure 5a shows that the UVLO turn-on and
turn-off thresholds are fixed internally at 16 V and 10
V respectively. The 6 V hysteresis prevents VCC
oscillations during power sequencing. Figure 5b
shows supply current requirements. Start-up current
is less than 1 mA for efficient bootstrapping from the
rectified input of an off-line converter, as illustrated
by figure 6. During normal circuit operation, VCC is
developed from auxiliary winding WAUX with D1 and
CIN. At start-up, however, CIN must be charged to 16
V through RIN. With a start-up current of 1 mA, RIN
can be as large as 100 kΩ and still charge CIN when
VAC = 90 V RMS (low line). Power dissipation in RIN
would then be less than 350 mW even under high
line (VAC = 130 V RMS) conditions.
During UVLO, the UC3842 output driver is biased to
a high impedance state. However, leakage currents
(up to 10 µA), if not shunted to ground, could pull
high the gate of a POWERMOS. A 100 kΩ shunt, as
showing in figure 6, will hold the gate voltage below
1V.
UNDER-VOLTAGE LOCKOUT (UVLO)
This circuit insures that VCC is adequate to make the
UC3842 fully operational before enabling the output
3/16
APPLICATION NOTE
Figure 5 : (a) Under-voltage Lockout and (b) Supply Current Requirements.
(a)
(b)
Figure 6 : Providing Power to the UC3842.
OSCILLATOR
The UC3842 oscillator is programmed as shown in
figure 7a. Oscillator timing capacitor CT is charged
from VREF (5 V) through RT, and discharged by an
internal current source. Charge and discharge times
are given by :
tc ≈ 0.55 RT CT
4/16
0.0063 RT – 2.7
)
0.0063 RT – 4.0
1
frequency, then, is : f =
tc + td
td ≈ RT CT ln (
For RT > 5 kΩ, td is small compared to tc, and :
1
1.8
f≈
≈
RT CT
0.55 RT CT
APPLICATION NOTE
During the discharge time, the internal clock signal
blanks the output to the low state. Therefore, td limits
maximum duty cycle (DMAX) to :
tc
td
DMAX =
=1–
tc + td
τ
where τ = 1/f = switching period.
The timing capacitor discharge current is not tightly
controlled, so td may vary somewhat over tempera-
ture and from unit to unit. Therefore, when very precise duty cycle limiting is required, the circuit of figure 7b is recommended.
One or more UC3842 oscillators can be synchronized to an external clock as shown in figure 8. Noise
immunity is enhanced if the free-running oscillator
frequency (f = 1/(tc + td)) is programmed to be
~ 20 % less than the clock frequency.
Figure 7 : (a) Oscillator Timing Connections and (b) Circuit for Limiting Duty Cycle.
(a)
Figure 8 : Synchronization to an External Clock.
ERROR AMPLIFIER
The error amplifier (E/A) configuration is shown in
figure 9. The non-inverting input is not brought out
(b)
tc
(tH + tL)
tH = 0.693 (RA + RB) C
tL = 0.693 RB C
DMAX =
to a pin, but is internally biased to 2.5 V ± 2 %. The
E/A output is available at pin 1 for external compensation, allowing the user to control the converter’s
closed-loop frequency response.
Figure 10a shows an E/A compensation circuit suitable for stabilizing any current-mode controlled topology except for flyback and boost converters
operating with continuous inductor current. The feedback components add a pole to the loop transfer
function at fp = 1/2 πRf Cf. Rf and Cf are chosen so
that this pole cancels the zero of the output filter capacitor ESR in the power circuit. Ri and Rf fix the lowfrequency gain. They are chosen to provide as much
gain as possible while still allowing the pole formed
by the output filter capacitor and load to roll off the
loop gain to unity (0dB) at f ≈ fswitching/4. This technique insures converter stability while providing good
dynamic response.
Continuous-inductor-current boost and flyback converters each have a right-half-plane zero in their
transfer function. An additional compensation pole
is needed to roll off loop gain at a frequency less than
that of the RHP zero. Rp and Cp in the circuit of figure
10b provide this pole.
5/16
APPLICATION NOTE
The E/A output will source 0.5 mA and sink 2 mA. A
lower limit for Rf is given by :
VE/A OUT(max) – 2.5 V 6 V – 2.5 V
Rf (MIN) ≈
=
= 7 kΩ
0.5 mA
0.5 mA
E/A input bias current (2 µA max) flows through Ri,
resulting in a DC error in output voltage (Vo) given
by :
It is therefore desirable to keep the value of Ri as low
as possible.
Figure 11 shows the open-loop frequency response
of the UC3842 E/A. The gain represent an upper limit on the gain of the compensated E/A. Phase lag
increases rapidly as frequency exceeds 1 MHz due
to second-order poles at ∼ 10 MHz and above.
∆ Vo(max) = (2 µA) Ri
Figure 9 : UC3842 Error Amplifier.
Figure 10 : (a) Error Amplifier Compensation Addition Pole and (b) Needed for Continu
ous Inductor-current Boost ad Flyback.
(a)
(b)
6/16
Figure 11 : Error Amplifier Open-loop Frequency
Response.
APPLICATION NOTE
CURRENT SENSING AND LIMITING
The UC3842 current sense input is configured as
shown in figure 12. Current-to-voltage conversion is
done externally with ground-referenced resistor RS.
Under normal operation the peak voltage across RS
is controlled by the E/A according to the following relation :
VC – 1.4 V
VRS (pk) =
3
where : VC = control voltage = E/A output voltage.
RS can be connected to the power circuit directly or
through a current transformer, as figure 13 illustrates. While a direct connection is simpler, a transformer can reduce power dissipation in RS, reduce
errors caused by the base current, and provide level
shifting to eliminate the restraint of ground-reference sensing. The relation between VC and peak
current in the power stage is given by :
VRS(pk)
N
)=
(VC – 1.4)
i(pk) = N (
RS
3 RS
For purposes of small-signal analysis, the controlto-sensed-current gain is :
i(pk)
N
=
VC
3 RS
When sensing current in series with the power transistor, as shown in figure 13, current waveform will
often have a large spike at its leading edge. This is
due to rectifier recovery and/or interwinding capacitance in the power transformer. If unattenuated, this
transient can prematurely terminate the output pulse. As shown, a simple RC filter is usually adequate
to suppress this spike. The RC time constant should
be approximately equal to the current spike duration
(usually a few hundred nanoseconds).
The inverting input to the UC3842 current-sense
comparator is internally clamped to 1 V (figure 12).
Current limiting occurs if the voltage at pin 3 reaches
this threshold value, i.e. the current limit is defined
by :
N.1V
iMAX =
RS
where : N = current sense transformer turns ratio.
= 1 when transformer not used.
Figure 12 : Current Sensing.
7/16
APPLICATION NOTE
Figure 13 : Transformer-coupled Current Sensing.
Figure 14 : Output Cross-conduction.
TOTEM-POLE OUTPUT
The UC3842 has a single totem-pole output. The
output transistors can be operated to ± 1 A peak current and ± 200 mA average current. The peak current is self-limiting, so no series current-limiting
resistor is needed when driving a power MOS gate.
Cross-conduction between the output transistors is
minimal, as figure 14 shows. The average added power due to cross-conduction with Vi = 30 V is only
80 mW at 200 kHz.
Figures 15-17 show suggested circuits for driving
POWERMOS and bipolar transistors with the
UC3842 output. The simple circuit of figure 15 can
be used when the control IC is not electrically isolated from the power MOS. Series resistor R1 provides
damping for a parasitic tank circuit formed by the power MOS input capacitance and any series wiring inductance. Resistor R2 shunts output leakage
currents (10 µA maximum) to ground when the under-voltage lockout is active. Figure 16 shows an
isolated power MOS drive circuit which is appropriate when the drive signal must be levelshifted or transmitted across an isolation boundary. Bipolar
transistors can be driven effectively with the circuit
of figure 17. Resistors R1 and R2 fix the on-state
base current. Capacitor C1 provides a negative base
current pulse to remove stored charge at turn-off.
SHUTDOWN TECHNIQUES
PWM LATCH
This flip-flop, shown in figure 4, ensures that only a
single pulse appears at the UC3842 output in any
one oscillator period. Excessive power transistor
dissipation and potential saturation of magnetic elements are thereby averted.
8/16
Shutdown of the UC3842 can be accomplished by
two methods ; either raise pin 3 above 1 V or pull pin
1 below 1 V. Either method causes the output of the
PWM comparator to be high (refer to block diagram,
figure 4). The PWM latch is reset dominant so that
the output will remain low until the first clock pulse
following removal of the shutdown signal at pin 1 or
pin 3. As shown in figure 18, an externally latched
shutdown can be accomplished by adding an SCR
which will be reset by cycling VCC below the lower
under-voltage lockout threshold (10 V). At this point
all internal bias is removed, allowing the SCR to reset.
Figure 15 : Direct POWERMOS Drive.
APPLICATION NOTE
Figure 16 : Isolated POWERMOS Drive.
Figure 17 : Bipolar Drive with Negative Turn-off Bias.
AVOIDING COMMON PITFALLS
Current-mode controlled converters can exhibit performance peculiarities under certain operating conditions. This section explains these situations and
how to correct them when using the UC3842.
SLOPE COMPENSATION PREVENTS INSTABILITIES
It is well documented that current-mode controlled
converters can exhibit subharmonic oscillations
when operated at duty cycles greater than 50 %.
Fortunately, a simple technique (usually requiring
only a single resistor to implement) exists which corrects this problem and at the same time improves
converter performance in other respects. This "slope compensation" technique is described in detail in
Reference 6. It should be noted that "duty cycle"
here refers to output pulse width divided by oscillator
period, even in push-pull designs where the transformer period is twice that of the oscillator. Therefore, push-pull circuits will almost always require
slope compensation to prevent subharmonic oscillation.
9/16
APPLICATION NOTE
Figure 18 : Shutdown Achieved by
(a) Pulling Pin 3 High
(b) Pulling Pin 1 Low.
(a)
(b)
most easily derived from the control chip oscillator
as shown in figure 20a. The sawtooth slope in figure
19b is m = m2/2. This particular slope value is significant in that it yields "perfect" current-mode control ;
i.e. with m2/2 the average inductor current follows
the control signal so that, in the small-signal analysis, the inductor acts as a controlled current source.
All current-mode controlled converters having continuous inductor current therefore benefit from this
amount of slope compensation, whether or not they
operate above 50 % duty.
More slope is needed to prevent subharmonic oscillations at high duty cycles. With slope m = m2, such
oscillations will not occur if the error amplifier gain
(AV(E/A)) at half the switching frequency (fs/2) is kept
below a threshold value (reference 6) :
π 2 CO
AV (E/A)
<
4τ
m = m2
f = fs/2
where :
Figure 19 illustrates the slope compensation technique. In figure 19a the uncompensated control voltage and current sense waveforms are shown as a
reference. Current is often sensed in series with the
switching transistor for buck-derived topologies. In
this case, the current sense signal does not track the
decaying inductor current when the transistor is off,
so dashed lines indicate this inductor current. The
negative inductor current slope is fixed by the values
of output voltage (Vo) and inductance (L) :
diL
VL
– VF – Vo
– (VF + Vo)
=
=
=
dt
L
L
L
where : VF = forward voltage drop across the freewheeling diode. The actual slope (m2) of the dashed
lines in figure 19a is given by :
RS
diL
– RS (VF + Vo)
.
=
m2 =
N
dt
NL
where : RS and N are defined as the "Current Sensing" section of this paper.
In figure 19b, a sawtooth voltage with slope m has
been added to the control signal. The sawtooth is
synchronized with the PWM clock, and practice is
10/16
Co = sum of filter and load capacitance
τ = 1/fs
Slope compensation can also improve the noise immunity of a current-mode controlled supply. When
the inductor ripple current is small compared to the
average current (as in figure 19a), a small amount
of noise on the current sense or control signals can
cause a large pulse-width jitter. The magnitude of
this jitter varies inversely with the difference in slope
of the two signals. By adding slope as in figure 19b,
the jitter is reduced. In noisy environments it is sometimes necessary to add slope m > m2 in order to
correct this problem. However, as m increases beyond m = m2/2, the circuit becomes less perfectly
current controlled. A complex trade-off is then required ; for very noisy circuits the optimum amount of
slope compensation is best found empirically.
Once the required slope is determined, the value of
RSLOPE in figure 20a can be calculated :
3m=
∆VRAMP
∆ tRAMP
RSLOPE =
. AV(E/A) =
3mτ
1.4
0.7 V
τ/2
(
RSLOPE
ZF | fs
)=
1.4
τ
(
RSLOPE
ZF | fs
)
(ZF | fs) = 2.1 . m . τ . ZF | fs
where : ZF| fs is the E/A feedback impedance at the
switching frequency.
For m = mL : ∆τRAMP
Rs (VF + VO)
) ZF | fs
RSLOPE = 1.7 τ (
NL
APPLICATION NOTE
Figure 19 : Slope Compensation Waveforms :
(a) No Comp.
(b) Comp. Added to Control Voltage.
(c) Comp. Added to Current Sense.
Note that in order for the error amplifier to accurately
replicate the ramp, ZF must be constant over the frequency range fs to at least 3 fs.
In order to eliminate this last constraint, an alternative method of slope compensation is shown in figures 19c and 20b. Here the artificial slope is added
to the current sense waveform rather than subtracted from the control signal. The magnitude of the added slope still relates to the downslope of inductor
current as described above. The requirement for
RSLOPE is now :
m=
∆VRAMP
Rf
0.7
Rf
(
)=
(
)
∆tRAMP
Rf + RSLOPE
τ/2
Rf + RSLOPE
RSLOPE =
For m = m2 :
RSLOPE = Rf (
1.4 NL
– 1)
RS (VF + VO) τ
RSLOPE loads the UC3842 RT/CT terminal so as to
cause a decrease in oscillator frequency. If RSLOPE >> RT then the frequency can be corrected by decreasing RT slightly. However, with RSLOPE ≤ 5 RT
the linearity of the ramp degrades noticeably, causing over-compensation of the supply at low duty cycles. This can be avoided by driving RSLOPE with an
emitter-follower as shown in figure 21.
1.4 Rf
1.4
– Rf = Rf (
– 1)
mτ
mτ
11/16
APPLICATION NOTE
Figure 20 : Slope Compensation Added (a) to Control Signal or (b) to Current Sense Waveform.
(a)
(b)
Figure 21 : Emitter-follower Minimizes Load at
RT/CT Terminal.
NOISE
As mentioned earlier, noise on the current sense or
control signals can cause significant pulse-width jitter, particularly with continuous-inductor-current designs. While slope compensation helps alleviate this
problem, a better solution is to minimize the amount
of noise. In general, noise immunity improves as impedance decrease at critical points in a circuit.
One such point for a switching supply is the ground
line. Small wiring inductances between various
ground points on a PC board can support commonmode noise with sufficient amplitude to interfere with
correct operation of the modulating IC. A copper
ground plane and separate return lines for high-current paths greatly reduce common-mode noise.
12/16
APPLICATION NOTE
Note that the UC3842 has a single ground pin. High
sink currents in the output therefore cannot be returned separately.
Ceramic bypass capacitors (0.1 µF) from VI and
VREF to ground will provide low-impedance paths for
high frequency transients at those points. The input
to the error amplifier, however, is a high-impedance
point which cannot be bypassed without affecting
the dynamic response of the power supply. Therefore, care should be taken to lay out the board in
such a way that the feedback path is far removed
from noise generating components such as the
power transistor(s).
Figure 22a illustrates another common noise-induced problem. When the power transistor turns off, a
noise spike is coupled to the oscillator RT/CT terminal. At high duty cycles the voltage at RT/CT is approaching its threshold level (∼ 2.7 V, established by
the internal oscillator circuit) when this spike occurs.
A spike of sufficient amplitude will prematurely trip
the oscillator as shown by the dashed lines. In order
to minimize the noise spike, choose CT as large as
possible, remembering that deadtime increases
with CT. It is recommended that CT never be less
than ∼ 1000 pF. Often the noise which causes this
problem is caused by the output (pin 6) being pulled
below ground at turn-off by external parasitics. This
is particularly true when driving POWERMOS. A diode clamp from ground to pin 6 will prevent such output noise from feeding to the oscillator. If these
measures fail to correct the problem, the oscillator
frequency can always be stabilized with an external
clock. Using the circuit of figure 8 results in an RT/CT
waveform like that of figure 22b. Here the oscillator
is much more immune to noise because the ramp
voltage never closely approaches the internal threshold.
Figure 22 : (a) Noise on Pin 4 Can Cause Oscillator to Pre-trigger.
(b) With External Sync. Noise Does not Approach threshold Level.
(a)
MAXIMUM OPERATING FREQUENCY
Since output deadtime varies directly with CT, the restraint on minimum CT (1000 pF) mentioned above
results in a minimum deadtime varies for the
UC3842. This minimum deadtime varies with RT
and therefore with frequency, as shown in figure 23.
Above 100 kHz, the deadtime significantly reduces
the maximum duty cycle obtainable at the UC3842
output (also show in figure 23). Circuits not requiring
large duty cycles, such as the forward converter and
flyback topologies, could operate as high as 500
kHz. Operation at higher frequencies is not recom-
(b)
mended because the deadtime become less predictable.
The speed of the UC3842 current sense section
poses an additional constraint on maximum operating frequency. A maximum current sense delay of
400 ns represents 10 % of the switching period at
250 kHz and 20 % at 500 kHz. Magnetic components must not saturate as the current continues to
rise during this delay period, and power semiconductors must be chosen to handle the resulting peak
currents. In short, above ∼ 250 kHz, may of the advantages of higher-frequency operation are lost.
13/16
APPLICATION NOTE
Figure 23 : Deadtime and Maximum Obtainable Duty-cycle vs. Frequency with Minimum Recommended
CT.
CIRCUIT EXAMPLES
1. OFF-LINE FLYBACK
Figure 24 shows a 25 W multiple-output off-line flyback regulator controlled with the UC3842. This regulator is low in cost because it uses only two
magnetic elements, a primary-side voltage sensing
technique, and an inexpensive control circuit. Specifications are listed below.
SPECIFICATIONS :
Line Isolation :
3750 V
Switching Frequency :
40 kHz
Efficiency @ full load :
70 %
Input Voltage
95 VAC to 130 VAC
(50Hz/60Hz)
Output Voltage :
A. + 5 V, 5 % : 1 A to 4 A load
Ripple voltage : 50 mV
P-P Max.
B. + 12 V, 3 % : 0.1 A to 0.3 A
load
Ripple voltage : 100 mV
P-P Max
C. – 12 V, 3 % 0.1 A to 0.3 A
load
Ripple voltage : 100 mV
P-P Max
14/16