Product Brief
embedded Programmable Logic
Origami™
The Design Software Environment for Menta eFPGA Core® technology
Menta® Origami™ is the design software environment for Menta eFPGA Core® technology. Origami
offers a powerful integrated solution for logic design using all Menta eFPGA Core IP generated by Menta
Origami Designer™. The Graphical User Interface (GUI) makes the tool easy to use for users of all
expertise levels. The windows-based interface and menu scheme guides users through the design and
compilation process. From fully automatic to user-guided design implementation, Origami software
supports the needs of logic designs and logic designers from simple to complex projects.
Design entry is made simple using software from leading third-party vendors. Origami software offers high-level,
target-independent design with efficient logic compilation, delivering unprecedented performance for the most
complex designs. Origami has been developed to operate efficiently in all third-party environments and is
optimized for high level Verilog and VHDL synthesis and design. Origami converts users design entry into
functionally equivalent logic gates on Menta eFPGA Core IP, with optimized speed and area.
Figure 1: Origami™ design flow
Key Benefits
Technology mapping, placement
and routing
Timing analysis easier and faster
Easy design export to simulators
Scripting with TCL
Introduction
Origami is a robust and complete
design software environment from
entering the design to programming
your eFPGA Core IP. It uses proven
implementation engine technology
developed exclusively for Menta
technology. This unique software
allows
you
to
target
all
programmable logic architecture
generated with the Menta Origami
Designer™ tool.
Origami includes a complete set of
tools covering all aspects of
programmable logic design.
Synthesis
Origami
uses
industry-leading
synthesis solution for design entry,
Synopsys Design Compiler or
Cadence Encounter RTL Compiler.
The synthesizer converts HDL
(VHDL/Verilog) code into a gatelevel netlist, represented in terms
of MGTECH component library
(Menta’s library containing basic
primitives).
Mapping
Mapping stage is intended to
translate the gate-level netlist into
specific architecture resources, like
LUT (Look-Up Table). The process
attempts to reduce area, delay, or a
combination of area and delay in
Origami
the final LUT network. Detailed
information on targeted resources
are included in the Origami DB. The
output physically represents the
design mapped to the selected
programmable logic architecture
and ready for placement and
routing.
Placement
functionally verify generated result
after processes, like Mapping,
Placement and Routing.
Bitstream
The bitstream is produced for the
targeted eFPGA Core IP architecture
and it’s used to configure the
architecture that will execute the
desired function.
Scripting TCL
Origami software allows capabilities
for scripting the design flow.
Origami specific TCL commands are
available for all design phases.
Figure 2: Physical placement view
Placement process takes a mapped
design and decides the physical
locations and inter-connections of
each logic blocks in the design. The
placement objective is to minimize
the total wire-length required to
complete the routing.
Routing
Timing Analysis
Figure 4: Detailed Timing Analysis
view
The Timing Analyzer performs static
timing analysis for verification that
the delay along a given path meets
timing requirements.
Availability
Figure 3: Physical routing view
Routing phase provides connection
between I/O blocks and building
blocks of the architecture, and
between one block to another. It
takes
into
accounts
timing
constraints setup by the designer.
The Menta Origami software is now
available on Red Hat Linux X86 64bit platform.
For more information about Menta
products or support services, visit
us on the web at: www.menta.fr or
contact [email protected].
Throughout the flow, Origami
generates simulation models after
every step, which is used to
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June 2012, Rev. 2
Menta SAS ∙ Cap Omega ∙ CS39521 ∙ Rond-Point Benjamin Franklin ∙ 34960 Montpellier Cedex 2 ∙ France
© 2012 Menta SAS. All rights reserved. eFPGA Creator, eFPGA Core, eFPGA Programmer, Menta and the Menta logo are registered trademarks of
Menta SAS. Origami and Origami Designer are trademarks of Menta SAS. All other trademarks and tradenames are the property of their respective holders.