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Computer Science Department
CS220 (Spring 2013)
Third Exam
EXAM IS OPEN BOOKS AND NOTES
ANSWER ALL QUESTIONS
TIME ALLOWED
Question
1
2
3
4
5
Total
60 MINUTES
Possible Points
20
25
15
20
20
100
Points Scored
Question 1] [20 points] Provide short answers (3 sentences or less) to each of the
following questions
Explain the tradeoffs involved in each of the following design decisions.
(a) What type of cache misses does a set-associative cache help with compared to a direct
mapped cache?
(b) Why is it that the Memory Management Unit (MMU) is implemented in Hardware?
Could we have implemented it in software?
(c) Describe a program that would have very bad memory performance on a system with
a typical memory hierarchy.
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Question 2] [25 points]: This problem concerns the way virtual addresses are translated into
physical addresses. Imagine a system with the following parameters:
• Virtual addresses are 18 bits wide.
• Physical addresses are 15 bits wide.
• The page size is 512 bytes.
• The TLB is direct mapped with 16 total entries.
The contents of the TLB and the first 32 entries of the page table are shown as follows. All
numbers are given in hexadecimal.
TLB
Index
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Tag
16
1B
10
0F
1F
11
03
1D
06
0F
0A
1F
02
18
0C
1E
PPN
10
2D
0F
1E
31
1F
2B
33
08
19
09
20
13
3D
0B
34
Valid
1
1
1
0
1
0
1
0
1
1
0
1
0
1
0
0
VPN
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
PPN
17
28
14
0B
26
13
0F
10
1C
25
31
16
01
15
0C
14
Page Table
Valid VPN
1
10
1
11
1
12
0
13
0
14
1
15
1
16
1
17
0
18
1
19
0
1A
1
1B
1
1C
1
1D
0
1E
0
1F
PPN
26
17
0E
10
2D
1B
31
12
23
04
0C
2B
1E
3E
27
18
Valid
0
0
1
1
0
0
1
0
1
0
1
1
0
1
1
1
3
Part 1
(a) The diagram below shows the format of a virtual address. Please indicate the following fields by labeling the diagram: (if a field does not exist, do not draw it on the diagram): VPO The virtual page offset VPN The virtual page number TLBI The TLB index bits TLBT The TLB tag 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (b) The diagram below shows the format of the physical address. Please indicate the following fields by labeling the diagram: (if a field does not exist, do not draw it on the diagram PPO The physical page offset PPN The physical page number 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (c) How many entries are there in the page table? (we’re only showing you the first 32) 4
(d) For the given virtual addresses, please indicate the TLB entry accessed and the physical address. Indicate whether the TLB misses and whether a page fault occurs. If there is a page fault, enter “-‐“ for “PPN” and leave the physical address blank. Virtual address 0x0F32F 1. Virtual address (one bit per box) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2. Address translation Parameter Value Parameter Value VPN 0x TLB Hit? (Y/N) TLB Index 0x Page Fault? (Y/N) TLB Tag 0x PPN 0x 3. Physical address:________________________________________________________ (e) Given that a generated virtual address got translated to physical address 0x7b12, what was the virtual address? Break it down below and show how it was translated into 0x7b12 4. Virtual address (one bit per box) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5. Address translation Parameter Value Parameter Value VPN 0x TLB Hit? (Y/N) TLB Index 0x Page Fault? (Y/N) TLB Tag 0x PPN 0x 5
Question 3 [15 points] Consider a 64 byte 2-way set associative cache with 8 byte cache
lines. Memory addresses are 8-bits. The cache uses LRU replacement (if a set is full, the
least recently accessed way is removed when a new cache line is accessed).
(a) The boxes below represent the bit-format of an address. In each box, indicate which field
that bit represents (it is possible that a field does not exist) by labeling them as follows:
B: Block Offset
S: Set Index
T: Cache Tag
7 6 5 4 3 2 1 0 (b) The table below shows a trace of load addresses accessed in the data cache. Assume the
cache is initially empty. For each row in the table, please complete the two rightmost
columns, indicating (i) the set number (in decimal notation) for that particular load, and (ii)
whether that loads hits (H) or misses (M) in the cache (circle either “H” or “M” accordingly).
Load
No.
Hex
Address
Binary
Address
Set Number?
(in Decimal)
Hit or Miss
(Circle one)
1
43
0100 0011
H
M
2
B2
1011 0010
H
M
3
40
0100 0000
H
M
4
F9
1111 1001
H
M
5
B2
10110010
H
M
6
93
1001 0011
H
M
7
D0
1101 0000
H
M
8
B0
1011 0000
H
M
9
67
0110 0111
H
M
10
07
0000 0111
H
M
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Question 4 [20 points] This problem tests your understanding of Unix process control.
Consider the following C program (with line numbers). For space reasons, we are not
checking error return codes, so assume that all functions return normally. Recall that the
waitpid call causes the part to wait until the child process with process id matching the first
argument (pid) exits before proceeding.
1 int main() {
2 int count = 0;
3 int pid;
4
5 if( !(pid = fork()) ) {
6
while((count < 2) && (pid = fork()) ) {
7
count++;
8
printf("%d", count)
9
}
10
if (count > 0) {
11
printf("%d", count);
12
}
13 }
14 if(pid) {
15
waitpid(pid, NULL, 0);
16
count = count << 1;
17
printf("%d", count)
18
}
19 }
Its important to recall that in C, evaluating a condition such as (A && B) evaluates A first, and only if it is true is B evaluated. (a) How many total processes including the original process will be present?
(b) List all the possible outputs.
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Question 5 [20 points] In this problem, you will perform cache analysis for three code
sequences. Assume a very small direct mapped 16 byte data cache with two cache lines. We
assume a float requires 4 bytes. Drawing the cache
helps.
For each code sequence, we assume a cold cache and that the array X is cache aligned (that is,
X[0] is loaded into the the beginning of the first cache line. All other variables are held in
registers.
Recall that miss rate is defined as #misses/#accesses
1. Code 1:
float X[8], t = 0; for(int j = 0; j < 2; j++) for(int i = 0; i < 8; i++) t += X[i]; Answer the following:
(a) Miss rate:____________________
(b) What types ot types of locality does this code have with respect to this cache?
2. Code 2:
float X[8], t = 0; for(int j = 0; j < 2; j++) { for(int i = 0; i < 7; i += 2) t += X[i]; for(int i = 1; i < 8; i += 2 t += X[i]; } Answer the following:
(a) Miss rate:__________________________
(b) What types ot types of locality does this code have with respect to this cache?
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3. Code 3:
float X[8], float t = 0; for(i = 0; i < 2; i++) for(k = 0; k < 2; k++) for(j = 0; j < 4; j++) t += X[j + i*4]; Answer the following:
(a) Miss rate:____________________________________
(b) What types ot types of locality does this code have with respect to this cache?
4. Changing Cache:
All three code fragments above perform the same computation. Assume you could change the
code any way you want to perform the same computation and also change the cache as you
wish.
(a) What is the minimum number of cache misses achievable?
(b) How would the cache look like to achieve this?
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