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ACOE301 – Computer
Architecture II
Useful Information
• Instructor: Lecturer K. Tatas
• Office hours : Mo5, Tu3, We6-8, Fri5
– E-mail: [email protected]
– http://staff.fit.ac.cy/com.tk
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Prerequisites: ACOE201
Lectures/week: 3 + 1 (Lab)
ECTS: 5 (x25 h) = 125h
Evaluation: 60% Final exam – 20% Labs/Quizzes
– 20% midterm/assignment
• Enrollment key: ACOE301_FALL12
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Course Objectives
• Introduce students to computer
architecture and organization with
emphasis on
– performance metrics and cost,
– instruction set architectures,
– RISC processor design,
– Pipelining
– memory hierarchy.
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Course Outcomes
• By the end of this course students should
be able to:
– Understand the computer architecture and
organization of modern processors.
– Further advance their knowledge in designing
computer architecture systems using
Assembly, C/C++ and VHDL.
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Course Description
• Introduction to Computer Architecture:
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Organisation and abstraction of a computer.
ISAs.
Emerging computer architecture technologies.
Processor, caches, memory and I/O devices.
• Instruction Set Architecture (ISA):
– Specifications, classes, registers, memory addressing
and addressing modes.
– The complete MIPS architecture and in-depth
analysis.
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Course Description
• RISC Processor Design:
– Full ALU design of the MIPS processor.
– Multiplication and division algorithms in
hardware.
– Single-cycle, multi-cycle datapath and
controller design.
• Performance Metrics:
– Measuring performance and metrics.
– Improve performance, clock cycles, CPI,
instructions count, MIPS, MOPS, MFLOPs.
– Benchmarks. Amdahl's Law.
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Course Description
• Pipelining:
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Single-cycle, Multi-cycle versus Pipeline.
Structural, data and control hazards.
Forwarding.
Exceptions.
MIPS R3000 pipeline and design of a pipelined processor.
Loop unrolling in scalar and superscalar computer systems.
Software pipelining.
• Memory Hierarchy:
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Locality and memory hierarchy.
SRAM and DRAM.
Memory organization.
Advanced cache memory.
Virtual memory.
Protection. Translation Lookaside Buffer (TLB).
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Textbook and References
• Paterson, Hennessy, Computer
Organisation and Design: the
Hardware/Software Interface, Morgan
Kaufman, 2003.
• M. Mano, C. R. Kime, Logic and
Computer Design Fundamentals,
Prentice Hall, 2004
• J. P. Hayes, Computer Architecture and
Organization, 3Ed, McGraw Hill., 1998
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The task of the computer designer
• Determine what attributes are important for a new machine, then
design a machine to maximize performance while staying within cost
and power constraints.
• This task has many aspects
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instruction set design
functional organization
logic design
implementation.
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integrated circuit design
Packaging
Power
cooling
• Optimizing the design requires familiarity with a very wide range of
technologies:
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Compilers
operating systems
logic design
packaging.
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Basic Terminology
• instruction set architecture refers to is the part of the processor that
is visible to the programmer or compiler writer. The instruction set
architecture serves as the boundary between the software and
hardware
• Hardware is used to refer to the specifics of a machine
– detailed logic design
– Implementation/packaging technology
• Often a line of machines contains machines with identical instruction
set architectures and nearly identical organizations, but they differ in
the detailed hardware implementation.
– For example, the Pentium II and Celeron are nearly identical, but offer
different clock rates and different memory systems,
• In this course the word computer architecture is intended to cover all
three aspects of computer design
– instruction set architecture
– Organization
– hardware
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HISTORICAL PERSPECTIVE
• 1st generation: 1945 - 1955
– Tubes, punchcards
• 2nd generation: 1955 - 1965
– transistors
• 3rd generation: 1965 – 1980
– Integrated circuits
• 4th generation: 1980 –
– PCs and workstations
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1st generation (1945-1955)
• Programming was done in machine
language
• No operating system
• Programming and maintenance done
by one group of people
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ENIAC –
The first electronic computer (1946)
18,000
tubes
300 Tn
170 KWatt
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2nd generation (1955-1965)
• Transistor-based
• Fairly reliable
• Clear distinction between designers,
manufacturers, users, programmers,
and support personnel.
• Only afforded by governments,
universities or large companies
(millions $)
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2nd generation (1955-1965)
• Program was first written on paper
(FORTRAN) and then punched into
cards
• Cards were then delivered to the user.
• Mostly used for scientific and technical
calculations
– Solving differential equations
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3rd generation (1965-1980)
• IC-based operation
• IBM develops compatible systems
• Tradeoffs in performance, memory, I/O
etc).
• Greater MHz/$
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4th generation (1980-1990)
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LSI-based PCs
Significantly cheaper
User-friendly software
2 dominant operating systems:
– MS DOS: IBM PC (8088, 80286, 80386,
80486)
– UNIX: RISC workstations
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5th generation (1990-)
• PC networks
• Network operating systems
• Each machine runs its own operating
system
• Users don’t care where their programs
are being executed
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Famous quotes
• “Future computers may weigh less than 1,5
tn”, (1949)
• “I believe there is a world market for five
computers”, T. Watson, IBM CEO (1943)
• “There is no particular reason why
someone would want a computer at home”,
K. Oslon, president of DEC (1974)
• “640Κbytes of memory should be enough
for anybody”, B. Gates, president of
Microsoft (1981)
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Microprocessor Technologies
(Orthogonal)
• VLSI technology
• Computer Architecture
• Compiler technology
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Moore’s Law
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Intel 4004 Micro-Processor
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Recent advances
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The Future: 3D ICs
Battery
MEMS
DNA Chip
Image Sensor
RF Chip
Processor
• 3D integration: One
chip
Memory
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Computer Architecture
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RISC vs. CISC
– Complex instruction set computer (CISC):
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Large instruction set;
Complex operations;
Complex addressing modes;
Complex hardware, long execution time;
Minimum number of instructions needed for a given task;
Easy to program, simpler compiler.
– Reduced instruction set computer (RISC):
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Small instruction set;
Simple instructions to allow for fast execution (fewer steps);
Large number of registers;
Only read/write (load/store) instructions should access the main memory,
one MM access per instruction;
Simple addressing modes to allow for fast address computation;
Fixed-length instructions with few formats and aligned fields to allow for
fast instruction decoding;
increased compiler complexity and compiling time;
simpler and faster hardware implementation, pipelined architecture.
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RISC vs. CISC example
• CISC (M68000)
– Add the content of MM location pointed to by A3 to the
component of an array starting at MM address 100. The index
number of the component is in A2. The content of A3 is then
automatically incremented by 1.
• RISC (MIPS)
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Memory Architecture
• Von Neumann: Common memory for data
and instructions
• Harvard: Separate data and instruction
memories
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Von Neumann Memory
Architecture
address
memory
data
200
PC
CPU
200
ADD r5,r1,r3
ADD IR
r5,r1,r3
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Harvard Memory Architecture
address
data memory
data
address
program memory
PC
CPU
data
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Pipelining
• Dividing the processing task into stages,
which are executed in parallel
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Application-Specific Processors
• Processors optimized for a specific
application domain
– DSP processors
• Multiplier/accumulator in ALU, Harvard memory
architecture
– Multimedia processors
• Image processing/video hardware accelerators
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Assembler/Compiler
technologies
• Increased productivity by using high-level
languages
• For critical tasks and embedded systems,
assembly is commonly used
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References
• Weste, Harris, CMOS VLSI Design: A
Circuits and Systems Perspective
• Patterson, Hennessy - Computer
Organization and Design; The HardwareSoftware Interface, 2E (Morgan
Kaufman, 1997)
• Fundamentals Of Computer Organization
And Architecture (2005) Wiley
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