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Chapter 7
Microsequencer Control Unit
Design
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Chapter Outline
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•
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Basic Microsequencer Design
Very Simple Microsequencer
Relatively Simple Microsequencer
Reducing the Number of
Microinstructions
• Microcoded vs. Hardwired Control
• Pentium Microprocessor
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Micro-stuff
• Micro-operations
• Microinstructions
• Microprograms
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Generic Microsequencer
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Generating the Next Address
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•
•
•
Current Address + 1
Address specified by microinstruction
Microsubroutine register
Mapping hardware
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Microinstruction Format
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Types of Microcode
• Horizontal
• Vertical
• Direct
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A Very Simple Microsequencer
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Mapping Logic
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State Addresses
State
Address
FETCH1
FETCH2
FETCH3
ADD1
0000 (0)
0001 (1)
0010 (2)
1000 (8)
ADD2
AND1
AND2
1001 (9)
1010 (10)
1011 (11)
JMP1
INC1
1100 (12)
1110 (14)
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Partial Microcode
State
FETCH1
Address
0000 (0)
SEL
0
ADDR
0001
FETCH2
FETCH3
ADD1
0001 (1)
0010 (2)
1000 (8)
0
1
0
0010
XXXX
1001
ADD2
AND1
AND2
1001 (9)
1010 (10)
1011 (11)
0
0
0
0000
1011
0000
JMP1
INC1
1100 (12)
1110 (14)
0
0
0000
0000
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Micro-operations
Mnemonic
ARPC
Micro-Operation
ARPC
ARDR
PCIN
PCDR
ARDR[5..0]
PCPC + 1
PCDR[5..0]
DRM
IRDR
PLUS
AND
DRM
IRDR[7..6]
ACAC + DR
ACAC^DR
ACIN
ACAC + 1
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Preliminary Horizontal
Microcode
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Optimized Horizontal
Microcode
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Control Signals
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Generic Vertical Microcode
Decoding
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Field Assignments
• Simultaneous micro-operations in
different fields
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Field Assignments
• Simultaneous micro-operations in
different fields
• Include a NOP in each field
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Field Assignments
• Simultaneous micro-operations in
different fields
• Include a NOP in each field
• Distribute remaining micro-operations to
minimize total number of bits required
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Field Assignments
• Simultaneous micro-operations in
different fields
• Include a NOP in each field
• Distribute remaining micro-operations to
minimize total number of bits required
• Group together micro-operations that
modify the same register
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Micro-operation Assignments
M1
NOP
DRM
M2
NOP
PCIN
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Micro-operation Assignments
M1
NOP
DRM
ACIN
PLUS
AND
M2
NOP
PCIN
PCDR
ARPC
AIDR
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Micro-operation Assignments
M1
NOP
DRM
ACIN
PLUS
AND
AIDR
M2
NOP
PCIN
PCDR
ARPC
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Micro-operation Assignments
and Field Values
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Vertical Microcode
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Micro-operation Generation
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Nanoinstructions
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Directly Generating Control
Signals
• Output control signals instead of microoperations
• No external decoding required
• No external hardware required to
generate control signals
• More difficult to code
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Preliminary Direct Microcode
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Optimize Direct Microcode
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Relatively Simple
Microsequencer
• No changes to
– Instruction set
– Data paths
– ALU
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Modified State Diagram
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Microsequencer Hardware
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State Assignments
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Condition Values
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Branch Types
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Branch Logic
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Partial Microcode
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Partial Microcode (continued)
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Micro-operations
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Horizontal Microcode
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Horizontal Microcode
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Horizontal Microcode
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Control Signals
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Reducing the Number of
Microinstructions
• Microsubroutines
• Microcode Jumps
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Microsubroutines
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Revised State Assignments
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Microsequencer with
Microsubroutines
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Revised Branch Types
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Revised Branch Logic
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Revised Microcode
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Microcode Jumps
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Revised Microcode
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Microprogrammed Control vs.
Hardwired Control
• Complexity of the instruction set
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Microprogrammed Control vs.
Hardwired Control
• Complexity of the instruction set
• Ease of modification
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Microprogrammed Control vs.
Hardwired Control
• Complexity of the instruction set
• Ease of modification
• Clock speed
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The Pentium Microprocessor
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Summary
•
•
•
•
Basic Microsequencer Design
Very Simple Microsequencer
Relatively Simple Microsequencer
Reducing the Number of
Microinstructions
• Microcoded vs. Hardwired Control
• Pentium Microprocessor
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