Introduction

Gate-level minimization refers to the design task of
finding an optimal gate-level implementation of
Boolean functions describing a digital circuit.

Optimization methods:
 Boolean Algebra
 K-Map
 Tabulation method
1
The Map Method

The complexity of the digital logic gates
 The complexity of the algebraic expression

Logic minimization
 Algebraic approaches
 The Karnaugh map
 A simple straight forward procedure
 A pictorial form of a truth table
 Applicable if the number of variables < 7

A diagram made up of squares
 Each square represents one minterm
2
Two-Variable Map

A two-variable map
Four minterms
x' = row 0; x = row 1
y' = column 0; y = column 1



A truth table in square
diagram
Fig.(a): xy = m3
Fig. (b): x+y = x'y+xy' +xy =
m1+m2+m3



3
A Three-variable Map
A three-variable map




Eight minterms
The Gray code sequence
Any two adjacent squares in the map differ by only on variable



4
Primed in one square and unprimed in the other
e.g., m5 and m7 can be simplified
m5+ m7 = xy'z + xyz = xz (y'+y) = xz
A Three-variable Map



5
m0 and m2 (m4 and m6) are adjacent
m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'
Example 3.1
Simplify the Boolean function F(x, y, z) = S(2, 3, 4, 5)


F(x, y, z) = S(2, 3, 4, 5) = x'y + xy'
F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy‘= x y
6
Example 3.2
Simplify F(x, y, z) = S(3, 4, 6, 7)


7
F(x, y, z) = S(3, 4, 6, 7) = yz+ xz'
Four adjacent Squares
Consider four adjacent squares




8
2, 4, and 8 squares can be simplified
m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) =
x'z' + xz‘ = z'
m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z
+ xz = z
Example 3.3
 Simplify F(x, y, z) = S(0, 2, 4, 5, 6)

F(x, y, z) = S(0, 2, 4, 5, 6) = z'+ xy'
9
Example 3.4

let F = A'C + A'B + AB'C + BC
a) Express it in sum of minterms.
b) Find the minimal sum of products expression.
Ans:
F(A, B, C) =S(1, 2, 3, 5, 7) = C + A'B
10
Four-Variable Map

The map


11
16 minterms
Combinations of 2, 4, 8, and 16 adjacent squares
Example 3.5

Simplify F(w, x, y, z) = S(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
F = y'+w'z'+xz'
12
Example 3.6

Simplify F = ABC + BCD + ABCD + ABC
ABC + BCD + ABCD + ABC= BD + BC +ACD
13
Prime Implicants

Prime Implicants
 All the minterms are covered.
 Minimize the number of terms.
 A prime implicant: a product term obtained by
combining the maximum possible number of
adjacent squares (combining all possible maximum
numbers of squares).
 Essential P.I.: a minterm is covered by only one
prime implicant.
 The essential P.I. must be included.
14
Prime Implicants

Consider F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)


15
The simplified expression may not be unique
F = BD+B'D'+CD+AD = BD+B'D'+CD+AB'
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'
Five-Variable Map

Map for more than four variables becomes complicated

16
Five-variable map: two four-variable map (one on the top of the
other).
Example 3.7

Simplify F = S(0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
F = A'B'E'+BD'E+ACE
17
Example 3.7 (cont.)

Another Map for Example 3-7
18
Example 3.8
 Simplify F = S(0, 1, 2, 5, 8, 9, 10) into (a) sum-of-products form,
and (b) product-of-sums form:
a) F(A, B, C, D)= S(0, 1, 2, 5, 8,
9, 10) = B'D'+B'C'+A'C'D
b) F' = AB+CD+BD'
» Apply DeMorgan's theorem;
F=(A'+B')(C'+D')(B'+D)
F(A, B, C, D)= S(0, 1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D
19
Example 3.8 (cont.)

Gate implementation of the function of Example 3.8
Sum-of products form
20
Product-of sums form
Sum-of-Minterm Procedure

Consider the function defined in Table 3.2.

In sum-of-minterm:
F ( x, y, z) = (1,3,4,6)


21
Using the complement of F:
F’(x, y, z)= S(0,2,5,7)
F ( x, y, z ) = ( x  z)( x  z )
Sum-of-Minterm Procedure

Consider the function defined in Table 3.2.

Combine the 1’s:
F ( x, y, z ) = xz  xz

Combine the 0’s :
F'( x, y , z ) = xz  xz 
22
Don't-Care Conditions

The value of a function is not specified for certain
combinations of variables


The don't-care conditions can be utilized in logic
minimization


BCD; 1010-1111: don't care
Can be implemented as 0 or 1
Example 3.9: simplify F(w, x, y, z) = S(1, 3, 7, 11, 15)
which has the don't-care conditions d(w, x, y, z) = S(0, 2, 5)
23
Example 3.9 (cont.)



24
F = yz + w'x'; F = yz + w'z
F = S(0, 1, 2, 3, 7, 11, 15) ; F = S(1, 3, 5, 7, 11, 15)
Either expression is acceptable
3.3 Simplify the following Boolean expression using threevariable maps: d) F(x, y, z) = x y z + x\ y\ z + x y\ z\
y
yz
xyz
0
x y\ z \
x\
y\
z
00
x
x
1
01
11
1
1
1
z
25
10
3.5 Simplify the following Boolean expression using fourvariable maps: a) F(w,x, y, z) = S(1,4,5,6,12,14,15)
y
yz
00 01 11 10
wx
x z\
00
1
w\ y\ z
01
wxy
1
1
1
x
11
1
1
w
10
F =w\ y\ z+w x y+ x z\
26
z
1
3.5 Simplify the following Boolean expression using fourvariable maps: b) F(A,B,C,D)= S(1,5,9,10,11,14,15)
C
CD
AB
AC
A\ C\ D
00
01
00
1
01
1
11
10
A B\ D
B\
C\
D
B
11
F
27
1
1
1
A
10
=A\C\D+AC+(AB\D
1
or
B\C\D)
1
D
3.5 Simplify the following Boolean expression using fourvariable maps: c) F(w,x, y, z) = S(0,1,4,5,6,7,8,9)
y
yz
wx
00
01
w\ x
00
1
1
x\ y\
01
1
1
11
10
1
1
x
11
w
F =x\y\+w\x
10
1
1
z
28
3.5 Simplify the following Boolean expression using fourvariable maps: d) F(A,B,C,D)= S(0,2,4,5,6,7,8,10,13,15)
C
CD
AB
B\ D\
BD
00
00
1
01
1
01
11
10
1
1
1
1
B
A\ B
11
A\ D\
F
29
1
A
10
=B\D\+BD+(A\B
1
or
A\D\)
1
1
D
3.6 Simplify the following Boolean expression using fourvariable maps: a)A\B\C\D\+AC\D\+B\CD\+A\BCD+BC\D
C
CD
AB
B\ D\
00
A\ B D
01
00
01
11
1
10
1
1
1
B
A B C\
11
1
10
1
1
A
F
30
=B\D\+A\BD+ABC\
1
D
3.6 Simplify the following Boolean expression using fourvariable maps: b) x\z+w\xy\+w(x\y+xy\)
= x\z+w\xy\+wx\y+wxy\
y
yz
wx
x\ z
00
x y\
01
00
1
01
11
1
1
10
1
x
w x\ y
11
1
1
w
10
1
1
F =x\ z+xy\+wx\y
z
31
1
3.6 Simplify the following Boolean expression using fourvariable maps: c)A\B\C\D\+A\CD\+AB\D\+ABCD+A\BD
C
CD
B\ D\
A\
00
AB
00
BD
11
1
01
BCD
01
10
1
1
1
1
B
A\ B C
A\
F
C
D\
11
A
=B\D\+A\BD+BCD+(A\BC
32
1
10
or
1
A\CD\)
1
D
3.6 Simplify the following Boolean expression using fourvariable maps: d)A\B\C\D\+AB\C+B\CD\+ABCD\+BC\D
C
CD
AB
00
A\ B\ D\
B C\ D
00
01
11
1
01
10
1
1
B
A C D\
11
A B\ C
1
1
A
10
F
33
=A\B\D\+BC\D+ACD\+AB\C
1
D
1
3.10 Simplify the following Boolean function by first finding the
essential prime implicants: c) F(A,B,C,D)=S(1,3,4,5,10,11,12,13,14,15)
C
CD
B C\ essential
AB
A C essential
00
A\ B\ D non-essential
01
B\
C D non-essential
Redundant
F =BC\+AC+A\B\D
34
1
01
11
1
1
10
1
B
A B non-essential
A\ C\ D non-essential
00
11
1
1
1
1
1
1
A
10
D
3.15 Simplify the following Boolean function, together with don't care
condition d, and then express the simplified function in sum-ofminterms form: b) F(A,B,C,D)=Sm(0,6,8,13,14) + Sd(2,4,10)
C
CD
AB
B\ D\
00
01
11
10
00
1
x
01
X
1
C D\
A B C\ D
11
1
1
A
F = B\D\+ABC\D+CD\
10
1
x
F = S(0,2,6,8,10,13,14)
D
35
B
3.15 Simplify the following Boolean function, together with don't care
condition d, and then express the simplified function in sum-ofminterms form: c) F(A,B,C,D)=Sm(4,5,7,12,13,14) +Sd(1,9,11,15)
C
CD
B C\
AB
00
00
BD
01
AB
01
11
x
1
1
1
B
11
1
1
x
x
x
A
F = BC\+BD+AB
F = S(4,5,7,12,13,14,15)
10
D
36
10
1
Logic Diagram of a
Quadruple NAND Chip
Quadruple N AND Chip
37
NAND and NOR Implementation

NAND gate is a universal gate

38
Can implement any digital system
NAND Gate

Two graphic symbols for a NAND gate
39
Example 3.10

Example 3-10: implement F(x, y, z) =
F ( x, y, z ) = (1,2,3,4,5,7)
40
F ( x, y, z ) = xy   xy  z
Procedure with Two Levels NAND

The procedure
 Simplified in the form of sum of products;
 A NAND gate for each product term; the inputs to
each NAND gate are the literals of the term (the
first level);
 A single NAND gate for the second sum term (the
second level);
 A term with a single literal requires an inverter in
the first level.
41
Multilevel NAND Circuits

Boolean function implementation

AND-OR logic → NAND-NAND logic


AND → AND + inverter
OR: inverter + OR = NAND
F = A(CD + B) + BC
42
NAND Implementation
F = (AB +AB)(C+ D)
43
NOR Implementation


NOR function is the dual of NAND function.
The NOR gate is also universal.
44
Graphic Symbols for a NOR Gate
Example: F = (A + B)(C + D)E
F = (A + B)(C + D)E
45
Example
F = (AB +AB)(C + D)
46
AND-OR-Invert Implementation

AND-OR-INVERT (AOI) Implementation



NAND-AND = AND-NOR = AOI
F = (AB+CD+E)'
F' = AB+CD+E (sum of products)
AND-OR-INVERT circuits, F = (AB +CD +E)
47
OR-AND-Invert Implementation

OR-AND-INVERT (OAI) Implementation



OR-NAND = NOR-OR = OAI
F = ((A+B)(C+D)E)'
F' = (A+B)(C+D)E (product of sums)
OR-AND-INVERT circuits, F = ((A+B)(C+D)E)'
48
Other Two-level Implementations
49
Exclusive-OR Function

Exclusive-OR (XOR)


Exclusive-NOR (XNOR)


(xy)' = xy + x'y'
Some identities







xy = xy'+x'y
x0 = x
x1 = x'
xx = 0
xx' = 1
xy' = (xy)'
x'y = (xy)'
Commutative and associative


50
AB = BA
(AB) C = A (BC) = ABC
Exclusive-OR Implementations

Implementations

51
(x'+y')x + (x'+y')y = xy'+x'y = xy
Odd Function



52
ABC = (AB'+A'B)C' +(AB+A'B')C = AB'C'+A'BC'+ABC+A'B'C =
S(1, 2, 4, 7)
XOR is a odd function → an odd number of 1's, then F = 1.
XNOR is a even function → an even number of 1's, then F = 1.
XOR and XNOR

Logic diagram of odd and even functions
Logic Diagram of Odd and Even Functions
53
Four-variable Exclusive-OR function

Four-variable Exclusive-OR function

54
ABCD = (AB'+A'B)(CD'+C'D) =
(AB'+A'B)(CD+C'D')+(AB+A'B')(CD'+C'D)
Parity Generation and Checking
55
Parity Generation and Checking
56
Parity Generation and Checking

Parity Generation and Checking


A parity bit: P = xyz
Parity check: C = xyzP


57
C=1: one bit error or an odd number of data bit error
C=0: correct or an even # of data bit error