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Multichannel ISM Band
FSK/GFSK/OOK/GOOK/ASK Transmitter
ADF7012
FEATURES
GENERAL DESCRIPTION
Single-chip, low power UHF transmitter
75 MHz to 1 GHz frequency operation
Multichannel operation using fractional-N PLL
2.3 V to 3.6 V operation
On-board regulator
Programmable output power
−16 dBm to +14 dBm, 0.4 dB steps
Data rates: dc to 179.2 kbps
Low current consumption
868 MHz, 10 dBm, 21 mA
433 MHz, 10 dBm, 17 mA
315 MHz, 0 dBm, 10 mA
Programmable low battery voltage indicator
24-lead TSSOP
The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK
UHF transmitter designed for short-range devices (SRDs). The
output power, output channels, deviation frequency, and modulation type are programmable by using four, 32-bit registers.
The fractional-N PLL and VCO with external inductor enable
the user to select any frequency in the 75 MHz to 1 GHz band.
The fast lock times of the fractional-N PLL make the ADF7012
suitable in fast frequency hopping systems. The fine frequency
deviations available and PLL phase noise performance facilitates
narrow-band operation.
There are five selectable modulation schemes: binary frequency
shift keying (FSK), Gaussian frequency shift keying (GFSK),
binary on-off keying (OOK), Gaussian on-off keying (GOOK),
and amplitude shift keying (ASK). In the compensation register,
the output can be moved in <1 ppm steps so that indirect compensation for frequency error in the crystal reference can be made.
APPLICATIONS
Low cost wireless data transfer
Security systems
RF remote controls
Wireless metering
Secure keyless entry
A simple 3-wire interface controls the registers. In power-down,
the part has a typical quiescent current of <0.1 μA.
FUNCTIONAL BLOCK DIAGRAM
PRINTED
INDUCTOR
OSC1
OSC2
CLKOUT
L1
L2
CVCO
VDD
OOK\ASK
÷CLK
VCO
PA
÷R
DVDD
PFD/
CHARGE
PUMP
RFOUT
RFGND
DGND
CREG
OOK\ASK
+FRACTIONAL N
FSK\GFSK
Σ-Δ
LDO
REGULATOR
TxCLK
LE
DATA
SERIAL
INTERFACE
CLK
CE
PLL LOCK
DETECT
FREQUENCY
COMPENSATION
BATTERY
MONITOR
CENTER
FREQUENCY
AGND
MUXOUT
MUXOUT
RSET
04617-0-001
TxDATA
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
ADF7012
TABLE OF CONTENTS
Features .............................................................................................. 1 GFSK Modulation ...................................................................... 14 Applications ....................................................................................... 1 Power Amplifier ......................................................................... 14 General Description ......................................................................... 1 GOOK Modulation .................................................................... 15 Functional Block Diagram .............................................................. 1 Output Divider ........................................................................... 16 Revision History ............................................................................... 2 MUXOUT Modes....................................................................... 16 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 17 Timing Characteristics..................................................................... 5 Choosing the External Inductor Value .................................... 17 Absolute Maximum Ratings............................................................ 6 Choosing the Crystal/PFD Value ............................................. 17 Transistor Count ........................................................................... 6 Tips on Designing the Loop Filter ........................................... 18 ESD Caution .................................................................................. 6 PA Matching................................................................................ 18 Pin Configuration and Function Descriptions ............................. 7 Transmit Protocol and Coding Considerations ..................... 18 Typical Performance Characteristics ............................................. 8 Application Examples .................................................................... 19 315 MHz ........................................................................................ 8 315 MHz Operation ................................................................... 20 433 MHz ........................................................................................ 9 433 MHz Operation ................................................................... 21 868 MHz ...................................................................................... 10 868 MHz Operation ................................................................... 22 Circuit Description ......................................................................... 12 915 MHz Operation ................................................................... 23 PLL Operation ............................................................................ 12 Register Descriptions ..................................................................... 24 Crystal Oscillator ........................................................................ 12 Register 0: R Register ................................................................. 24 Crystal Compensation Register ................................................ 12 Register 1: N-Counter Latch ..................................................... 25 Clock Out Circuit ....................................................................... 12 Register 2: Modulation Register ............................................... 26 Loop Filter ................................................................................... 13 Register 3: Function Register .................................................... 27 Voltage-Controlled Oscillator (VCO) ..................................... 13 Outline Dimensions ....................................................................... 28 Voltage Regulators ...................................................................... 13 Ordering Guide .......................................................................... 28 FSK Modulation.......................................................................... 13 REVISION HISTORY
6/09—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Table 4 ............................................................................ 7
Changes to Crystal Oscillator Section ......................................... 12
Changes to Loop Filter Section ..................................................... 13
Changes to GFSK Modulation Section ........................................ 14
Changes to Choosing the External Inductor Value Section ..... 17
Changes to Component Values—Crystal: 3.6864 MHz ............ 20
Changes to Component Values—Crystal: 4.9152 MHz ............ 21
Changes to Component Values—Crystal: 4.9152 MHz ............ 22
Changes to Component Values—Crystal: 10 MHz.................... 23
Added Register Headings Throughout ........................................ 24
Changes to Ordering Guide .......................................................... 28
10/04—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADF7012
SPECIFICATIONS
DVDD = 2.3 V – 3.6 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C.
Table 1.
Parameter
RF OUTPUT CHARACTERISTICS
Operating Frequency
Phase Frequency Detector
MODULATION PARAMETERS
Data Rate FSK/GFSK
Data Rate ASK/OOK
Deviation FSK/GFSK
GFSK BT
ASK Modulation Depth
OOK Feedthrough (PA Off )
POWER AMPLIFIER PARAMETERS
Maximum Power Setting, DVDD = 3.6 V
Maximum Power Setting, DVDD = 3.0 V
Maximum Power Setting, DVDD = 2.3 V
Maximum Power Setting, DVDD = 3.6 V
Maximum Power Setting, DVDD = 3.0 V
Maximum Power Setting, DVDD = 2.3 V
PA Programmability
POWER SUPPLIES
DVDD
Current Consumption
315 MHz, 0 dBm/5 dBm
433 MHz, 0 dBm/10 dBm
868 MHz, 0 dBm/10 dBm/14 dBm
915 MHz, 0 dBm/10 dBm/14 dBm
VCO Current Consumption
Crystal Oscillator Current
Consumption
Regulator Current Consumption
Power-Down Current
REFERENCE INPUT
Crystal Reference Frequency
B Version
Unit
75/1000
FRF/128
MHz min/max VCO range adjustable using external inductor; divide-by-2, -4, -8
options may be required
Hz min
179.2
64
kbps
Kbps
PFD/214
511 × PFD/214
0.5
25
−40
−80
Hz min
Hz max
typ
dB max
dBm typ
dBm typ
FRF = FVCO
FRF = FVCO/2
14
13.5
12.5
14.5
14
13
0.4
dBm
dBm
dBm
dBm
dBm
dBm
dB typ
FRF = 915 MHz, PA is matched into 50 Ω
FRF = 915 MHz, PA is matched into 50 Ω
FRF = 915 MHz, PA is matched into 50 Ω
FRF = 433 MHz, PA is matched into 50 Ω
FRF = 433 MHz, PA is matched into 50 Ω
FRF = 433 MHz, PA is matched into 50 Ω
PA output = −20 dBm to +13 dBm
2.3/3.6
V min/V max
8/14
10/18
14/21/32
16/24/35
1/8
190
mA typ
mA typ
mA typ
mA typ
mA min/max
μA typ
280
0.1/1
μA typ
μA typ/max
3.4/26
MHz min/max
Single-Ended Reference Frequency
3.4/26
MHz min/max
Crystal Power-On Time 3.4 MHz/26
MHz
Single-Ended Input Level
1.8/2.2
ms typ
CMOS levels
Conditions/Comments
Using 1 MHz loop bandwidth
Based on US FCC 15.247 specifications for ACP; higher data rates
are achievable depending on local regulations
For example, 10 MHz PFD − deviation min = ±610 Hz
For example, 10 MHz PFD − deviation max = ±311.7 kHz
DVDD = 3.0 V, PA is matched into 50 Ω, IVCO = min
VCO current consumption is programmable
CE to clock enable valid
Refer to the LOGIC INPUTS parameter. Applied OSC 2,
oscillator circuit disabled.
Rev. A | Page 3 of 28
ADF7012
Parameter
PHASE-LOCKED LOOP PARAMETERS
VCO Gain
315 MHz
433 MHz
868 MHz
B Version
Unit
Conditions/Comments
22
24
80
MHz/V typ
MHz/V typ
MHz/V typ
VCO divide-by-2 active
VCO divide-by-2 active
88
0.3/2.0
−65/−70
MHz/V typ
V min/max
dBc
IVCO is programmable
0.3
0.9
1.5
2.1
mA typ
mA typ
mA typ
mA typ
Referring to DB[7:6] in Function Register
Referring to DB[7:6] in Function Register
Referring to DB[7:6] in Function Register
Referring to DB[7:6] in Function Register
−85
−83
−80
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA
PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA
PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA
915 MHz
Phase Noise (Out of Band)1
315 MHz
433 MHz
−80
dBc/Hz typ
PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA
−103
−104
dBc/Hz typ
dBc/Hz typ
PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA
PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA
868 MHz
915 MHz
Harmonic Content (Second) 2
Harmonic Content (Third)2
−115
−114
−20
−30
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA
PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA
FRF = FVCO
Harmonic Content (Others)2
Harmonic Content (Second)2
Harmonic Content (Third)2
−27
−24
−14
dBc typ
dBc typ
dBc typ
Harmonic Content (Others)2
−19
dBc typ
0.7 × DVDD
V min
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
0.2 × DVDD
±1
4.0
V max
μA max
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
DVDD − 0.4
V min
CMOS output chosen
500
0.4
μA max
V max
IOL = 500 μA
915 MHz
VCO Tuning Range
Spurious (IVCO Min/Max)
Charge Pump Current
Setting [00]
Setting [01]
Setting [10]
Setting [11]
Phase Noise (In band) 1
315 MHz
433 MHz
868 MHz
LOGIC INPUTS
Input High Voltage, VINH
Output High Current, IOH,
Output Low Voltage, VOL
1
2
FRF = FVCO/N (where N = 2, 4, 8)
Measurements made with NFRAC = 2048.
Measurements made without harmonic filter.
Rev. A | Page 4 of 28
ADF7012
TIMING CHARACTERISTICS
DVDD = 3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t4
Test Conditions/Comments
LE setup time
Data-to-clock setup time
Data-to-clock hold time
Clock high duration
Clock low duration
Clock-to-LE setup time
LE pulse width
t5
CLK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
04617-0-002
t6
LE
Figure 2. Timing Diagram
Rev. A | Page 5 of 28
ADF7012
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
This device is a high performance RF integrated circuit with an
ESD rating of 1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Table 3.
Parameter
DVDD to GND
(GND = AGND = DGND = 0 V)
Digital I/O Voltage to GND
Analog I/O Voltage to GND
Operating Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +3.9 V
TRANSISTOR COUNT
35819 (CMOS)
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +85°C
150°C
150.4°C/W
ESD CAUTION
215°C
220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 28
ADF7012
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD 1
24
CREG2
CREG1 2
23
RSET
22
AGND
21
DVDD
20
RFOUT
CPOUT 3
TxDATA 4
TxCLK 5
TSSOP
ADF7012
19 RFGND
TOP VIEW
DGND 7 (Not to Scale) 18 VCOIN
OSC1 8
17
CVCO
OSC2 9
16
L2
CLKOUT 10
15
L1
CLK 11
14
CE
DATA 12
13
LE
04617-0-003
MUXOUT 6
Figure 3. Pin Configuration
Table 4. Pin Functional Descriptions
Pin No. Mnemonic
1
DVDD
2
CREG1
3
CPOUT
4
5
TxDATA
TxCLK
6
MUXOUT
7
8
9
DGND
OSC1
OSC2
10
CLKOUT
11
CLK
12
DATA
13
LE
14
CE
15
L1
16
17
L2
CVCO
18
VCOIN
19
20
RFGND
RFOUT
21
DVDD
22
23
24
AGND
RSET
CREG2
Description
Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin.
A 1 μF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor improves
regulator power-on time, but may cause higher spurious noise.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current
changes the control voltage on the input to the VCO.
Digital data to be transmitted is input on this pin.
GFSK and GOOK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7012. The
clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on the falling edge of TxCLK.
The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit.
Provides the Lock_Detect Signal. This signal is used to determine if the PLL is locked to the correct frequency. It also
provides other signals, such as Regulator_Ready, which is an indicator of the status of the serial interface regulator, and a
voltage monitor (see the MUXOUT Modes section for more information).
Ground for Digital Section.
The reference crystal should be connected between this pin and OSC2.
The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving this pin
with CMOS levels, and powering down the crystal oscillator bit in software.
A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive several
other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance
CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches,
the latch being selected using the control bits.
Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1μA. Register values are lost when
CE is low and the part must be reprogrammed once CE is brought high.
Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the value of the
inductor to be connected between L1 and L2.
Connected to external printed or discrete inductor.
A 22 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012. This
capacitor is necessary to ensure stable VCO operation.
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the
tuning voltage, the higher the output frequency.
Ground for Output Stage of Transmitter.
The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output should be
impedance matched using suitable components to the desired load. See the PA Matching section.
Voltage supply for VCO and PA section. This should have the same supply as DVDD (Pin 1), and should be between 2.3 V and
3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin.
Ground Pin for the RF Analog Circuitry.
External Resistor to set charge pump current and some internal bias currents. Use 3.6 kΩ as default.
Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves regulator
power-on time and phase noise, but may have stability issues over the supply and temperature.
Rev. A | Page 7 of 28
ADF7012
TYPICAL PERFORMANCE CHARACTERISTICS
315 MHz
–60
= NORMAL
FREQUENCY = 9.08 kHz
LEVEL = –84.47dBc/Hz
–70
5
0
–80
A
3
–20
–30
–100
–50
–120
–60
–140
1.0k
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
–70
1 [T1]
–80
RBW
0.45dBm VBW
315.05060120MHz SWT
1
CENTER 3.5MHz
5kHz RF ATT 30dB
5kHz
dBm
500ms UNIT
2
5
0
A
700MHz/
–11.48dBm
939.87975952MHz
–34.11dBm
1.26252505GHz
SPAN 7GHz
RBW
1MHz RF ATT 30dB
0.18dBm VBW
1MHz
308.61723447MHz SWT 17.5ms UNIT
dBm
REF LVL
5dBm
1
A
SGL
–20
–30
1MA
–40
1MA
3
–40
–50
–50
–60
–60
–70
–70
–80
–80
2
04617-0-005
1 [T1]
–90
–95
CENTER 315MHz
50kHz/
–90
–95
SPAN 500kHz
4 [T1]
–42.93dBm
939.87975952MHz
–55.48dBm
1.26252505GHz
SPAN 7GHz
700MHz/
Figure 8. Harmonic Response, Fifth-Order Butterworth Filter
RBW 500kHz RF ATT 30dB
0.31dBm VBW 500kHz
315.40080160MHz SWT
dBm
5ms UNIT
1
3 [T1]
0.18dBm
308.61723447MHz
–50.53dBm
631.26252505MHz
CENTER 3.5MHz
Figure 5. FSK Modulation, Power = 0 dBm, Data Rate = 1 kbps,
FDEVIATION = ±50 kHz
REF LVL
5dBm
2 [T1]
D1 –41.5dBm
4
04617-0-008
–30
5
0
A
–10
REF LVL
5dBm
RBW
20.33dBm VBW
26.55310621kHz SWT
5kHz RF ATT 30dB
5kHz
dBm
500ms UNIT
A
1
–10
–20
–20
–30
D2 –49dBm
1MA
–50
–70
–70
0.31dBm
315.40080160MHz
40MHz/
–80
04617-0-006
–80
–90
–95
SPAN 400MHz
1 [T1]
3 [T1]
2 [T1]
–3.49dBm
315.00012525MHz
–20.33dB
26.55310621kHz
–20.85dB
–27.55511022kHz
CENTER 315MHz
Figure 6. Spurious Components—Meets FCC Specs
50kHz/
04617-0-009
–60
CENTER 315MHz
3
–40
D1 –41.5dBm
1 [T1]
2
–30
1MA
–60
–90
–95
4 [T1]
–10
–20
–50
3 [T1]
Figure 7. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
–10
–40
0.27dBm
308.61723447MHz
–35.43dBm
631.26252505MHz
2 [T1]
–90
–95
10.0M
Figure 4. Phase Noise Response—DVDD = 3.0 V, ICP = 0.86 mA
IVCO = 2.0 mA, FOUT = 315 MHz, PFD = 3.6864 MHz, PA Bias = 5.5 mA
REF LVL
5dBm
D1 –41.5dBm
04617-0-007
–130
5
0
1MA
4
2
–40
–110
04617-0-004
dBc (Hz)
1
–10
–90
5
0
RBW
1MHz RF ATT 30dB
0.27dBm VBW
1MHz
308.61723447MHz SWT 17.5ms UNIT
dBm
REF LVL
5dBm
SPAN 500kHz
Figure 9. OOK Modulation, Power = 0 dBm, Data Rate = 10 kbps
Rev. A | Page 8 of 28
ADF7012
433 MHz
1 2.00V/ 2 1.00V/
1.50ms 500μs TRIG'D
1 720mv
15
10
RBW
10.01dBm VBW
433.91158317MHz SWT
REF LVL
15dBm
30kHz RF ATT 40dB
30kHz
dBm
90ms UNIT
1
A
0
–10
–20
2 CLKOUT
1MA
–30
D1 –36dBm
–40
–50
–60
04617-0-010
04617-0-013
–70
–80
–85
CENTER 433.9500601MHz 3.2MHz/
Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms
= NORMAL
FREQUENCY = 393.38 kHz
LEVEL = –102.34dBc/Hz
–60
15
10
–80
0
–100
–10
RBW
1MHz RF ATT 40dB
10.10dBm VBW
1MHz
434.86973948MHz SWT 17.5ms UNIT
dBm
REF LVL
15dBm
1
A
3
2
4
–20
–120
–40
–160
–50
–180
–200
1.0k
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
REF LVL
15dBm
D1 –36dBm
1 [T1]
–70
CENTER 3.5GHz
15
10
A
1
0
0
–10
–20
–30
D1 –36dBm
SPAN 7GHz
RBW
1MHz RF ATT 40dB
9.51dBm VBW
1MHz
434.86973948MHz SWT 17.5ms UNIT
dBm
REF LVL
15dBm
1
A
SGL
1MA
2
–50
–50
–60
–60
–70
–70
04617-0-012
1 [T1]
–80
–85
STOP 434.79kHz
D1 –30dBm
3
–40
174kHz/
700MHz/
–5.12dBm
1.30460922GHz
–17.57dBm
1.73947896GHz
–20
1MA
–30
–80
–85
3 [T1]
4 [T1]
Figure 14. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
RBW 10kHz RF ATT 40dB
5.60dBm VBW 300kHz
433.91158317MHz SWT
dBm
44ms UNIT
START 433.05MHz
10.10dBm
434.86973948MHz
–15.25dBm
869.73947896MHz
2 [T1]
–80
–85
10.0M
–10
–40
D1 –30dBm
–60
Figure 11. Phase Noise Response—ICP = 2.0 mA, IVCO = 2.0 mA,
RFOUT = 433.92 MHz, PFD = 4 MHz, PA Bias = 5.5 mA
15
10
1MA
–30
–140
04617-0-011
dBc (Hz)
Figure 13. Spurious Components—Meets ETSI Specs
04617-0-014
–40
SPAN 32MHz
2 [T1]
D1 –36dBm
4
9.51dBm
434.86973948MHz
–33.75dBm
869.73947896MHz
CENTER 3.5GHz
3 [T1]
4 [T1]
700MHz/
–43.60dBm
1.30460922GHz
–43.44dBm
1.73947896GHz
04617-0-015
1 CE
SPAN 7GHz
Figure 15. Harmonic Response, Fifth-Order Butterworth Filter
Figure 12. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps,
FDEVIATION = ±19.28 kHz
Rev. A | Page 9 of 28
ADF7012
868 MHz
= NORMAL
FREQUENCY = 251.3 kHz
LEVEL = –99.39dBc/Hz
–20
15
10
–40
dBc (Hz)
A
2
0
–20
–80
3
1MAX
4
1MA
–30
–100
–40
–120
–50
–160
1.0k
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
1 [T1]
–70
10.0M
12.27dBm
869.33867735MHz
–4.00dBm
1.72865731GHz
2 [T1]
–80
–85
CENTER 3.8GHz
Figure 16. Phase Noise Response—ICP = 2.5 mA, IVCO = 1.44 mA,
RFOUT = 868.95 MHz, PFD = 4.9152 MHz, Power = 12.5 dBm, PA Bias = Max
REF LVL
15dBm
D1 –30dBm
–60
04617-0-016
–140
RBW 10kHz RF ATT
30dB
–40.44dBm VBW 10kHz MIXER –20dBm
869.20000000MHz SWT 15ms UNIT
dBm
2
LN
3 [T1]
4 [T1]
640MHz/
1
1 [T1]
0
0
–10
–10
2 [T1]
–20
–30
–30
D2 –36dBm
–40
1
–50
CENTER 868.944489MHz
D2 –30dBm
2
3
–70
60kHz/
–80
–85
START 3.8GHz
SPAN 600kHz
Figure 17. FSK Modulation, Power = 12.5 dBm, Data Rate = 38.4 kbps,
FDEVIATION = ±19.2 kHz
REF LVL
15dBm
RBW
12.55dBm VBW
869.025050100MHz SWT
1
1 [T1]
0
2 [T1]
–10
3 [T1]
30dB
2kHz RF ATT
2kHz MIXER –20dBm
dBm
16s UNIT
12.55dBm
869.02505010MHz
–57.89dBm
859.16695500MHz
–81.97dBm
862.00000000MHz
–20 1MAX
A
LN
1MA
–30
D2 –36dBm
–40
2
D1 –54dBm
–60
04617-0-018
–70
–80
–85
1MA
3
START 856.5MHz
2.5MHz/
04617-0-020
2 [T1]
–80
–85
40.44dBm
869.20000000MHz
8.02dBm
868.96673347MHz
04617-0-017
1 [T1]
–50
1MAX
A
LN
–60
–60
15
10
10.39dBm
869.33867735MHz
–50.92dBm
1.72000000GHz
–50.40dBm
2.59600000GHz
–40
–50
–70
SPAN 6.4GHz
RBW 1kHz RF ATT
30dB
10.39dBm VBW 1kHz MIXER –20dBm
869.33867735MHz SWT 10ms UNIT
dBm
REF LVL
15dBm
3 [T1]
1MA
–16.88dBm
2.59699399GHz
–15.06dBm
3.46913828GHz
Figure 19. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
15
10
A
–20 1MAX
1MHz RF ATT 40dB
1MHz
dBm
16ms UNIT
1
–10
–60
15
10
RBW
12.27dBm VBW
869.33867735MHz SWT
REF LVL
15dBm
04617-0-019
0
STOP 881.5MHz
Figure 18. Spurious Components—Meets ETSI Specs
Rev. A | Page 10 of 28
640MHz/
SPAN 6.4GHz
Figure 20. Harmonic Response, Fifth-Order Chebyshev Filter
ADF7012
915 MHz
–40
= NORMAL
FREQUENCY = 992.38 kHz
LEVEL = –102.34dBc/Hz
–60
15
10
–80
A
1
0
2
–10
–100
–20
–120
3
1MAX
–40
–160
–50
–200
1.0k
10.0k
100.0k
PHASE NOISE (Hz)
1.0M
D1 –41.5dBm
–60
1 [T1]
–70
10.0M
2 [T1]
–80
–85
10.25dBm
907.81563126MHz
–10.06dBm
1.83126253GHz
CENTER 3.8GHz
Figure 21. Phase Noise Response—ICP = 1.44 mA, IVCO = 3.0 mA,
RFOUT = 915.2 MHz, PFD =10 MHz, Power = 10 dBm, PA Bias = 5.5 mA
REF LVL
15dBm
RBW 10kHz RF ATT 40dB
3.88dBm VBW 300kHz
915.19098196MHz SWT 15ms UNIT
dBm
–20.29dBm
2.74188377GHz
–17.50dBm
3.65250501GHz
640MHz/
SPAN 6.4GHz
RBW 50MHz RF ATT 40dB
9.06dBm VBW 50MHz
907.81563126MHz SWT
dBm
6.4s UNIT
REF LVL
15dBm
A
1
–10
1MA
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
1MAX
2
04617-0-036
1 [T1]
–80
–85
CENTER 915.190982MHz
50kHz/
–80
–85
*
A
SGL
0
–10
1MA
–20
–30
D1 –41.5dBm
D1 –49.5dBm
–60
04617-0-037
–70
–80
–85
CENTER 915.2MHz
40MHz/
3
D1 –41.5dBm
4
9.06dBm
907.81563126MHz
–48.40dBm
1.83126253GHz
3 [T1]
4 [T1]
640MHz/
–46.22dBm
2.74188377GHz
–46.96dBm
3.65250501GHz
SPAN 6.4GHz
Figure 25. Harmonic Response, Fifth-Order Chebyshev Filter
RBW 10kHz RF ATT 40dB
9.94dBm VBW 300kHz
915.23167977MHz SWT 100ms UNIT
dBm
1
2 [T1]
CENTER 3.8GHz
SPAN 500kHz
Figure 22. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps,
FDEVIATION = ±19.2 kHz
REF LVL
15dBm
1MA
04617-0-039
–20 1MAX
–50
4 [T1]
0
–10
–40
3 [T1]
Figure 24. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
15
10
A
1
0
15
10
1MA
04617-0-038
–180
15
10
4
–30
–140
04617-0-021
dBc (Hz)
RBW 50MHz RF ATT 40dB
10.25dBm VBW 50MHz
907.81563126MHz SWT
dBm
6.4s UNIT
REF LVL
15dBm
SPAN 400MHz
Figure 23. Spurious Components—Meets FCC Specs
Rev. A | Page 11 of 28
ADF7012
CIRCUIT DESCRIPTION
PLL OPERATION
CRYSTAL/R
R
LOOP FILTER
PFD
CP
VCO
OSC2
CP2
CP1
Figure 27. Oscillator Circuit on the ADF7012
Two parallel resonant capacitors are required for oscillation at
the correct frequency—the value of these depend on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds to give the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary between 2 pF to 5 pF, depending on board layout.
Where possible, to ensure stable frequency operation over all
conditions, capacitors should be chosen so that they have a
very low temperature coefficient and/or opposite temperature
coefficients
Typically, for a 10 MHz crystal with 20 pF load capacitance,
the oscillator circuit can tolerate a crystal ESR value of ≤ 50 Ω.
The ESR tolerance of the ADF7012 decreases as crystal frequency increases, but this can be offset by using a crystal with
lower load capacitance.
CRYSTAL COMPENSATION REGISTER
FVCO
The ADF7012 features a 15-bit fixed modulus, which allows the
output frequency to be adjusted in steps of FPFD/15. This fine
resolution can be used to easily compensate for initial error and
temperature drift in the reference crystal.
04617-0-022
VCO/N
N
OSC1
04617-0-023
A fractional-N PLL allows multiple output frequencies to be
generated from a single-reference oscillator (usually a crystal)
simply by changing the programmable N value found in the
N register. At the phase frequency detector (PFD), the reference
is compared to a divided-down version of the output frequency
(VCO/N). If VCO/N is too low a frequency, typically the output
frequency is lower than desired, and the PFD and charge-pump
combination sends additional current pulses to the loop filter.
This increases the voltage applied to the input of the VCO.
Because the VCO of the ADF7012 has a positive frequency vs.
voltage characteristic, any increase in the VTUNE voltage applied
to the VCO input increases the output frequency at a rate of
kilovolts, the tuning sensitivity of the VCO (MHz/V). At each
interval of 1/PFD seconds, a comparison is made at the PFD
until the PFD and charge pump eventually force a state of
equilibrium in the PLL where PFD frequency = VCO/N. At
this point, the PLL can be described as locked.
Figure 26. Fractional-N PLL
FADJUST = FSTEP × FEC
FOUT =
FCRYSTAL × N
= FPFD × N
R
(1)
For a fractional-N PLL
FOUT
N
⎛
⎞
= FPFD × ⎜ N INT + FRAC
12 ⎟
2
⎝
⎠
(2)
where NFRAC can be Bits M1 to M12 in the fractional-N register.
CRYSTAL OSCILLATOR
The on-board crystal oscillator circuitry (Figure 27) allows an
inexpensive quartz crystal to be used as the PLL reference. The
oscillator circuit is enabled by setting XOEB low. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the error correction
register within the R register.
A single-ended reference may be used instead of a crystal, by
applying a square wave to the OSC2 pin, with XOEB set high.
(3)
where:
FSTEP = FPFD/215
FEC = Bit F1 to Bit F11 in the R Register
Note that the notation is twos complement, so F11 represents
the sign of the FEC number.
Example
FPFD = 10 MHz
FADJUST = −11 kHz
FSTEP = 10 MHz/215 = 305.176 Hz
FEC = −11 kHz/305.17 Hz = −36 = −(00000100100) =
11111011100 = 0x7DC
CLOCK OUT CIRCUIT
The clock out circuit takes the reference clock signal from the
Crystal Oscillator section and supplies a divided-down 50:50
mark-space signal to the CLKOUT pin. An even divide from
2 to 30 is available. This divide is set by the DB[19:22] in the
R register. On power-up, the CLKOUT defaults to divide by 16.
Rev. A | Page 12 of 28
ADF7012
DVDD
The varactor capacitance can be adjusted in software to increase
the effective VCO range by writing to the VA1 and VA2 bits in
the R register. Under typical conditions, setting VA1 and VA2
high increases the center frequency by reducing the varactor
capacitance by approximately 1.3 pF.
CLKOUT
ENABLE BIT
DIVIDER
1 TO 15
÷2
CLKOUT
04617-0-024
OSC1
Figure 28. CLKOUT Stage
The output buffer to CLKOUT is enabled by setting Bit DB4 in
the function register high. On power-up, this bit is set high.
The output buffer can drive up to a 20 pF load with a 10% rise
time at 4.8 MHz. Faster edges can result in some spurious
feedthrough to the output. A small series resistor (50 Ω) can
be used to slow the clock edges to reduce these spurs at FCLK.
LOOP FILTER
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 29.
CHARGE
PUMP OUT
Figure 37 shows the variation of VCO gain with frequency.
VCO gain is important in determining the loop filter design—
predictable changes in VCO gain resulting in a change in the
loop filter bandwidth can be offset by changing the chargepump current in software.
VCO Bias Current
VCO bias current may be adjusted using bits VB1 to VB4 in the
function register. Additional bias current will reduce spurious
levels, but increase overall current consumption in the part. A
bias value of 0x5 should ensure oscillation at most frequencies
and supplies. Settings 0x0, 0xE , and 0xF are not recommended.
Setting 0x3 and Setting 0x4 are recommended under most
conditions. Improved phase noise can be achieved for lower
bias currents.
VOLTAGE REGULATORS
VCO
04617-0-025
There are two band gap voltage regulators on the ADF7012
providing a stable 2.25 V internal supply: a 2.2 μF capacitor
(X5R, NP0) to ground at CREG1 and a 470 nF capacitor at CREG2
should be used to ensure stability. The internal reference
ensures consistent performance over all supplies and reduces
the current consumption of each of the blocks.
Figure 29. Typical Loop Filter
In FSK, it is recommended that the loop bandwidth be a
minimum of two to three times the data rate. Widening the
LBW excessively reduces the time spent jumping between
frequencies, but results in reduced spurious attenuation. See
the Tips on Designing the Loop Filter section.
For OOK/ASK systems, a wider loop bandwidth than for FSK
systems is desirable. The sudden large transition between two
power levels results in VCO pulling (VCO temporarily goes to
incorrect frequency) and can cause a wider output spectrum.
By widening the loop bandwidth a minimum of 10× the data
rate, VCO pulling is minimized because the loop settles quickly
back to the correct frequency. A free design tool, the ADI SRD
Design Studio™, can be used to design loop filters for the Analog
Devices family of transmitters.
The combination of regulators, band gap reference, and biasing
typically consume 1.045 mA at 3.0 V and can be powered down
by bringing the CE line low. The serial interface is supplied by
Regulator 1, so powering down the CE line causes the contents
of the registers to be lost. The CE line must be high and the regulators must be fully powered on to write to the serial interface.
Regulator power-on time is typically 100 μs and should be taken
into account when writing to the ADF7012 after power-up.
Alternatively, regulator status may be monitored at the MUXOUT
pin once CE has been asserted, because MUXOUT defaults to
the regulator ready signal. Once Regulator_ready is high, the
regulator is powered up and the serial interface is active.
VOLTAGE-CONTROLLED OSCILLATOR (VCO)
FSK MODULATION
The ADF7012 features an on-chip VCO with an external tank
inductor, which is used to set the frequency range. The center
frequency of oscillation is governed by the internal varactor
capacitance and that of the external inductor combined with
the bond-wire inductance. An approximation for this is given
in Equation 4. For a more accurate selection of the inductor,
see the section Choosing the External Inductor Value.
FSK modulation is performed internally in the PLL loop by
switching the value of the N register based on the status of
the TxDATA line. The TxDATA line is sampled at each cycle
of the PFD block (every 1/FPFD seconds). When TxDATA
makes a low-to-high transition, an N value representing the
deviation frequency is added to the N value representing the
center frequency. Immediately the loop begins to lock to the
new frequency of FCENTER + FDEVIATION. Conversely, when TxDATA
makes a high-to-low transition, the N value representing the
deviation is subtracted from the PLL N value representing the
center frequency and the loop transitions to FCENTER − FDEVIATION.
FVCO =
1
2π ( LINT + LEXT ) × (CVAR + CFIXED )
(4)
Rev. A | Page 13 of 28
ADF7012
PFD/
CHARGE
PUMP
PA STAGE
VCO
FSK DEVIATION
FREQUENCY
÷N
–FDEV
04617-0-026
THIRD-ORDER
Σ-Δ MODULATOR
+FDEV
TxDATA
FRACTIONAL-N
INTEGER-N
Figure 30. FSK Implementation
I/O
TxDATA
INT
TxCLK
ADF7012
μC
The deviation from the center frequency is set using the D1 to
D9 bits in the modulation register. The frequency deviation
may be set in steps of
FSTEP ( Hz ) =
FETCH
FETCH
SAMPLE SAMPLE
FETCH
SAMPLE
Figure 31. TxCLK/TxDATA Synchronization.
FPFD
214
(5)
The deviation frequency is therefore
FDEVIATION ( Hz ) =
FETCH
04617-0-040
4R
For GFSK and GOOK, the incoming bit stream to be transmitted needs to be synchronized with an on-chip sampling
clock which provides one sample per bit to the Gaussian FIR
filter. To facilitate this, the sampling clock is routed to the
TxCLK pin where data is fetched from the host microcontroller
or microprocessor on the falling edge of TxCLK, and the data
is sampled at the midpoint of each bit on TxCLK’s rising edge.
Inserting external RC LPFs on TxDATA and TxCLK lines
creates smoother edge transitions and improves spurious
performance. As an example, suitable components are a 1 kΩ
resistor and a 10 nF capacitor for a data rate of 5 kbps.
FPFD × ModulationNumber
214
The number of steps between symbol 0 and symbol 1 is
determined by the setting for the index counter.
The GFSK deviation is set up as
(6)
GFSK DEVIATION ( Hz) =
where ModulationNumber is set by Bit D1 to Bit D9.
FPFD × 2 m
212
(7)
where m is the mod control (Bit MC1 to Bit MC3 in the
modulation register).
The maximum data rate is a function of the PLL lock time (and
the requirement on FSK spectrum). Because the PLL lock time
is reduced by increasing the loop-filter bandwidth, highest data
rates can be achieved for the wider loop filter bandwidths. The
absolute maximum limit on loop filter bandwidth to ensure
stability for a fractional-N PLL is FPFD/7. For a 20 MHz PFD
frequency, the loop bandwidth could be as high as 2.85 MHz.
FSK modulation is selected by setting the S1 and S2 bits in the
modulation register low.
where the DividerFactor is set by Bit D1 to Bit D7, and the
IndexCounter is set by Bit IC1 and Bit IC2 in the modulation
register.
GFSK MODULATION
POWER AMPLIFIER
Gaussian frequency shift keying (GFSK) represents a filtered
form of frequency shift keying. The data to be modulated to
RF is prefiltered digitally using a finite impulse response filter
(FIR). The filtered data is then used to modulate the sigmadelta fractional-N to generate spectrally-efficient FSK.
The output stage is based on a Class E amplifier design, with
an open-drain output switched by the VCO signal. The output
control consists of six current mirrors operating as a programmable current source.
FSK consists of a series of sharp transitions in frequency as the
data is switched from one level to another. The sharp switching
generates higher frequency components at the output, resulting
in a wider output spectrum.
With GFSK, the sharp transitions are replaced with up to 128
smaller steps. The result is a gradual change in frequency. As a
result, the higher frequency components are reduced and the
spectrum occupied is reduced significantly. GFSK does require
some additional design work as the data is only sampled once
per bit, and so the choice of crystal is important to ensure the
correct sampling clock is generated.
The GFSK sampling clock samples data at the data rate
DataRate (bps ) =
FPFD
DividerFactor × IndexCounter
(8)
To achieve maximum voltage swing, the RFOUT pin needs to be
biased at DVDD. A single pull-up inductor to DVDD ensures a
current supply to the output stage; PA is biased to DVDD volts,
and with the correct choice of value transforms the impedance.
The output power can be adjusted by changing the value of
Bit P1 to Bit P6. Typically, this is P1 to P6 output −20dBm at
0x0, and 13 dBm at 0x7E at 868 MHz, with the optimum
matching network.
Rev. A | Page 14 of 28
ADF7012
The nonlinear characteristic of the output stage results in an
output spectrum containing harmonics of the fundamental,
especially the third and fifth. To meet local regulations, a lowpass filter usually is required to filter these harmonics.
As is the case with GFSK, GOOK requires the bit stream
applied at TxDATA to be synchronized with the sampling clock,
TxCLK (see the GFSK Modulation section).
The output stage can be powered down by setting Bit PD2 in
the function register low.
10
0
GOOK MODULATION
–10
OOK
–20
POWER (dBm)
FPFD
DividerFactor × IndexCounter
–60
–70
–80
909.43
(9)
910.43
FREQUENCY (MHz)
910.93
20
10
0
–10
POWER (dBm)
Figure 32 shows the step response of the Gaussian FIR filter.
An index counter of 16 is demonstrated for simplicity. While
the pre-filter data would switch the PA directly from off to on
with a low-to-high data transition, the filtered data gradually
increases the PA output in discrete steps. This has the effect of
making the output spectrum more compact.
GOOK
Figure 33. GOOK vs. OOK Frequency Spectra
(Narrow-Band Measurement)
Bit D1 to Bit D6 represent the output power for the system
for a positive data bit. Divider Factor = 0x3F represents the
maximum possible deviation from PA at minimum to PA
at maximum output. Note that PA output level bits in Register 2
are defunct. An index counter setting of 128 is recommended.
PRE-FILTER DATA
(0 TO 1 TRANSITION)
–20
–30
OOK
–40
–50
–60
–80
–90
885.43
GOOK
910.43
FREQUENCY (MHz)
Figure 34. GOOK vs. OOK Frequency Spectra
(Wideband Measurement)
DISCRETIZED
FILTER OUTPUT
Figure 32. Varying PA Output for GOOK (Index Counter = 16).
Rev. A | Page 15 of 28
04617-0-044
–70
04617-0-041
PA SETTING
16 (MAX)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 (PA OFF)
–40
–50
The GOOK sampling clock samples data at the data rate:
DataRate (bps ) =
–30
04617-0-043
Gaussian on-off keying (GOOK) represents a prefiltered form
of OOK modulation. The usually sharp symbol transitions
are replaced with smooth Gaussian-filtered transitions with
the result being a reduction in frequency pulling of the VCO.
Frequency pulling of the VCO in OOK mode can lead to a
wider than desired bandwidth, especially if it is not possible
to increase the loop filter bandwidth to > 300 kHz.
935.93
ADF7012
OUTPUT DIVIDER
Battery Voltage Readback
An output divider is a programmable divider following the
VCO in the PLL loop. It is useful when using the ADF7012 to
generate frequencies of < 500 MHz.
By setting MUXOUT to 1010 to 1101, the battery voltage can
be estimated. The battery measuring circuit features a voltage
divider and a comparator where the divided-down supply
voltage is compared to the regulator voltage.
PFD
CP
LOOP
FILTER
VCO
OUTPUT
DIVIDER
PA
÷1/2/4/8
÷N
04617-0-042
REFERENCE
DIVIDER
Figure 35. Output Divider Location in PLL
The output divider may be used to reduce feedthrough of the
VCO by amplifying only the VCO/2 component, restricting the
VCO feedthrough to leakage.
Because the divider is in loop, the N register values should be
set up according to the usual formula. However, the VCO gain
(KV) should be scaled according to the divider setting, as shown
in the following example:
FOUT = 433 MHz
FVCO = 866 MHz
KV @ 868 MHz = 60 MHz/V
The divider value is set in the R register.
Table 5.
OD2
0
1
0
1
MUXOUT
1010
1011
1100
1101
MUXOUT High
DVDD < 2.35 V
DVDD < 2.75 V
DVDD < 3.0 V
DVDD < 3.25 V
MUXOUT Low
DVDD > 2.35 V
DVDD > 2.75 V
DVDD > 3.0 V
DVDD > 3.25 V
The accuracy of the measurement is limited by the accuracy of
the regulator voltage and the internal resistor tolerances.
Regulator Ready
The regulator has a power-up time, dependant on process and
the external capacitor. The regulator ready signal indicates that
the regulator is fully powered, and that the serial interface is
active. This is the default setting on power-up at MUXOUT.
Digital Lock Detect
Therefore, KV for loop filter design = 30 MHz/V.
OD1
0
0
1
1
Table 6.
Divider Status
Divider off
Divide by 2
Divide by 4
Divide by 8
MUXOUT MODES
The MUXOUT pin allows the user access to various internal
signals in the transmitter, and provides information on the
PLL lock status, the regulator, and the battery voltage. The
MUXOUT is accessed by programming Bits M1 to M4 in the
function register and observing the signal at the MUXOUT pin.
Digital lock detect indicates that the status of the PLL loop.
The PLL loop takes time to settle on power-up and when the
frequency of the loop is changed by changing the N value.
When lock detect is high, the PFD has counted a number of
consecutive cycles where the phase error is < 15 ns. The lock
detect precision bit in the function register determines whether
this is three cycles (LDP = 0), or five cycles (LDP = 1). It is
recommended that LDP be set to 1. The lock detect is not
completely accurate and goes high before the output has settled
to exactly the correct frequency. In general, add 50% to the
indicated lock time to obtain lock time to within 1 kHz. The
lock detect signal can be used to decide when the power
amplifier (PA) should be enabled.
R Divider
MUXOUT provides the output of the R divider. This is a
narrow pulsed digital signal at frequency FPFD. This signal
may be used to check the operation of the crystal circuit and
the R divider. R divider/2 is a buffered version of this signal
at FPFD/2.
Rev. A | Page 16 of 28
ADF7012
THEORY OF OPERATION
CHOOSING THE EXTERNAL INDUCTOR VALUE
CHOOSING THE CRYSTAL/PFD VALUE
The ADF7012 allows operation at many different frequencies by
choosing the external VCO inductor to give the correct output
frequency. Figure 36 shows both the minimum and maximum
frequency vs. the inductor value. These are measurements based
on 0603 CS type inductors from Coilcraft, and are intended as
guidelines in choosing the inductor because board layout and
inductor type varies between applications.
The choice of crystal value is an important one. The PFD
frequency must be the same as the crystal value or an integer
division of it. The PFD determines the phase noise, spurious
levels and location, deviation frequency, and the data rate in
the case of GFSK. The following sections describe some factors
to consider when choosing the crystal value.
The inductor value should be chosen so that the VCO is centered at the correct frequency. When locked, the VCO tuning
voltage can be between 0.2 V and 2.1 V. This voltage can be
measured at Pin 18 (VCOIN). To ensure operation over
temperature and from part to part, an inductor should be
chosen so that the tuning voltage is ~1 V at the desired output
frequency.
Standard crystal values are 3.6864 MHz, 4 MHz, 4.096 MHz,
4.9152 MHz, 7.3728 MHz, 9.8304 MHz, 10 MHz, 11.0592 MHz,
12 MHz, and 14.4792 MHz. Crystals with these values are
usually available in stock and cost less than crystals with
nonstandard values.
MIN (meas)
MAX (meas)
MIN (eqn)
FREQUENCY (MHz)
1000
MAX (eqn)
900
800
700
Beat Note Spurs
600
Beat note spurs are spurs occurring for very small or very large
values in the fractional register. These are quickly attenuated by
the loop filter. Selection of the PFD therefore determines their
location, and ensures that they have negligible effect on the
transmitter spectrum.
04617-0-031
500
400
300
Reference Spurious Levels
Reference spurious levels (spurs) occur at multiples of the
PFD frequency. The reference spur closest to the carrier is
usually highest with the spur further out being attenuated by
the loop filter. The level of reference spur is lower for lower
PFD frequencies. In designs with high output power where
spurious levels are the main concern, a lower PFD frequency
(<5 MHz) may be desirable.
1200
1100
Standard Crystal Values
0
5
10
15
20
INDUCTANCE (nH)
25
30
35
Phase Noise
Figure 36. Output Frequency vs. External Inductor Value
IBIAS = 2.0 mA.
For frequencies between 270 MHz and 550 MHz, it is recommended to operate the VCO at twice the desired output
frequency and use the divide-by-2 option. This ensures reliable
operation over temperature and supply.
For frequencies between 130 MHz and 270 MHz, it is recommended to operate the VCO at four times the desired output
frequency and use the divide-by-4 option.
The phase noise of a frequency synthesizer improves by 3 dB
for every doubling of the PFD frequency. Because ACP is
related to the phase noise, the PFD may be increased to reduce
the ACP in the system. PFD frequencies of < 5 MHz typically
deliver sufficient phase noise performance for most systems.
Deviation Frequency
The deviation frequency is adjustable in steps of
FSTEP ( Hz ) =
For frequencies below 130 MHz, it is best to use the divideby-8 option. It is not necessary to use the VCO divider for
frequencies above 550 MHz.
ADIsimSRD Design Studio is a design tool which can perform
the frequency calculations for the ADF7012, and is available at
www.analog.com.
FPFD
214
(10)
To get the exact deviation frequency required, ensure FSTEP is a
factor of the desired deviation.
Rev. A | Page 17 of 28
ADF7012
TIPS ON DESIGNING THE LOOP FILTER
The loop filter design is crucial in ensuring stable operation
of the transmitter, meeting adjacent channel power (ACP)
specifications, and meeting spurious requirements for the
relevant regulations. ADIsimSRD Design Studio™ is a free tool
available to aid the design of loop filters. The user enters the
desired frequency range, the reference crystal and PFD values,
and the desired loop bandwidth. ADIsimSRD Design Studio
gives a good starting point for the filter, and the filter can be
further optimized based on the criteria below.
Setting Tuning Sensitivity Value
The tuning sensitivity or kV, usually denoted in MHz/V, is
required for the loop filter design. It refers to the amount that
a change of a volt in the voltage applied to the VCOIN pin,
changes the output frequency. Typical data for the ADF7012
over a frequency range is shown.
120
Spurious Levels
In the case where the output power is quite high, a reduced loop
filter bandwidth reduces the spurious levels even further, and
provides additional margin on the specification.
The following sections provide examples of loop filter designs
for typical applications in specific frequencies.
PA MATCHING
The ADF7012 exhibits optimum performance in terms of
transmit power and current consumption only if the RF output
port is properly matched to the antenna impedance.
ZOPT_PA depends primarily on the required output power,
and the frequency range. Selecting the optimum ZOPT_PA
helps to minimize the current consumption. This data sheet
contains a number of matching networks for common frequency bands. Under certain conditions it is recommended
to obtain a suitable ZOPT_PA value by means of a load-pull
measurement.
100
DVDD
RFOUT
PA
ANTENNA
60
LPF
ZOPT_PA
40
Figure 38. ADF7012 with Harmonic Filter
004617-0-032
300
400
500
600
700
800
FREQUENCY (MHz)
900
1000
The impedance matching values provided in the next section
are for 50 Ω environments. An additional matching network
may be required after the harmonic filter to match to the
antenna impedance. This can be incorporated into the filter
design itself in order to reduce external components.
1100
Figure 37. kV vs. VCO Frequency
Charge-Pump Current
The charge-pump current allows the loop filter bandwidth to be
changed using the registers. The loop bandwidth reduces as the
charge pump current is reduced and vice versa.
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
PREAMBLE
Selecting Loop Filter Bandwidth
Data Rate
The loop filter bandwidth should usually be at two to three
times the data rate. This ensures that the PLL has ample time
to jump between the mark and space frequencies.
ACP
In the case where the ACP specifications are difficult to meet,
the loop filter bandwidth can be reduced further to reduce the
phase noise at the adjacent channel. The filter rolls off at 20 dB
per decade.
SYNC
WORD
ID
FIELD
DATA FIELD
CRC
04617-0-034
20
0
200
04617-0-033
KV (MHz/V)
80
Figure 39. Typical Format of a Transmit Protocol
A dc-free preamble pattern such as 10101010… is recommended for FSK/ASK/OOK demodulation. Preamble patterns
with longer run-length constraints such as 11001100…. can also
be used. However, this can result in a longer synchronization
time of the received bit stream in the chosen receiver.
Rev. A | Page 18 of 28
ADF7012
APPLICATION EXAMPLES
04617-0-035
Figure 40. Applications Diagram with Harmonic Filter
Rev. A | Page 19 of 28
ADF7012
315 MHz OPERATION
Deviation
The recommendations presented here are guidelines only.
The design should be subject to internal testing prior to FCC
site testing. Matching components need to be adjusted for
board layout.
The deviation is set to ± 50 kHz to accommodate simple
receiver architecture.
The FCC standard 15.231 regulates operation in the band
from 260 MHz to 470 MHz in the US. This is used generally
in the transmission of RF control signals, such as in a satellitedecoder remote control, or remote keyless entry system.
The band cannot be used to send any continuous signal. The
maximum output power allowed is governed by the duty cycle
of the system. A typical design example for a remote control
is provided.
Design Criteria
315 MHz center frequency
FSK/OOK modulation
1 mW output power
House range
Meets FCC 15.231
The main requirements in the design of this remote are a long
battery life and sufficient range. It is possible to adjust the
output power of the ADF7012 to increase the range depending
on the antenna performance.
The center frequency is 315 MHz. Because the ADF7012
VCO is not recommended for operation in fundamental mode
for frequencies below 400 MHz, the VCO needs to operate at
630 MHz. Figure 36 implies an inductor value of, or close to,
7.6 nH. The chip inductor chosen = 7.5 nH (0402CS-7N5
from Coilcraft). Coil inductors are recommended to provide
sufficient Q for oscillation.
Crystal and PFD
Phase noise requirements are not excessive as the adjacent
channel power requirement is −20 dB. The PFD is chosen to
minimize spurious levels (beat note and reference), and to
ensure a quick crystal power-up time.
PFD = 3.6864 MHz − power-up time 1.6 ms.
Figure 10 shows a typical power-on time for a 4 MHz crystal.
N-Divider
The N-divider is determined as being
NINT = 85
NFRAC = (1850)/4096
VCO divide-by-2 is enabled
The modulation steps available are in 3.6864 MHz/214 :
Modulation steps = 225 Hz
Modulation number = 50 kHz/225 Hz = 222
Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used.
Additional bias current reduces any spur, but increases current
consumption.
The PA bias can be set to 5.5 mA and can achieve 0 dBm.
Loop Filter Bandwidth
The loop filter is designed with the ADIsimSRD Design Studio.
The loop bandwidth design is straightforward because the
20 dB bandwidth is generally of the order of >400 kHz (0.25%
of center frequency). A loop bandwidth of close to 100 kHz
strikes a good balance between lock time and spurious
suppression. If it is found that pulling of the VCO is more than
desired in OOK mode, the bandwidth could be increased.
Design of Harmonic Filter
The main requirement of the harmonic filter should ensure
that the third harmonic level is < −41.5 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 3.6864 MHz
Loop Filter
ICP
0.866 mA
LBW
100 kHz
C1
680 pF
C2
12 nF
C3
220 pF
R1
1.1 kΩ
R2
3 kΩ
Matching
L1
56 nH
L2
1 nF
C14
470 pF
Harmonic Filter
L4
22 nH
L5
22 nH
C15
3.3 pF
C16
8.2 pF
C17
3.3 pF
Rev. A | Page 20 of 28
ADF7012
433 MHz OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to ETSI site testing.
Matching components need to be adjusted for board layout.
The ETSI standard EN 300-220 governs operation in the
433.050 MHz to 434.790 MHz band. For many systems, 10%
duty is sufficient for the transmitter to output 10 dBm.
Design Criteria
433.92 MHz center frequency
FSK modulation
10 mW output power
200 m range
Meets ETSI 300-220
The main requirement in the design of this remote is a long
battery life and sufficient range. It is possible to adjust the
output power of the ADF7012 to increase the range depending
on the antenna performance.
The center frequency is 433.92 MHz. It is possible to operate the
VCO at this frequency. Figure 36 shows the inductor value vs.
center frequency. The inductor chosen is 22 nH. Coilcraft
inductors such as 0603-CS-22NXJBU are recommended.
Crystal and PFD
The phase noise requirement is such to ensure the power at
the edge of the band is < −36 dBm. The PFD is chosen to
minimize spurious levels (beat note and reference), and to
ensure a quick crystal power-up time.
PFD = 4.9152 MHz − Power-Up Time 1.6 ms. Figure 10 shows a
typical power-up time for a 4 MHz crystal.
N-Divider
The N Divider is determined as being:
Nint = 88
Nfrac = (1152)/4096
VCO divide-by-2 is not enabled
Deviation
The deviation is set to ± 50 kHz to accommodate a simple
receiver architecture.
The modulation steps available are in 4.9152 MHz/214 :
Modulation steps = 300 Hz
Modulation number = 50 kHz/300Hz = 167
Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used.
Additional bias current reduces any spurious, but increases
current consumption.
The PA bias can be set to 5.5 mA and achieve 10 dBm.
Loop Filter Bandwidth
The loop filter is designed with ADIsimSRD Design Studio.
The loop bandwidth design requires that the channel power
be < −36 dBm at ±870 kHz from the center. A loop bandwidth
of close to 160 kHz strikes a good balance between lock time for
data rates, including 32 kbps and spurious suppression. If it is
found that pulling of the VCO is more than desired in OOK
mode, the bandwidth could be increased.
Design of Harmonic Filter
The main requirement of the harmonic filter should ensure
that the third harmonic level is < −30 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 4.9152 MHz
Loop Filter
Icp
2.0 mA
LBW
100 kHz
C1
680 pF
C2
12 nF
C3
270 pF
R1
910 Ω
R2
3.3 kΩ
Matching
L1
22 nH
L2
10 pF
C14
470 pF
Harmonic Filter
L4
22 nH
L5
22 nH
C15
3.3 pF
C16
8.2 pF
C17
3.3 pF
Rev. A | Page 21 of 28
ADF7012
868 MHz OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to ETSI site testing.
Matching components need to be adjusted for board layout.
The ETSI standard EN 300-220 governs operation in the
868 MHz to 870MHz band. The band is broken down into
several subbands each having a different duty cycle and output
power requirement. Narrowband operation is possible in the
50kHz channels, but both the output power and data rate are
limited by the −36 dBm adjacent channel power specification.
There are many different applications in this band, including
remote controls for security, sensor interrogation, metering
and home control.
Design Criteria
868.95 MHz center frequency (band 868.7MHz − 869.2 MHz)
FSK modulation
12 dBm output power
300 m range
Meets ETSI 300-220
38.4 kbps data rate
The design challenge is to enable the part to operate in this
particular subband and meet the ACP requirement 250 kHz
away from the center.
The center frequency is 868.95 MHz. It is possible to operate the
VCO at this frequency. Figure 31 shows the inductor value vs.
center frequency. The inductor chosen is 1.9 nH. Coilcraft
inductors such as 0402-CS-1N9XJBU are recommended.
Crystal and PFD
The phase noise requirement is such to ensure the power at
the edge of the band is < −36 dBm. This requires close to
−100 dBc/Hz phase noise at the edge of the band.
PFD = 4.9152 MHz − Power Up-Time 1.6 ms. Figure 10 shows a
typical power-on time for a 4MHz crystal.
The N divider is determined as being:
Nint = 176
Nfrac = (3229)/4096
VCO divide-by-2 is not enabled.
The deviation is set to ±19.2 kHz to accommodate a simple
receiver architecture and ensure that the modulation spectrum
is narrow enough to meet the adjacent channel power (ACP)
requirements.
The modulation steps available are in 4.9152 MHz/214 :
Modulation steps = 300 Hz
Modulation number = 19.2 kHz/300 Hz = 64.
Bias Current
Because low current is desired, a 2.5 mA VCO bias can be used.
Additional bias current reduces any spurious, but increases
current consumption. A 2.5 mA bias current gives the best
spurious vs. phase noise trade-off.
The PA bias should be set to 7.5 mA to achieve 12 dBm.
Loop Filter Bandwidth
The loop filter is designed with ADIsimSRD Design Studio.
The loop bandwidth design requires that the channel power be
< −36 dBm at ±250 kHz from the center. A loop bandwidth of
close to <60 kHz is required to bring the phase noise at the edge
of the band sufficiently low to meet the ACP specification. This
represents a compromise between the data rate requirement and
the phase noise requirement.
Design of Harmonic Filter
The main requirement of the harmonic filter should ensure that
the second and third harmonic levels are < −30 dBm. A fifthorder Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 4.9152 MHz
The PFD is chosen to minimize spurious levels (beat note and
reference), and to ensure a quick crystal power-up time. A PFD
of < 6 MHz places the largest PFD spur at a frequency of greater
than 862 MHz, and so reduces the requirement on the spur
level to −36 dBm instead of −54 dBm.
N-Divider
Deviation
Loop Filter
Icp
1.44 mA
LBW
60 kHz
C1
1.5 nF
C2
22 nF
C3
560 pF
R1
390 Ω
R2
910 Ω
Matching
L1
27 nH
L2
6.2 nH
C14
470 pF
Harmonic Filter
L4
8.2 nH
L5
8.2 nH
C15
4.7 pF
C16
6.8 pF
C17
4.7 pF
Rev. A | Page 22 of 28
ADF7012
915 MHz OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to FCC site testing.
Matching components need to be adjusted for board layout.
FCC 15.247 and FCC 15.249 are the main regulations governing
operation in the 902 MHz to 928 MHz Band. FCC 15.247
requires some form of spectral spreading. Typically, the
ADF7012 would be used in conjunction with the frequency
hopping spread spectrum (FHSS) or it may be used in
conjunction with the digital modulation standard which
requires large deviation frequencies. Output power of < 1 W
is tolerated on certain spreading conditions.
Compliance with FCC 15.249 limits the output power to
−1.5 dBm, but does not require spreading. There are many
different applications in this band, including remote controls
for security, sensor interrogation, metering, and home control.
The modulation steps available are in 10 MHz/214 :
Modulation steps = 610 Hz
Modulation number = 19.2 kHz/610 Hz = 31.
Bias Current
Because low current is desired, a 3 mA VCO bias can be used
and still ensure oscillation at 928 MHz. Additional bias current
reduces any spurious noise, but increases current consumption.
A 3 mA bias current gives the best spurious vs. phase noise
trade-off.
The PA bias should be set to 5.5 mA to achieve 10 dBm power.
The loop filter is designed with the ADIsimSRD Design Studio.
A data rate of 170 kHz is chosen, which allows for data rates of
> 38.4 kbps. It also attenuates the beat note spurs quickly to
ensure they have no effect on system performance.
915.2MHz center frequency
FSK modulation
10 dBm output power
200 m range
Meets FCC 15.247
38.4 kbps data rate
Design of Harmonic Filter
The center frequency is 915.2 MHz. It is possible to operate
the VCO at this frequency. Figure 36 shows the inductor value
vs. center frequency. The inductor chosen is 1.6 nH. Coilcraft
inductors such as 0603-CS-1N6XJBU are recommended.
Additional hopping frequencies can easily be generated by
changing the N value.
Crystal and PFD
The phase noise requirement is such to ensure that the 20 dB
bandwidth requirements are met. These are dependent on the
channel spacing chosen. A typical channel spacing would be
400 kHz, which would allow 50 channels in 20 MHz and enable
the design to avoid the edges of the band.
The PFD is chosen to minimize spurious levels. There are beat
note spurious levels at 910 MHz and 920 MHz, but the level is
usually significantly less than the modulation power. They are
also attenuated quickly by the loop filter to ensure a quick
crystal power-up time.
PFD = 10 MHz − Power-Up Time 1.8 ms (approximately).
Figure 10 shows a typical power-on time for a 4 MHz crystal.
The N divider is determined as being:
Nint = 91
Nfrac = (2130)/4096
VCO divide-by-2 is not enabled
The deviation is set to ±19.2 kHz to accommodate a simple
receiver architecture, and to ensure the available spectrum is
used efficiently.
Loop Filter Bandwidth
Design Criteria
N-Divider
Deviation
The main requirement of the harmonic filter should ensure
that the third harmonic level is < −41.5 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a suggested starting point is given next. The Pi format is chosen
to minimize the number of inductors in the system.
Component Values—Crystal: 10 MHz
Loop Filter
Icp
1.44 mA
LBW
170 kHz
C1
470 pF
C2
12 nF
C3
120 pF
R1
470 Ω
R2
1.8 kΩ
Matching
L1
27 nH
L2
6.2 nH
C14
470 pF
Harmonic Filter
L4
8.2 nH
L5
8.2 nH
C15
4.7 pF
C16
6.8 pF
C17
4.7 pF
Rev. A | Page 23 of 28
ADF7012
REGISTER DESCRIPTIONS
DB15
DB14
DB13
DB12
R3
R2
R1
F11
OD2
OD1
OUTPUT DIVIDER
0
0
1
1
0
1
0
1
DISABLED
DIVIDE BY 2
DIVIDE BY 4
DIVIDE BY 8
VA2
VA1
VCO ADJUST
0
0
1
1
0
1
0
1
NO VCO ADJUSTMENT
.......
.......
MAX VCO ADJUSTMENT
CL4
0
0
0
0
.
.
.
1
1
CL3
0
0
0
1
.
.
.
1
1
CL2
0
1
1
0
.
.
.
1
1
CL1
1
0
1
0
.
.
.
0
1
CLKOUT
DIVIDE RATIO
2
4
6
8
.
16 (DEFAULT)
.
28
30
Figure 41. Register 0: R Register
Rev. A | Page 24 of 28
DB4
DB3
DB2
DB1
DB0
F2
F1
C2 (0)
C1 (0)
DB5
F3
DB6
F4
F7
RL4
0
0
0
0
.
.
.
1
1
1
1
F5
DB8
F8
X1 XOEB
0
XTAL OSCILLATOR ON (DEFAULT)
1
XTAL OSCILLATOR OFF
DB7
DB9
F9
D1 CRYSTAL DOUBLER
0
CRYSTAL DOUBLER OFF
1
CRYSTAL DOUBLER ON
F6
DB11
DB10
F10
11-BIT FREQUENCY ERROR CORRECTION
F11
.......
F3
F2
F1
F-COUNTER
OFFSET
0
0
0
0
0
.......
.......
.......
.......
.......
1
1
.
0
0
0
0
.
0
0
0
1
.
1
0
+1023
+1022
.
+1
+0
1
1
.
1
1
.......
.......
.......
.......
.......
1
1
.
0
0
1
1
.
0
0
1
0
.
1
0
–1
–2
–3
–1023
–1024
RL3
0
0
0
1
.
.
.
1
1
1
1
RL2
0
1
1
0
.
.
.
0
0
1
1
RL1
1
0
1
0
.
.
.
0
1
0
1
RF R COUNTER
DIVIDE RATIO
1
2
3
4
.
.
.
12
13
14
15
04617-0-027
DB16
4-BIT R DIVIDER
ADDRESS
BITS
DB17
X1
DB19
CL1
R4
DB20
CL2
XOEB
DB21
CL3
CRYSTAL
DOUBLER
DB22
D1
DB23
DB24
VA2
VA1
DB25
OD1
CLOCK OUT
DIVIDER
CL4
DB26
OD2
DB27
DB28
DB29
DB30
DB31
OUTPUT
VCO
DIVIDER ADJUST
DB18
REGISTER 0: R REGISTER
ADF7012
ADDRESS
BITS
0
0
1
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
0
1
2
.
.
.
4092
4093
4094
4095
N2
0
0
1
.
.
.
1
1
N1
0
1
0
.
.
.
0
1
Rev. A | Page 25 of 28
DB0
C1 (1)
N-COUNTER
DIVIDE RATIO
0
1
2
.
.
.
254
255
THE N-VALUE CHOSEN IS A MINIMUM OF
P2 + 3P + 3. FOR PRESCALER 8/9 THIS
MEANS A MINIMUM N-DIVIDE OF 91. FOR
PRESCALER 4/5 THIS MEANS A MINIMUM
N-DIVIDE OF 31.
Figure 42. Register 1: N-Counter Latch
DB1
M7
0
0
0
.
.
.
1
1
1
1
DB2
DB8
M8
MODULUS
DIVIDE RATIO
M1
DB9
M9
M1
C2 (0)
DB11
DB10
M10
N3
0
0
0
.
.
.
1
1
DB3
DB12
M11
N4
0
0
0
.
.
.
1
1
M2
DB13
N5
0
0
0
.
.
.
1
1
M2
04617-0-028
N6
0
0
0
.
.
.
1
1
.......
.......
.......
.......
.......
.......
.......
.......
.......
.......
DB4
DB14
N1
M12
0
0
0
.
.
.
1
1
1
1
DB5
DB16
N3
DB15
0
0
0
.
.
.
1
1
1
1
M3
DB17
N4
N2
0
0
0
.
.
.
1
1
1
1
M4
DB18
N5
M3
M11
DB6
DB19
N6
P1 PRESCALER
0
4/5
1
8/9
N7
0
0
0
.
.
.
1
1
M10 .......
M12
M5
DB20
N7
N8
0
0
0
.
.
.
1
1
12-BIT FRACTIONAL-N
DB7
DB21
8-BIT INTEGER-N
M6
DB22 PRESCALER
P1
N8
DB23
REGISTER 1: N-COUNTER LATCH
ADF7012
DB2
DB1
DB0
S1
C2 (1)
C1 (0)
ADDRESS
BITS
MOD
CONTROL
DB3
DB4
S2
GOOK
DB5
P1
DB12
D2
G1
DB13
D3
DB6
DB14
D4
P2
DB15
D5
MUST BE LOW
DB7
DB16
D6
DB8
DB17
D7
P4
DB18
D8
DB9
DB19
D9
P5
DB20
MC1
DB11
DB21
MC2
DB10
DB22
MC3
P6
DB23
IC1
POWER AMPLIFIER
DB24
MODULATION DEVIATION
P3
GFSK MOD
CONTROL
IC2
DB25
G1 GAUSSIAN OOK
0 OFF
1 ON
S2
S1
0
0
1
1
0
1
0
1
MODULATION
SCHEME
FSK
GFSK
ASK
OOK
IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0
POWER AMPLIFIER OUTPUT LEVEL
D6
0
.
.
1
P6
0
.
.
1
.
.
.
.
1
.
.
.
.
1
D2
0
0
.
1
D1
0
1
.
1
PA OFF
PA MAX
IF FREQUENCY SHIFT KEYING SELECTED
D9
0
0
0
0
.
1
.......
.......
.......
.......
.......
.......
.......
D3
0
0
0
0
.
1
D2
0
0
1
1
.
1
D1
0
1
0
1
.
1
.
.
.
.
1
.
.
.
.
1
P2
0
0
.
1
P1
0
1
.
1
PA OFF
PA MAX
FSTEP = FPFD /214
F DEVIATION
PLL MODE
1 × FSTEP
2 × FSTEP
3 × FSTEP
.......
511 × FSTEP
IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED
IC2
0
0
1
1
IC1
0
1
0
1
INDEX COUNTER
16
32
64
128
MC3
0
0
.
1
MC2
0
0
.
1
MC1
0
1
.
1
GFSK MOD CONTROL
0
1
.
7
D7
0
0
0
0
.
1...
.......
.......
.......
.......
.......
.......
.......
D3
0
0
0
0
.
1
D2
0
0
1
1
.
1
Figure 43. Register 2: Modulation Register
Rev. A | Page 26 of 28
D1
0
1
0
1
.
1
DIVIDER FACTOR
0
1
2
3
.......
127
04617-0-029
DB26
DB27
DB28
DB29
DB30
DB31
TEST BITS
D1
INDEX
COUNTER
REGISTER 2: MODULATION REGISTER
ADF7012
DB11
DB10
DB9
M1
VD1
CP4
ADDRESS
BITS
DATA
INVERT
CLKOUT
ENABLE
PA
ENABLE
PLL ENABLE
DB0
DB12
M2
PA ENABLE
PA OFF
PA ON
PD3
CLKOUT
0
1
CLKOUT OFF
CLKOUT ON
04617-0-030
MUXOUT
LOGIC LOW
LOGIC HIGH
INVALID MODE – DO NOT USE
REGULATOR READY (DEFAULT)
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
R DIVIDER/2 OUTPUT
N DIVIDER/2 OUTPUT
RF R DIVIDER OUTPUT
DATA RATE
BATTERY MEASURE IS < 2.35V
BATTERY MEASURE IS < 2.75V
BATTERY MEASURE IS < 3V
BATTERY MEASURE IS < 3.25V
NORMAL TEST MODES
Σ-Δ TEST MODES
Rev. A | Page 27 of 28
PD2
0
1
PLL ENABLE
PLL OFF
PLL ON
CHARGE PUMP
CURRENT
0.3mA
0.9mA
1.5mA
2.1mA
VCO DISABLE
VCO ON
VCO OFF
Figure 44. Register 3: Function Register
DB1
DB13
M3
M1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C1 (1)
DB14
M4
M2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
C2 (1)
DB15
LD1
M3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
DB2
DB16
VB1
M4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VD1
0
1
CP1
PD1
DB17
VB2
LD PRECISION
3 CYCLES (DEFAULT)
5 CYCLES
PD1
0
1
BLEED UP
BLEED OFF (DEFAULT)
BLEED ON
CP2
DB3
DB18
VB3
1mA
.
8mA
DB4
DB19
VB4
LD1
0
1
VCO BIAS
CURRENT
0.5mA
DATA INVERT
NORMAL
INVERTED
BLEED DOWN
BLEED OFF (DEFAULT)
BLEED ON
CP3
0
1
PD2
DB20
PA1
VB1
1
0
.
1
PD3
DB21
PA2
6µA
7µA
.
.
12µA
DB5
DB22
PA3
VB2
0
1
.
1
CP4
0
1
PA BIAS
5µA
I1
DB23
PT1
VB3
0
0
.
1
PA1
0
1
0
.
.
1
DB6
DB24
PT2
VB4
0
0
.
1
PA2
0
0
1
.
.
1
DB7
DB25
PT3
PA3
0
0
0
.
.
1
CP1
DB26
PT4
I1
0
1
CP2
DB27
PT5
DB8
DB28
ST1
CP3
VCO
DISABLE
DB29
BLEED CHARGE
CURRENT PUMP
ST2
MUXOUT
DB30
VCO BIAS
ST3
PA BIAS
DB31
PLL TEST
MODES
ST4
SD TEST
MODES
LD
PRECISION
REGISTER 3: FUNCTION REGISTER
ADF7012
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
4.50
4.40
4.30
1
6.40 BSC
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
0.10 COPLANARITY
1.20
MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 45. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADF7012BRU1
ADF7012BRU-REEL1
ADF7012BRU-REEL71
ADF7012BRUZ1
ADF7012BRUZ-RL1
ADF7012BRUZ-RL71
EVAL-ADF7012DBZ11
EVAL-ADF7012DBZ21
EVAL-ADF7012DBZ31
EVAL-ADF7012DBZ41
EVAL-ADF7012DBZ51
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead TSSOP
24-Lead TSSOP, 13” REEL
24-Lead TSSOP, 7” REEL
24-Lead TSSOP
24-Lead TSSOP, 13” REEL
24-Lead TSSOP, 7” REEL
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04617-0-6/09(A)
Rev. A | Page 28 of 28
Package Option
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
Frequency Range
75 MHz to 1 GHz
75 MHz to 1 GHz
75 MHz to 1 GHz
75 MHz to 1 GHz
75 MHz to 1 GHz
75 MHz to 1 GHz
902 MHz to 928 MHz
860 MHz to 880 MHz
418 MHz to 435 MHz
310 MHz to 330 MHz
75 MHz to 1 GHz