10/02/2015
Vivado 2014.4 Windows Basic System
Contents
1
History ........................................................................................................................... 2
2
Introduction .................................................................................................................... 2
3
Open Vivado .................................................................................................................. 3
4
New Project ................................................................................................................... 4
5
Project Settings ............................................................................................................ 12
6
Create Processor System ............................................................................................ 13
6.1
New Block Diagram .............................................................................................. 13
6.2
Generate Output Products .................................................................................... 17
6.3
HDL Wrapper ........................................................................................................ 18
7
Implement Design ........................................................................................................ 20
8
Export Hardware .......................................................................................................... 22
9
Launch SDK................................................................................................................. 23
10
New Application Project............................................................................................ 25
10.1
Hello ..................................................................................................................... 25
10.2
Bootloader ............................................................................................................ 27
10.3
Bootloader debug flags ......................................................................................... 29
11
Program FPGA ......................................................................................................... 30
12
Debug ...................................................................................................................... 31
12.1
Setup .................................................................................................................... 31
12.2
Configure .............................................................................................................. 31
12.3
Debug Application ................................................................................................. 34
13
Boot Image ............................................................................................................... 38
14
MicroSD ................................................................................................................... 39
14.1
Set Avnet MicroZed Development Board Boot Mode ............................................ 39
14.2
Configure HyperTerminal ...................................................................................... 40
14.3
Reset Avnet MicroZed Development ..................................................................... 40
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Vivado 2014.4 Windows Basic System
1 History
Revision
A
Date
5/2/2015
Author
Description
[email protected] Initial Revision
Table 1 : History
2 Introduction
This document describes how to build a Processor System (PS) system for the Avnet
MicroZed development board using Vivado 2014.4 on Windows 7 Professional
Service pack 1 (64-bit) Host.
•
•
•
•
•
•
•
•
•
Create Block Diagram
Implement design
Export hardware to SDK
Launch SDK
Create application
Create bootloader
Debug application (Avnet MicroZed)
Create boot image
Boot FPGA from Micro SD card (Avnet MicroZed)
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3 Open Vivado
“Start -> All Programs -> Xilinx Design Tools -> Vivado 2014.4 -> Vivado 2014.4” or
Double click on “Vivado 2014.4” desktop icon.
Figure 1: Vivado
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4 New Project
Create a new Vivado project.
“File -> New Project”.
Figure 2: Vivado
Click on the “Next” button.
Figure 3: New Project - Create a New Vivado Project
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Select Project Name and Location.
“Project name: -> basic_test”
“Project location: -> I:/Syfer/CAD/Projects/Xilinx/microzed/vivado_2014_4/basic_system”
Click on the “Create project subdirectory” check box to un-check.
Click on the “Next” button.
Figure 4: New Project – Project Name
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Select the Project Type.
Click on the “RTL Project” radio button to select.
Click on the “Next” button.
Figure 5: New Project - Project Type
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Add HDL Source Files.
No HDL sources are required to be added at this stage.
Click on the “Next” button.
Figure 6: New Project - Add Sources
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Add Existing IP.
No Existing IP are required to be added at this stage.
Click on the “Next” button.
Figure 7: New Project – Add Existing IP (optional)
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Add Constraints.
No constraints are required to be added at this stage.
Click on the “Next” button.
Figure 8: New Project - Add Constraints (Optional)
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Select Development Board.
Select “MicroZed Board”.
Note: Ensure that Revision F is selected.
Click on the “Next” button.
Figure 9: New Project - Default Part
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Project Summary.
Click on the “Finish” button.
Figure 10: New Project - New Project Summary
Figure 11: Vivado (New Project)
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5 Project Settings
“Tools -> Project Settings”.
Select “General”.
Select “Target language: -> VHDL”
Click on the “OK” button.
Figure 12: Project Settings - General
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6 Create Processor System
6.1 New Block Diagram
“Flow -> Create Block Diagram”.
Type “Design name -> system”.
Click on the “OK” button.
Figure 13: Create Block Diagram
Click on the “Add IP” button in the “Diagram” window.
Click on the “ZYNQ7 Processing System” IP.
Press “Enter” to add IP.
Figure 14: ZYNQ7 Processing System IP
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ZYNQ7 Processing System block diagram without connections.
Figure 15: Vivado – Add ZYNQ7 Processing System IP (Complete)
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Make external connections.
Click on the “Run Block Automation” hyperlink.
Click on the “OK” button.
Figure 16: ZYNQ7 Processing System IP (Run Block Automation)
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Validate Design.
“Tools -> Validate Design”.
Figure 17: Vivado – ZYNQ7 Processing System IP (Run Block Automation Complete)
Click on the “OK” button.
Figure 18: Validate Design
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6.2 Generate Output Products
Click on the “Sources” tab in the “Sources” window and select “system” block diagram.
Right click and select “Generate Output Products”.
Click on the “Generate” button.
Figure 19: Generate Output Products
Click on the “OK” button.
Figure 20: Generate Output Products - Complete
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6.3 HDL Wrapper
Click on the “Sources” tab in the “Sources” window and select “system” block diagram.
Right click and select “Generate Output Products”.
Click on the “Copy generated wrapper to allow user edits” radio button to select.
Click on the “OK” button.
Figure 21: Create HDL Wrapper
Click on the “OK” button.
Figure 22: Create HDL Wrapper (Complete)
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HDL Wrapper.
Figure 23: Vivado - HDL Wrapper
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7 Implement Design
“Flow -> Run Implementation”
Vivado lets the user know if any dependent sources are missing or out of date.
Click on the “OK” button.
Figure 24: Vivado – Missing Synthesis Results
Click on the “Generate Bitstream” radio button to select.
Figure 25: Implementation Completed
Click on the “Open Implemented Design” radio button to select.
Click on the “OK” button.
Figure 26: Bitstream Generation Completed
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Take a few moment to explore the implemented design in the “Device” window.
Figure 27: Vivado - Implemented Design
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8 Export Hardware
Export hardware to SDK.
“File -> Export Hardware”
Click on the “Include bitstream” check box to select.
Click on the “OK” button.
Figure 28: Export Hardware
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9 Launch SDK
“File -> Launch SDK”
Click on the “OK” button.
Figure 29: Launch SDK
Click on the “Allow access” button.
Figure 30: Windows Security Alert
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Figure 31: SDK Project
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10 New Application Project
10.1 Hello
“File -> New Application Project”
Type “Project name -> hello”.
Click on the “Next” button.
Figure 32: Hello Application Project
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Select “Hello World” template.
Click on the “Finish” button.
Figure 33: Hello World
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10.2 Bootloader
“File -> New -> Application Project”
Type “Project name -> zynq_fsbl”.
Click on the “Next” button.
Figure 34: Bootloader Application Project
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Select “Zynq FSBL” template.
Click on the “Finish” button.
Figure 35: Zynq fsbl
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10.3 Bootloader debug flags
Set Debug flags for “zynq_fsbl”.
Select the “zynq_fsbl” application in the “Project Explorer” window, right click
and select “Properties”.
Select “C/C++ Build -> Settings”
Select “Tool Settings” tab.
Select “ARM gcc compiler -> Debugging”
Type “-DFSBL_DEBUG_INFO=1” for “Other debugging flags”.
Figure 36: "zynq_fsbl" properties
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11 Program FPGA
Ensure that the Xilinx Platform Cable USB is connected to the target and the target is
powered. The Xilinx Platform Cable USB LED should be green.
“Xilinx Tools -> Program FPGA”.
Select “Bitstream: -> system_wrapper.bit”.
Click on the “Program” button.
Figure 37: Program FPGA
Ensure that the DONE LED “D2” is turned off then on to signify successful configuration.
The “SDK Log” will also indicate Programming Status.
Ensure that Programming was successful.
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12 Debug
12.1 Setup
Ensure that the Xilinx Platform Cable USB is connected to the target and the target is
powered. The Xilinx Platform Cable USB LED should be green.
On the Windows 7 Host open HyperTerminal.
Configure HyperTerminal with settings 115200/8/n/1/n.
12.2 Configure
Select “hello” in the “Project Explorer” window.
“Run -> Debug Configurations”.
Select “Xilinx C/C++ application (GDB)”, right click and select “New”.
Figure 38: Debug Configurations
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Select “hello Debug”.
Select the “Target Setup” tab.
Set “Initalization file: -> ps7_init.tcl”
Click on the “Run ps7_init” check box to select.
Click on the “Run ps7_post_config” check box to select.
Note: “Run ps7_post_config” sets the SLCR registers to enable level shifters, FPGA reset
and AFI registers. AXI communication will fail if the SLCR registers are not configured.
Figure 39: Debug Configurations - Target setup
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Select the “Application” tab.
Select “Project Name -> hello” by clicking on the “Browse” button.
Select “Application: -> Debug/hello.elf” by clicking on the “Search” button.
Click on the “Close” button.
Figure 40: Debug Configurations - Application
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12.3 Debug Application
Select the “hello” application in the “Project Explorer” window.
Click on the “Perspective”
button.
Figure 41: SDK
Select “Debug”.
Click on the “OK” button.
Figure 42: Open Perspective
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“Run -> Debug”
Figure 43: Debug –Debug Perspective
Execution is halted at main.
Use “ctrl + double click” and click on the “OK” button to add break point.
Use right click for breakpoint control.
“Run -> Resume”.
Figure 44: Debug - Add breakpoint
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Execution halts at breakpoint.
“Run -> Resume”.
Figure 45: Debug - “hello.elf” stopped at breakpoint
Execution complete.
Figure 46: “hello.elf” execution complete
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Terminate application.
“Run -> Terminate”.
Figure 47: Terminate Application
Close “SDK”.
Ensure that HyperTerminal output displays “Hello World”
Figure 48: HyperTerminal
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13 Boot Image
Select the “hello” application in the “Project Explorer” window, right click and
select “Create Boot Image”.
“system_wrapper.bit” and “hello.elf” are type “datafile”.
zynq_fsbl.elf” is type “bootloader”
Click on the “Create Image” button.
Figure 49: Create Zynq Boot Image
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14 MicroSD
MicroSD must be formatted as FAT32.
The “BOOT.bin” from
“I:\Syfer\CAD\Projects\Xilinx\microzed\vivado_2014_4\basic_system\basic_test.sdk\hello\bo
otimage”can be copied directly to the MicroSD card.
Alternatively “bootimage.bif” has been copied and modified in the
“I:\Syfer\CAD\Projects\Xilinx\microzed\vivado_2014_4\basic_system\download\sd_image”.
Run “build_microsd_image.bat” to build “BOOT.bin”
14.1 Set Avnet MicroZed Development Board Boot Mode
Disconnect power from the Avnet MicroZed Development Board.
Insert Micro SD card into Avnet MicroZed Development Board Micro SD card connector “J6”.
Set the Avnet MicroZed Development Board Boot Mode to “Micro SD”.
JP3=2,3
JP2=2,3
Jp1=1,2
Figure 50: Boot Mode
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14.2 Configure HyperTerminal
Connect USB cable to PC and Avnet MicroZed Development Board “J2”.
On the Windows 7 Host open HyperTerminal.
Configure HyperTerminal with settings 115200/8/n/1/n.
Figure 51: HyperTerminal
14.3 Reset Avnet MicroZed Development
Press “SW2” on the Avnet MicroZed Development Board to reset the PS.
Figure 52: HyperTerminal
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