CSCI206 Activity 11: Exam 1 Review

Name:__________________________ Instruction Encoding
For each of the assembly instructions below, select the instruction format, complete the appropriate instruction fields with
a numeric value
(use binary, decimal, or hexadecimal; if a field is not used, leave it blank), and show the generated MIPS binary machine code
as a binary and hexadecimal value
. You may use the MIPS reference data (green sheet). 1. sll $s1, $s0, 8 Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ binary machine code: ________________________________________________ hexadecimal machine code: ___________________________________________ If $s0 = 0xABCD1234 and $s0 = 0 before the instruction, what are their values after? $s0 = ____________________________ $s1 = ____________________________ 2. bne $t3, $s2, 255 Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ binary machine code: ________________________________________________ hexadecimal machine code: ___________________________________________ If $t3 is
not equal to
$s2 and this instruction is at PC = 0x1000, what is the next PC? PC = ____________________________ 3. sw $a0, 8($t2) Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ binary machine code: ________________________________________________ hexadecimal machine code: ___________________________________________ If $a0 = 0x0100 and $t2 = 0x1000 what address is modified and what is the new value? modified address: ____________________________ = value: _______________ 4. j 0x1c00ff Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ binary machine code: ________________________________________________ hexadecimal machine code: ___________________________________________ If this instruction is at PC = 0x4000, what is the next PC? PC = ____________________________ Instruction Decoding
Decode the following mips binary instructions. Indicate the value for each field with a numeric value (if a field is not used, leave it blank). 1.0000 0010 0001 0000 1000 0000 0010 0000 Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ assembly instruction: ________________________________________________ 2.0x240a0000 Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ assembly instruction: ________________________________________________ 3.0001 0001 0010 1010 0000 0000 0000 0011 Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ assembly instruction: ________________________________________________ 4.0x2210002a Format (R, I, J, pseudo): _______________________________ opcode: _______ rs: ______ rt: ______ rd: ______ shamt: ______ funct: ______ immediate: ____________ address: ____________________________________ assembly instruction: ________________________________________________ Number Representation
Complete the table below showing the interpretation of the binary value in each format. binray unsigned int sign + magnitude 1’s comp 2’s comp biased B=8 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Assembly Structures
Convert the following C structures into MIPS assembly (pseudoinstructions are acceptable). Assume that C variables
a, i, x,
and
y
are loaded into registers
$s0, $s1, $s2,
and
$s3 respectively. Array
nums
is located in the data segment and has the same label in assembly. Example: C Code i = x + y; MIPS Assembly add $s1, $s2, $s3 1. while (i > 0){ a = a + 1; i = i 1; } 2. if (x != y) { a = a * 2; } else { a = a / 2; } 3. a = 0; i = 0; do { a = a + nums[i]; i = i + 1; } while (i < 100); 4. switch (x){ case 2: a = ‘X’; break; case 4: a = ‘Y’; break; case 8: a = ‘Z’; break; default: a = ‘\0’; break; } C Programming
1. Define a C struct for holding bank account information. This information should include: ○ Name ○ Balance ○ Address (street address, city, state, zip code) ○ Phone number (including area code) 2. Write C code that declares and initializes a pointer to an instance of
struct bank_account
allocated on the stack. 3. Write C code that declares an array of 100
struct bank_account
instances on the stack. 4. Write the function
print_account
that takes a pointer to a
struct bank_account
and uses
printf
to nicely output the account information to the terminal as shown in this example: Your Name
Balance: $99,999.00 124 Some Street Lewisburg, PA 17837 (123)1231234 5. Write the function
save_account
that accepts a pointer to a
struct bank_account and a
filename
and writes the bank account info to the specified file. Misc
1. Assume that we would like to expand the MIPS register file to 128 registers and expand the instruction set to contain four times as many instructions. ● How would this affect the size of each of the bit fields in the Rtype instructions? ● How would this affect the size of each bit field in the Itype instructions? ● How could each of the two proposed changes decrease the size of a MIPS assembly program? ● How could each of the two proposed changes increase the size of a MIPS assembly program? 2. The following instruction is not included in the MIPS instruction set: rpt $t2, loop # if (R[rs]>0) R[rs]=R[rs]1, PC=PC=4+BranchAddr ● If this instruction were to be implemented in the MIPS instruction set, what is the most appropriate instruction format? ● What is the shortest sequence of MIPS instructions that performs the same operation? 3. What is the range of addresses for conditional branches in MIPS? 4. What is the range of addresses for a jump in MIPS? 5. Write the following function in MIPS assembly language. Assume
func
is declared elsewhere with signature:
int f(int a, int b)
. int f(int a, int b, int c, int d){ return func(func(a,b), c+d); } Performance
1. Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3. Assume a program has the following instruction breakdowns; 500 million arithmetic instructions, 300 million load/store instruction, 100 million branch instructions. a. Suppose that more powerful arithmetic instructions are added to the ISA. On average, the use of these instructions will reduce the number of required operations by 25%. However, adding these instructions will the overall clock cycle time by 10%. Argue whether you should implement these instructions on not. b. Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? c. Suppose that we find a way to improve the performance of the arithmetic instructions by 10 times. What is the overall speedup of our machine? 2. Assume that for a given program 70% of the executed instruction are arithmetic, 10% load/store, and 20% branch. a. Given this instruction mix and the assumption that an arithmetic instruction requires 2 cycles, a load/store takes 6 cycles, and a branch takes 3 cycles, find the average CPI. b. To yield a 25% improvement in performance, how many cycles on average should an arithmetic instruction take if load/store and branch instructions are not improved at all? c. For a 50% improvement in performance; how many cycles on average should an arithmetic instruction take if load/store and branch instructions are not improved at all?