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積體電路製程先進技術與設備 Processing Technology and Equipment for Advanced Semiconductor Manufacturing Week 4 半導體製程概論 (III) 陳國聲 教授 March 27, 2015 Agenda – Lithography – Etching – Metallization and Interconnections – Polishing –Testing and Packaging – Mechanics issues Part I. Lithography IC Processing Flow Materials IC Fab Metallization CMP Dielectric deposition Test Wafers Thermal Processes Masks Implant PR strip Photolithograph y IC Design Etch PR strip Packaging Final Test Photomask and Reticle for Microlithography 1:1 Mask 4:1 Reticle Photograph provided courtesy of Advanced Micro Devices Photo 13.1 Process Overview Negative and Positive Photoresists Photoresist Substrate UV light Mask/reticle Photoresist Exposure Substrate Negative Photoresist Substrate Positive Photoresist Substrate After Development Relationship Between Mask and Resist Island of photoresist Desired photoresist structure to be printed on wafer Substrate Chrome Quartz Window Island Mask pattern required when using negative photoresist (opposite of intended structure) Figure 13.7 Mask pattern required when using positive photoresist (same as intended structure) Clear Field and Dark Field Masks Clear Field Mask Dark Field Mask Simulation of metal interconnect lines (positive resist lithography) Simulation of contact holes (positive resist lithography) Figure 13.8 Importance of Mask Overlay Accuracy Top view of CMOS inverter The masking layers determine the accuracy by which subsequent processes can be performed. The photoresist mask pattern prepares individual layers for proper placement, orientation, and size of structures to be etched or implanted. PMOSFET NMOSFET Small sizes and low tolerances do not provide much room for error. Cross section of CMOS inverter Figure 13.4 Layout and Dimensions of Reticle Patterns 1) STI etch 2) P-well implant 3) N-well implant 4) Poly gate etch 5) N+ S/D implant 6) P+ S/D implant 7) Oxide contact etch 8) Metal etch 5 6 4 Resulting layers 3 2 7 8 1 Top view Figure 14.2 Cross section Section of the Electromagnetic Visible Spectrum X-rays Gamma rays f (Hz) (m) 10 22 -14 10 (nm) 10 20 -12 10 10 -10 10 Infrared UV 18 10 10 -8 16 Microwaves 10 10 14 10 -6 10 157 193 248 365 VUV DUV DUV i 12 -4 10 10 Radio waves 10 -2 10 10 0 405 436 h g Common UV wavelengths used in optical lithography. Figure 13.3 8 10 10 2 6 10 10 4 4 Photoresist Contrast • An important performance index for PR • = 1/(log10(D100/D0)) • Typical = 2 – 3. High = sharp edge Eight Steps of Photolithography UV Light HMDS Resist Mask 1) Vapor prime 2) Spin coat 3) Soft bake 4) Alignment and Exposure 5) Post-exposure bake 6) Develop 7) Hard bake 8) Develop inspect Figure 13.9 Alignment and Exposure • • • • • Most critical process for IC fabrication Most expensive tool (stepper) in an IC fab. Most challenging technology Determines the minimum feature size Tools: – – – – Contact printer Proximity printer Projection printer Stepper • Simple equipment • Use before mid-70s • Resolution: capable Lenses for sub-micron • Direct mask-wafer contact, limited Mask mask lifetime Photoresist • Particles Contact Printer Light Source Wafer Contact Printing UV Light PR N-Silicon Mask Proximity Printer • ~ 10 mm from wafer surface • No direct contact • Longer mask Lenses lifetime • Resolution: > 3 mm Light Source Mask Photoresis t Wafer ~10 mm Proximity Printing ~10 mm UV Light PR N-Silicon Mask Scanning Projection System Slit Light Source Lens Mask Synchronized mask and wafer movement Lens Photoresist Wafer Step-&-Repeat Alignment/Exposure Step and Scan Exposure System Excimer laser Illuminator (193 nm ArF ) optics Reticle library (SMIF pod interface) Beam line Wafer transport system Operato r console Reticle stage Wafer stage Auto-alignment system 4:1 Reduction lens NA = 0.45 to 0.6 Used with permission from ASML, PAS 5500/900 Figure 14.38 Light Diffraction Without Lens Diffracted light Mask Intensity of the projected light • Short wavelength waves have less diffraction • Optical lens can collect diffracted light and enhance the image Resolution • The achievable, repeatable minimum feature size • Determined by the wavelength of the light and the numerical aperture of the system. The resolution can be expressed as K1 R NA • K1 is the system constant, is the wavelength of the light, NA = 2 ro/D, is the numerical aperture • NA: capability of lens to collect diffraction light Depth of Focus • The range that light is in focus and can achieve good resolution of projected image • Depth of focus can be expressed as: K 2 DOF 2 2( NA) K2 DOF 2( NA) 2 Focus Next Generation Lithography (NGL) • Extreme UV (EUV) lithography • Electron beam (E-beam) lithography • X-Ray lithography Photolithography 1.6 Feature Size (mm) 1.4 1.5 1.2 Maybe photolithography 1.0 1 Next Generation Lithography 0.8 0.8 0.5 0.6 0.35 0.4 0.25 0.2 0.18 0.13 0.10 0.07 0 84 88 90 93 95 98 Year 01 04 07 10 14 5 DOF Wafer Stepper Dr. M. Williams, MIT 6 DOF Wafer Scanner Prof. W. Kim, Texas A&M 6 DOF Wafer Scanner Prof. W. Kim, Texas A&M The Å Stage of MIT Dr. S. Ludwick, Aerotech Part II. Etching Wafer Process Flow Materials IC Fab Metallization CMP Dielectric deposition Test Wafers Thermal Processes Masks Implant PR strip Photolithography Design Etch PR strip Packaging Final Test AFM Tips STATE UNIVERSITY OF NEW YORK at STONY BROOK Yu-Hsuan Su Deep Reactive Ion Etching (DRIE) STATE UNIVERSITY OF NEW YORK at STONY BROOK Yu-Hsuan Su Examples of Overhang Structures Gate Mask Alignment Gate Mask Photoresist Polysilicon STI USG P-Well Gate Mask Exposure Gate Mask Photoresist Polysilicon STI USG P-Well Development/Hard Bake/Inspection PR Polysilicon STI USG P-Well Etch Polysilicon Polysilicon PR STI USG P-Well Etch Polysilicon, Continue Gate Oxide Polysilicon PR STI USG P-Well Strip Photoresist Gate Oxide Polysilicon STI USG P-Well Ion Implantation + Dopant Ions, As Gate Oxide STI n+ n+ Polysilicon USG P-Well Source/Drain Rapid Thermal Annealing Gate Oxide STI Polysilicon Gate n+ n+ USG P-Well Source/Drain Wet Etching • Remove materials by wet chemistry • Basic mechanisms – Reactant transport to surface – Surface reaction – Reaction product removal from surface • Advantages – High selectivity and inexpensive • Disadvantages – Isotropic, loss of resolution through undercut – Temperature/agitation sensitivity – Surface tension, bubble formation, wetting, solution degradation – Waste disposal Wet Oxide Etch • The most important wet etch • Typical reaction formula SiO 2( s ) 6HF( aq ) H2( g ) SiF6( g ) 2H2O( l ) • NH4F is usually added into HF as the buffer agent. We called buffered oxide etch (BOE) • Etch rate is ~ 0.5 mm/min. Depends on temperature, concentration, and type of oxide – Dry oxide has lowest etch rate – CVD oxide has much high etch rate 46 Wet Chemical Isotropic Etch Isotropic etch - etches in all directions at the same rate Resist Film Substrate Figure 16.4 Dry Etching Techniques • Physical bombardment (sputtering) – Ion milling, sputter etching • Chemical reaction – Pure plasma etching – Dry equivalent of wet chemistry (e.g., SF6 etching for silicon) • Combination of physical and chemical mechanisms – Plasma etching: with bombardment – Reactive ion etching (RIE) Chemical and Physical Dry Etch Mechanisms Physical Etching Chemical Etching Sputtered surface material Reactive +ions bombard surface Surface reactions of radicals + surface film Desorption of byproducts Isotropic etch Anisotropic etch Figure 16.12 Dry Etching Introduction RF Field Vacuum Transport Gas in CF4 Transport Plasma Reaction Plasma Reaction CF4 + e -> CF3+ + Fo + e Surface Reaction Si + 4F -> SiF4 Deposit Transport Gas Out CF4, SiF4 Surface Reaction Deposits C, C:F Polymers Selectivity • Selectivity of BPSG to Poly-Si: S = PR E2 BPSG Gate SiO2 Poly-Si Si E1 E1 E2 Part III. Metalization / Interconnections Wafer Process Flow Materials IC Fab Metalization CMP Dielectric deposition Test Wafers Thermal Processes Masks Implant PR strip Photolithography Design Etch PR strip Packaging Final Test Overview of Metalization • Surface wiring – Creating contact holes – Deposition of metals – Patterning of metals • Lead, metal lines, interconnects – alloying Applications: Interconnection Materials for Metalization • Conductor metals – Gold – Aluminum – Copper • Barrier metals – Titanium nitride (TiN); Titanium tungsten (TiW) • Refractory metals and metal silicides – TiSi2, WSi2, TaSi2, MoSi2 • Polysilicon • Insulators – PSG, BPSG, Low-k Copper Metallization SiN Ti/TiN M1 Cu CoSi2 FSG FSG PSG STI Ta or TaN Cu Cu W W n+ n+ USG P-Well p+ N-Well P-Epi P-Wafer p+ Overview of Multilevel Metallization Metal interconnect structure Metal stack interconnect Via interconnect structure with tungsten plug Interlayer Dielectric Local interconnect (tungsten) Initial metal contact Diffused active region in silicon substrate Sub quarter micron CMOS cross section Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Figure 12.1 © 2001 by Prentice Hall Copper Metallization Photograph courtesy of Integrated Circuit Engineering Photo 12.1 Metal Plugs in IC SiO2 Photograph courtesy of Integrated Circuit Engineering Photo 12.2 Contact/Interconnection Problems • Ohmic contact – Typical behavior between metal/metal • Schottky contact – Metal vs. semiconductor – May result in high contact resistance Junction Spiking Shallow junction Junction short Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Figure 12.5 © 2001 by Prentice Hall Diffused interconnections • Direct contact between metal & dielectric layers • Diffused line can be modeled as a distributed RC structure • Long diffused line results in large RC delay Polysilicon Interconnections • Connection between gate and diffused region • How to save sapce? • Buried contact – Save intervening space • Butted contact – Further save space but cause reliability problem Traditional vs. Damascene Metallization Traditional Interconnect Flow Dual Damascene Flow Cap ILD layer and CMP Cap ILD layer and CMP Nitride etch-stop layer (patterned and etched) Oxide Via-2 etch Second ILD layer deposition and etch through two oxide layers Tungsten deposition + CMP Copper fill Metal-2 deposition + etch Copper CMP Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Figure 12.2 © 2001 by Prentice Hall Copper • • • • Pre-deposition clean PVD barrier layer (Ta or TaN, or both) PVD copper seed layer Electrochemical plating bulk copper layer • Thermal anneal to improve conductivity Etch trenches and via holes FSG SiN FSG FSG Cu Cu Tantalum Barrier Layer and Copper Seed Layer Deposition Cu Ta SiN FSG FSG FSG Cu Cu Electrochemical Plating Copper Cu Ta FSG SiN FSG FSG Cu Cu CMP Copper and Tantalum, CVD Nitride SiN Ta FSG Cu SiN FSG Cu Cu LOCOS Process Pad Oxide Silicon nitride P-type substrate Pad oxidation, nitride deposition and patterning Silicon nitride SiO2 p+ P-type substrate p+ LOCOS oxidation p+ P-type substrate SiO2 p+ + p Isolation Doping Bird’s Beak + p Isolation Doping Nitride and pad oxide strip 71 Shallow Trench Isolation Photograph courtesy of Integrated Circuit Engineering Photo 11.5 Part IV. Polishing Schematic of Chemical Mechanical Planarization (CMP) Downforce Polishing pad Slurry dispenser Wafer carrier Wafer Polishing slurry Rotating platen Figure 18.8 CMP Oxide Mechanism Polishing pad (1) Slurry dispense (3) Mechanical force presses slurry into wafer Slurry CMP System Rotation By-products (5) By-product removal Si Si Si Si Si Si Si Si Si Si Si Si Si Drain Si - (2) H2O & OH travel to wafer surface Si Si Si Si(OH)4 (4) Surface reactions and mechanical abrasion Si Si Si Si Si SiO2 layer Figure 18.10 Si Si Si Si Si Chemical Mechanical Polishing Slurry Dispenser Pressure Membrane Wafer Holder Wafer Retaining Ring Slurry Polishing Pad Platen Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 76 CMP Polishing Pad Photo courtesy of Speedfam-IPEC Photo 18.2 Fumed Silica Particles Courtesy of Fujimi Corporation Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 78 Multilayer Metallization with Nonplanarized and Planarized Surfaces Planarized IC product Non-planarized IC product Micrographs courtesy of Integrated Circuit Engineering Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Photo 18.1 © 2001 by Prentice Hall CMP Simulation Module GUI 相對速度 Pad: 130rpm, Wafer: 90rpm Geometric setting MRR models & Process recipe setting visualization types Pad: 135rpm, Wafer: 90rpm [Tyan, 2007] 80 鑽石修整器初始位置與路徑 鑽石修整器初始位置 yp yp qi 180o qi 90o Dresser Op Op xp xp Dresser qi=90o Pad qi=180o Pad 鑽石修整器擺動路徑 Route1: 0~40o Route2: -40o~+40o yp yp Route1 ws ws Conditioner Arm Op Route2 Op xp xp Co nd itio ne wp rm rA wp Pad Pad 81 Grooved Pad Dressing Dressing Parameters wR=0.572 qi=90o route1: 0o~+40o t*= 70 t* = 10 t* = 70 Pad Configuration Grooved Pad Parameters Grooved pitch =12 mm Grooved depth = 0.2 mm Grooved width = 2 mm Recover Area 82 RAR=27.49% RAR=92.4% Part V. Testing and Packaging 83 Scribe Line Monitor Test Scribe line with monitor Structure test structures Figure 19.3 System Blocks for Automated Parametric Tester System Instrumentation Electronic interface Computer Probe card Wafer positioning (X, Y, Z, q) q-Z stage X-Y stage Figure 19.6 Traditional Assembly and Packaging Wafer Test and Sort Wire Bond Die Separation Plastic Package Figure 20.1 Die Attach Final Package and Test Typical IC Packages Dual in-line package (DIP) Quad flat pack (QFP) Single in-line package (SIP) Plastic leaded chip carrier (PLCC) Figure 20.2 Thin small outline packag (TSOP) Leadless chip carrier (LCC) Tool Thermosonic Ball Bond moves up Gold wire Capillary tool H2 torch Die Ball (1) (2) Pressure and and more wire is fed. ultrasonic energy Bonding ball on pad Die (3) (4) Pressure and heat form bond. Lead frame Tool moves upward. Wire breaks at the bond. (6) (5) Figure 20.12 Flip Chip Area Array Solder Bumps Versus Wirebond Flip chip bump area array Bonding pad perimeter array Figure 20.23 Chip with Ball Grid Array Photo 20.3 Part VI. Mechanics Issues Dislocations (a) model for an edge dislocation, (b) edge dislocation, (c)screw dislocation Illustration of Thermal Budget Gate As S/D Implantation Over Thermal Budget Lattice Damage With One Ion Light Ion Damaged Region Heavy Ion Single Crystal Silicon Micro Structures • Column-liked structure • Porous structure Stoney Formula • Simple 1-D thermal stress ( f s )(T1 T2 ) E f /(1 f ) • Stoney formula for thin film material – by curvature measurement to find residual 3 stress Es h s f 6(1 s )Rh f2 (1 hs /h f ) Residual Stress Measurement CVD Reactors
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