1. No category

Microelectronics Journal 46 (2015) 422–430
Contents lists available at ScienceDirect
Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo
A zero charge-pump mismatch current tracking loop for reference spur
reduction in PLLs
R.R. Manikandan n, Bharadwaj Amrutur
Electrical Communication Engineering Department, Indian Institute of Science, Bangalore 560012, India
art ic l e i nf o
a b s t r a c t
Article history:
Received 12 March 2014
Received in revised form
25 November 2014
Accepted 10 March 2015
The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in
the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This
paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body
bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur
suppression. A chip prototype of the proposed circuit was implemented in 0:13 μm CMOS technology.
The frequency synthesizer consumes 8.2 mA current from a 1.3 V supply voltage and achieves a phase
noise of 96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements
using the proposed calibration technique exhibited a mismatch current of less than 0.3 μA (0.55%) over
the VCO control voltage range of 0.3–1.0 V. The closed loop measurements show a minimized static
phase error of within 7 70 ps and a C9 dB reduction in reference spur level across the PLL output
frequency range 2.4–2.5 GHz. The presented CP calibration technique compensates for the DC current
mismatch and the mismatch due to channel length modulation effect and therefore improves the
performance of CP-PLLs in nano-meter CMOS implementations.
& 2015 Elsevier Ltd. All rights reserved.
Keywords:
Phase-locked loop (PLL)
Charge-pump
Current mismatch
Reference spur
Deterministic jitter
Static phase offset
1. Introduction
P spur ðdBcÞ ¼ 20 log
Charge-pump phase locked loops (CP-PLLs) are widely used for
frequency synthesis, up conversion and down conversion of baseband signals in RF transceivers, and clock generation in digital
systems [1]. Fig. 1 shows the block level description of a conventional CP-PLL. Implementation of CP-PLLs with high spectral purity
and wide frequency tuning range in nano-scaled CMOS process is
quite challenging [2–4]. Severely deteriorated channel length
modulation effect of nano-scaled CMOS process affects the matching between the charge-pump currents (I up and I dn ) and hence
degrades the performance of PLL by introducing a static phase
error between the phase frequency detector (PFD) input signals
and reference spurs in the frequency spectrum of its output signal
[5,6] as shown in Fig. 1.
The static phase error (Te) and the reference spur level (Pspur)
(using narrow-band frequency modulation approximation) due to
CP mismatch current can be expressed as [7,8]
T e ¼ T pfd n
Δi
I cp
Corresponding author. Tel.: þ 91 9535144501.
E-mail address: [email protected] (R.R. Manikandan).
http://dx.doi.org/10.1016/j.mejo.2015.03.004
0026-2692/& 2015 Elsevier Ltd. All rights reserved.
ð1Þ
!
f ref
I cp Rz K vco T pfd ΔI
pffiffiffi
20 log
I cp
f pl
2
ð2Þ
where Tpfd is the PFD reset delay, Δi is the CP mismatch current, Icp
is the CP output current, Rz is the resistor value in the loop filter,
Kvco is the VCO gain, fref is the reference frequency and fpl is the
frequency of pole in the loop filter given by ðC z þ C p Þ=2π Rz C z C p .
VCO architectures with low gain (Kvco) and wide frequency
tuning range using switched capacitor banks [9] and dual path
control techniques [10–13] are presented in the literature to
minimize reference spurs. These techniques either require complex digital frequency calibration schemes [9] or suffer due to
coarse-path leakage current and charge injection issues [11].
Randomization techniques in the charge distribution mechanism
to the loop filter are proposed in [14–17] to minimize the
magnitude of reference spurs. However, the performance of these
techniques are limited due to the open loop generation of equal
delays and increased in-band phase noise performance.
Fig. 2 shows the simulated reference spur and static phase error
characteristics versus the CP mismatch current. A zero PFD reset
delay (Tpfd) will eliminate the reference spurs and static phase
error issues in the charge-pump-PLL. However, an appropriately
designed smaller Tpfd is necessary for a dead-zone free PFD
operation [8] and therefore the CP mismatch current should be
minimized for an ideal PLL operation.
R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
Several CP mismatch current calibration schemes are presented
in the literature to minimize the pump current mismatch [18–26].
A replica CP based mismatch current calibration scheme was
presented in [18]. However, Ref. [18] calibrates the CPs under
different control voltages and hence difficult to compensate for the
mismatch due to channel length modulation effect. A digital
mismatch current calibration approach was presented in
[5,18,19]. However, the CP circuit implementations in these
reported works consume a larger current of 3nIcp, which is not
suitable for high output current (Icp) applications. Charge-pump
architectures with negative feedback using high gain OPAMPs to
minimize the mismatch current are presented in [22–26], but the
non-ideal effects of OPAMPs such as stability and offset voltage
limit the performance of CP.
Bulk-driven circuit techniques are highly useful in the design of
ultra low voltage analog circuits [27–30] and to compensate for
variation effects (PVT, die-to-die and within-die), and to reduce
the leakage power in digital circuits [31,32]. In this paper, we
present a charge-pump mismatch current calibration technique
utilizing an adaptive body bias tuning of its current source
transistors which provide a very fine resolution in the mismatch
current calibration and a zero CP mismatch current tracking PLL
architecture to minimize the static phase error and reference
spurs. The proposed technique compensates for the DC current
mismatch and the mismatch current due to channel length
423
modulation effect and hence improves the performance of CPPLLs in the nano-scaled CMOS process implementations.
This paper is organized as follows. Section 2 describes the
proposed CP mismatch current calibration scheme. The zero CP
mismatch current tracking loop operation and its measured results
are presented in Sections 3 and 4, respectively. Finally, the
conclusions are given in Section 5.
2. Charge-pump mismatch current calibration technique
The current steering charge-pump circuit used in the PLL is
shown in Fig. 3a. M7 and M3 are the up and down current source
transistors in the charge-pump, respectively, and their saturation
currents can be expressed as
1
W
I up ¼ μp C ox;p
ðV gs;p V T;p Þ2 ð1 þ λV ds;p Þ
ð3Þ
2
L p
1
W
I dn ¼ μn C ox;n
ðV gs;n V T;n Þ2 ð1 þ λV ds;n Þ
2
L n
ð4Þ
Fig. 4 shows the measured output current characteristics of the
CP. As the CP output voltage (Vctrl or VCO control voltage)
increases, V ds;n increases and V ds;p decreases, and hence Idn (NMOS
current) increases and Iup (PMOS current) decreases due to the
channel length modulation effect. Therefore, the CP currents Iup
and Idn are matched only for a single voltage point (zero mismatch
current point) and the mismatch current (I up I dn ¼ ΔI a 0) exists
for all other control voltages. This mismatch between chargepump currents creates ripple on VCO control voltage as shown
in Fig. 3b.
2.1. Proposed CP mismatch current calibration technique
The threshold voltage of a PMOS transistor (M7 in Fig. 3a) is
given by
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffi
V T;p ¼ V T0;p þ γ ð ϕ þ V bs;p ϕÞ
ð5Þ
Fig. 1. Conventional Type II, 3rd order integer-N charge-pump PLL.
In a conventional CP case, the body terminal of PMOS transistor
is connected to the supply voltage (V b ¼ V s ¼ V dd ) and its threshold voltage is equal to V T0;p . Forward body biasing of PMOS
transistor (M7) with V b o V dd reduces its threshold voltage
(V T;p oV T0;p ) and increases the magnitude of UP current (Iup) as
shown in Fig. 5.
Fig. 2. Simulation conditions: Icp ¼ 100 μA, Kvco ¼ 300 MHz/V, Rz ¼ 28:18 KΩ, Cz ¼84.58 pF, Cp ¼ 6.51 pF, and fref ¼5 MHz.
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R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
CP
LPF
Fig. 3. Current steering charge-pump circuit and its transient wave-forms for I up o I dn .
Fig. 4. Measured charge-pump output current characteristics.
Fig. 5. Simulated I D ; V T dependence on body voltage (Vb) of PMOS transistor (W
¼ 30 μm, L ¼ 3 μm).
Fig. 6a shows the measured output current characteristics of
the charge-pump circuit (Fig. 3a). In this design, the CP currents Iup
and Idn are matched for a lower VCO control voltage to emulate the
I up oI dn mismatch current scenario, when V b ¼ V s ¼ V dd . Forward
body biasing of UP current source transistor increases the PMOS
current (Iup) and shifts the zero mismatch current point to a higher
VCO control voltage as shown in Fig. 6a. Therefore, by adaptively
adjusting the body bias voltage of PMOS current source transistor
with respect to VCO control voltage, the zero mismatch current
point can be shifted to all VCO control voltages as demonstrated
in Fig. 6a. Thus minimizing the mismatch between CP currents Iup
and Idn generated due to the channel length modulation effect.
Fig. 6b shows the CP mismatch current characteristics
(ΔI ¼ I dn I up ) measured across the VCO control voltage range 0.3–
1 V. Measurements show a CP mismatch current of less than 0.3 μA
(0.55%) and 9.44 μA (17.2%), with the body bias tuning enabled and
Fig. 6. Measured CP currents with the PMOS transistor body voltage varied
between 1.3 V and 1.2 V (4 bit control, I up o I dn ).
disabled, respectively. The obtained matching performance between
the CP currents with a mismatch of less than 0.55% using body bias
tuning is comparable to those reported in [23–26] and the presented
technique is extremely useful in reducing the channel length
modulation effects on PLL performance.
3. Zero charge-pump mismatch current tracking PLL
architecture
The PLL architecture with the CP mismatch current reduction
loop is shown in Fig. 7. For an automatic charge-pump mismatch
current calibration with respect to VCO control voltage, we used an
auxiliary loop based calibration method [12,18,19]. The mismatch
current reduction loop monitors the polarity of static phase error
R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
425
Fig. 7. Zero charge-pump mismatch current tracking PLL architecture.
Fig. 8. Simulated step response of VCO control voltage (2.4–2.5 GHz).
Fig. 9. Charge-pump output current characteristics: SAR algorithm.
between the reference and feedback signals and calibrates the CP
mismatch current by adjusting the body bias voltage of UP current
source transistor.
The mismatch current reduction loop consists of a phase error
monitor, lock detector, 4-bit successive approximation register
(SAR) controlled logic and a digital to analog converter (DAC):
The lock detector enables the mismatch current reduction loop
and is implemented using standard digital logic circuits [10–17].
Fig. 10. VCO control voltage in the zero CP mismatch current tracking mode.
Fig. 11. SAR controller operation: PMOS bulk voltage and CP mismatch current.
The phase error monitor outputs the lead/lag status of the
reference signal over the feedback signal and is implemented
using conventional D-type flip-flop based symmetric bang–
bang phase detector [33].
The SAR controller is implemented using conventional digital
logic circuits [34] and the DAC uses a charge-sharing capacitive
DAC architecture [35]. The SAR controller along with the DAC
performs body bias tuning based on the lead/lag status output
of the phase detector.
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R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
Fig. 12. Simulation conditions: Icp ¼ 100 μA, Kvco ¼ 300 MHz/V, Rz ¼ 28.18 kΩ, Cz ¼ 84.58 pF, Cp ¼6.51 pF, fref ¼ 5 MHz, and Tpfd ¼5 ns.
The PLL operates in three modes: 1. initial coarse locking mode,
2. zero CP mismatch current tracking mode, and 3. steady state
mode. The step response of VCO control voltage explaining the
different modes of operation of PLL is shown in Fig. 8. In this
design, the charge pump currents are matched for a lower VCO
control voltage (point C in Fig. 9) and for higher voltages Iup is
lesser than Idn.
Coarse locking mode: In this mode, the PLL operates in its
conventional closed loop architecture and tries to acquire lock to
an output frequency set by the reference signal (Fref) and divider
value (in the case of Fig. 8, Fout ¼2.5 GHz and Fref ¼1 MHz). The lock
detector output is low with the SAR controller digital bits set to
high (1111) and the DAC output controlling the PMOS current
source transistor's body voltage is held at VDD (1.3 V).
For a VCO control voltage of 0.912 V (Fout ¼ 2.5 GHz), the
charge-pump currents are Iup ¼52.44 μA and Idn ¼56.12 μA (points
A and B in Fig. 9, respectively). This mismatch between the CP
currents creates ripple on VCO control voltage and frequency
modulates the VCO output signal.
Zero CP mismatch current tracking mode: The lock detector
enables the mismatch current reduction loop on the detection of
phase lock between the reference and feedback signals. Initially,
the reference signal leads the feedback signal (I up o I dn , Vb ¼ 1.3 V)
and the phase error is positive. A calibration clock generated by
dividing down the reference signal is used to trigger the 4 bit-SAR
controller. The charge-pump current characteristics demonstrating
the SAR controller operation in minimizing the mismatch between
Iup and Idn are shown in Fig. 9 and are explained as follows:
Transition 1: On the 1st rising edge of the calibration clock, SAR
controller calibrates its MSB (“1111” to “0111”) and forward body
biases the UP current source transistor (Vb ¼1.25 V in Fig. 11) to
increase the magnitude of its output current, shifting the zero
mismatch current point to a higher VCO control voltage.
Transition 2: On the 2nd clock rising edge, the charge-pump
current Iup is lesser than Idn, phase error is positive and the SAR
controller adjusts its output bits from “0111” to “0011” to further
increase the magnitude of Iup (Vb ¼1.225 V).
Transition 3: On the 3rd rising transition of calibration clock,
I up 4 I dn with the phase error negative and the SAR controller
reduces the magnitude of forward body biasing of PMOS transistor
and the magnitude of UP current (“0011” to “0101” and
Vb ¼ 1.2375 V).
Transition 4: On the 4th clock rising edge, I up oI dn and the
phase error is positive. The SAR controller calibrates its LSB (”0101”
to ”0100” and Vb ¼1.23125 V) increasing the magnitude of UP
current.
At the end of nth calibration cycle of a n-bit SAR controller, the
current points A, B and C in Fig. 9 almost coincide with each other
minimizing the charge-pump mismatch current and the magnitude of ripple on the VCO control voltage. This is a simple first
order loop operation and auxiliary loop added forms an unconditionally stable system. Figs. 10 and 11 show the effect of SAR
R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
427
Fig. 14. Measured VCO transfer characteristics (VCO þ EC output, PVT calibration
bits, B5 to B0).
Fig. 13. Die photograph of the fabricated test chip in 0.13 μm CMOS process and
the experimental setup used to demonstrate the proposed concept.
controller operation on the VCO control voltage and PMOS
transistor body voltage (Vb), respectively, during the zero chargepump mismatch current tracking mode.
Steady state mode: After n cycles of mismatch current calibration (for a n-bit SAR controller, in this design n ¼ 4), PLL operates
in its steady state mode with the SAR controller and DAC holding
the optimized body voltage for a minimum CP mismatch current
condition. The magnitude of CP mismatch current and pk–pk
ripple on VCO control voltage in this mode are 0.013 μA and
0.6 mV, and 3.68 μA and 5.9 mV with the mismatch current
reduction loop enabled and disabled, respectively, as shown
in Figs. 10 and 11.
Fig. 12 shows the static phase error and reference spur levels
simulated across the PLL output frequency range 2.4–2.5 GHz, for a Tpfd
of 5 ns. In this simulation, the PFD reset delay is assumed larger than
the optimum value to emulate the experimental conditions used in
the implementation (described in Section 4). The static phase error
and reference spur levels observed at 2.5 GHz output frequency are
423 ps and 66.46 dBc, and 9.3 ps and 86.8 dBc, respectively, with
the mismatch current reduction loop disabled and enabled, respectively, thus demonstrating the efficiency of proposed technique in
improving the reference spur and static phase error performance of
PLL. The results can be further improved by having an optimum reset
delay in the phase frequency detector design.
The overall settling time of the synthesizer is less than 120 μs for
a 100 MHz frequency step (2.4–2.5 GHz shown in Fig. 8) and it can be
improved by increasing the frequency at which the mismatch current
reduction loop operates or by increasing the loop bandwidth of PLL.
The DAC and other digital circuits in the mismatch current reduction
loop operate at a lower frequency of f ref =16 and the performance of
DAC is also relaxed in terms of speed, noise, and matching. Therefore,
the additional power consumption from the mismatch current
reduction loop is negligible.
In the steady state mode of frequency synthesizer, the capacitive DAC holds the optimum body voltage for the minimum CP
mismatch current condition and therefore its decay voltage must
Fig. 15. Measured phase noise characteristics of 2.4 GHz signal.
be kept within its LSB step. Simulations show a worst case DAC
decay of 1.32 mV over a 50 ms time duration (FF, 100 1C) which is
much lesser than the unit step voltage used in this implementation. In frequency hopping wireless communication applications
where the frequency is reset more often, this is not an issue and
for other applications, DAC architectures immune to leakage such
as R-2R DAC can be used [36].
4. Experimental setup and measurements
A chip prototype containing an integer-N charge-pump PLL
with the CP mismatch current reduction loop was fabricated in a
UMC 0.13 μm Mixed-Mode and RF CMOS 1.2 V/3.3 V 1P8M
process. The buffer A shown in Fig. 7 was not integrated onchip and as a result, the bulk leakage current disrupted the
normal operation of capacitive DAC. Consequently, we implemented the CP mismatch current reduction loop (enclosed by
dashed lines in Fig. 7) off-chip to demonstrate the proposed
concept. Fig. 13 shows the die photograph of the PLL chip and the
test setup used in the experiment.
4.1. Frequency synthesizer
The type-II, 3rd order integer-N charge-pump PLL used in the
experiment is shown in Fig. 7. The PLL does frequency synthesis at a
lower operating frequency of 800 MHz to reduce the power consumption from its VCO and divider circuits [37–40]. A digital logic
gate based edge combiner generates the 2.4 GHz RF carrier by
combining the output signals from different stages of a ring oscillator
VCO used in the PLL [41]. The reference signal frequency was chosen
as 1.667 MHz, so that the channel spacing in the up-converted
2.4 GHz frequency band is 5 MHz (for Zig-bee applications).
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R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
Fig. 16. Measured reference and feedback signals with the PLL operating in its steady state mode.
Fig. 17. Measured static phase error and reference spur with the CP mismatch current reduction loop disabled and enabled (Fout ¼ 2.4 GHz, Fref ¼ 1.667 MHz).
The phase frequency detector (PFD) and divider are implemented
using standard digital logic circuits with tri-state dead zone free
phase detector and down counter architectures, respectively. The
current steering charge-pump circuit with adaptive body bias tuning
(Fig. 3a) was designed to source or sink programmable currents in
the range of 3–100 μA from a reference current source of 10 μA. The
loop filter parameters are Rz ¼ 60 kΩ; C z ¼ 200 pF; C p ¼ 15:2 pF
designed for a PLL loop bandwidth of 100 kHz and phase margin
601. The loop filter capacitors are implemented using the gate
capacitance of NMOS transistors to reduce the area occupied by
large capacitors on-chip.
A pseudo-differential voltage controlled ring oscillator (VCO)
with varactor and bias current tuning is used in the PLL. The
VCO and edge combiner covers an operating frequency range of
R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
429
Fig. 18. Measurements across PLL operating frequency range 2.4–2.5 GHz.
Table 1
Performance summary and comparison.
Process, (μm)
Supply voltage (V)
Output frequency (GHz)
Reference frequency (MHz)
Loop Bandwidth (KHz)
Power consumption (mW)
Phase noise
(dBc/Hz)
Reference spur (dBc)
Static phase error (ps)
Area (mm2)
[19]
[11]
[21]
[29]
[14]
This worka
0.18
1.8
5.2
10
200
19.8
110
@ 1 MHz
68.5
–
0.64
0.25
2.5
4.5
4
90
117.5
87
@ 1 MHz
45
–
–
0.09
1
0.8
100
–
15
112
@ 0.2 MHz
48
o 7 40
0.048
0.065
0.4
0.35
21.875
–
0.109
90
@ 1 MHz
55.3
–
0.0081
0.18
1.8
2.4
1
–
18
110
@ 1 MHz
55
–
0.9
0.13
1.3
2.4
1.667
100
10.7
96.01
@ 1 MHz
b
31.47
c
o 7 70
0.31
a
Mismatch current reduction loop implemented off-chip.
The reference spurs are large due to undesired parasitic coupling through substrate and supply in this implementation A C9 dB reduction in spur level was
demonstrated with the CP mismatch current calibration.
c
Limited due to the use of large PFD reset delay.
b
2.35–2.55 GHz and the measured VCO transfer characteristics for
different PVT calibration settings (B5 to B0) are shown in Fig. 14.
The frequency synthesizer achieves a phase noise of 96.01 dBc/
Hz at 1 MHz offset from a 2.4 GHz RF carrier consuming 8.2 mA
current from a 1.3 V supply voltage. Fig. 15 shows the measured
phase noise characteristics of the 2.4 GHz signal generated by the
frequency synthesizer. The measured phase noise performance is
comparable to the other ring oscillator based frequency synthesizer implementations reported in [39,42] and can be improved by
burning additional power in the ring oscillator.
4.2. Zero charge-pump mismatch current tracking loop
The designed frequency synthesizer chip has test points that
bring out the PFD input signals (Fref and Ffb) and the CP PMOS
transistor body terminal to the chip package pins and the zero CP
mismatch current tracking loop are implemented off-chip to demonstrate the working of proposed concept. The digital circuits in the
mismatch current reduction loop are implemented in the FPGA using
conventional circuit techniques and the DAC is implemented from a
digitally controlled variable resistor chip AD8304. Fig. 13c shows the
experimental setup used in the demonstration.
The non-ideal effects such as undesired coupling through
substrate, supply voltage, and other parasitic interactions also
contributed to the reference spurs [7,19,43,44]. Therefore, we
have used a larger PFD reset delay in the implementation to
sense smaller CP mismatch currents through static phase error
measured off-chip and to observe the effects of CP mismatch
current on the reference spur performance of PLL over the other
non-ideal effects.
The measured charge-pump current characteristics and the
effect of body biasing in minimizing the CP mismatch current are
shown in Fig. 6. The measured transient response of reference and
feedback signals with the PLL operating in its steady state mode
are shown in Fig. 16:
In this implementation, the CP mismatch current and the PLL
output frequency increase with the VCO control voltage
(Figs. 6b and 14). Hence the static phase error between the
reference and feedback signals also increases with the PLL
output frequency as shown in Fig. 16a.
Forward body biasing of PMOS transistor reduces the CP
mismatch current and hence the static phase error also reduces
as demonstrated in Fig. 16b. At the zero mismatch current point
where I up ¼ I dn , the static phase error reaches C0 ps. Beyond
this body voltage, Iup becomes greater than Idn with the
reference signal lagging behind the feedback signal as shown
in Fig. 16b.
Fig. 17a shows the measured static phase error between the PFD
input signals (Fout ¼2.4 GHz) with the mismatch current reduction
loop disabled (2.215 ns) and enabled (41.09 ps). The corresponding
measured PLL output frequency spectrum (2.4 GHz) with the reference spur levels 22.42 dBc (loop disabled) and 31.47 dBc (loop
enabled) is shown in Fig. 17b. The measured spur levels are large due
to the undesired parasitic coupling from reference and feedback
signal buffers to the sensitive nodes of PLL through substrate, supply
and other non-ideal effects. Similar undesired parasitical effects
resulting in large spurious tones are also been reported in the
literature [43,45]. The static phase error and reference spur levels
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R.R. Manikandan, B. Amrutur / Microelectronics Journal 46 (2015) 422–430
measured across the synthesizer output frequency range 2.4–2.5 GHz
are shown in Fig. 18a and b, respectively. Table 1 presents the
summary of measured performance from the frequency synthesizer
and its comparison with other designs.
5. Conclusion
A charge-pump mismatch current reduction technique using
an adaptive body bias tuning of PMOS transistors in the CP was
demonstrated. The proposed technique compensates for the DC
current mismatch and the mismatch due to channel length
modulation effect and hence improves the static phase error and
reference spur performance of CP-PLLs in the nano-meter CMOS
implementations.
Chip prototype of a 2.4 GHz, integer-N charge-pump PLL was
fabricated in 0.13 μm CMOS process. Measurements show a CP
mismatch current of less than 0.3 μA (0.55%) and 9.44 μA (17.2%)
with and without body bias tuning, respectively, in the VCO
control voltage range 0.3–1 V. A zero CP mismatch current tracking loop was implemented off-chip for an automatic mismatch
current calibration with respect to VCO control voltage and to
improve the PLL performance. The closed loop measurements
show a C 9 dB improvement in the reference spur performance
and a static phase error of within 770 ps across the PLL output
frequency range (2.4–2.5 GHz).
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