1. technology and computing

Illinois Institute of Technology
Lecture 22
Memory; Sequential Logic Circuits
CS 350: Computer Organization & Assembler Language Programming
[Solved]
A. Why?
• Memory lets us access and update state values.
• Sequential logic circuits combine combinatorial circuits, memory, and a clock
to perform calculations that take inputs, use and update the state, and
produce outputs.
B. Outcomes
After this lecture, you should
• Know how memory combines address decoders and data storage/update.
• What sequential logic circuits, clocks, and flip-flops do and why we have them.
C. Registers Hold Bitstrings
• An n-bit wide register is a circuit that can store an n-bit bitstring.
• We can build an n-bit register by
combining n D-latches. (Shown to the
right is a 2-bit register.)
WE
• The register has n input data bits D[0 : n–1] and n output data bits Q[0 : n–1]
• The register also has one “control” bit,
Write Enable (WE), shared by all the
latches. If WE = 1, then the latches
update their states (and outputs). If
WE = 0, then the latches ignore their D
D₁
D₀
D-Latch
D-Latch
Q₁
Q₀
inputs and continue to output the same Q values.
D. Memory Bank
• We can combine multiple registers to produce a memory bank. We give each
register an unsigned bitstring address (i.e., a name) to identify it.
CS 350: Comp Org & Asm Pgm’g
–1 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
• Definition: The address size or address width is the number of bits in an
address. The address space is the set of legal addresses; it has size ≤ 2 k where
k is the address width. “k-bit addresses” means “has address width k”.
• Address size corresponds to the number of digits in a street address for
the U.S. Mail. (“10 West 31st Street” requires ≥ 2 decimal digits of
address size.)
• Definition: The addressability of a memory bank is the amount of data stored
at each address. If we have m-bit addressability and k-bit addresses, then the
memory bank contains ≤ m × 2 k bits.
• Addressability corresponds to the amount of data you can put in the
mailbox for a given street address.
• Computers generally have one of two kinds of addressability.
• Byte-addressability means it has 8-bit addressability.
• Word-addressability means its addressability equals its word size (the
amount of memory it takes to store an integer, typically).
• Note 1: For memory banks in general, the address size and addressability are
unrelated: You could have a very large set of small mailboxes (i.e., k is large
and m is small) or a small set of very large mailboxes (small k, large m).
• Examples: A calculator with one memory location has k = 0 and m = some
number of decimal digits. An array of 1024 bits has k = 10 and m = 1.
• Note 2: For computer memories with word addressability, we often have k ≤ m,
which means you can store an entire memory address at a memory address.
• The LC-3 computer has 16-bit addresses and 16-bit addressability.
• The SDC computer has 4-decimal digit addresses and 2-decimal digit
addressability.
• Alignment: If a memory bank is byte-addressable, the addresses of words are
often restricted to be multiples of the addressability. E.g., if a word is 4 bytes
wide, then the "aligned" word addresses are 0, 4, 8, 12, etc. (Such addresses are
word-aligned.) Trying to access an unaligned word can cause an error or a
slowdown in execution (depends on the hardware design).
CS 350: Comp Org & Asm Pgm’g
–2 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
E. Reading a Memory Bank
• With the goal of understanding how a read/write memory bank works, let’s
start by looking at reading from a memory with k-bit addresses and 1-bit
addressability.
• The k-bit memory address feeds into a decoder with 2k one-bit outputs. The
output specified by the value of the address will be 1; the others will be 0.
Select
Memory
address
k
/
Out
1-bit Reg
k-bit
Decoder
...
1-bit Reg
...
1-bit Reg
...
OR
Output
• A 1-bit register is a D-latch whose output is ANDed with a Select line: If the
select line is 1, the register outputs its stored value, otherwise it outputs 0.
For the select line, we use the decoder output line for this address.
Select
D-latch
AND
Out
Reading a 1-bit Register
CS 350: Comp Org & Asm Pgm’g
–3 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
• The outputs of the 2k registers get ORed together to form the output of our
memory bank: The output matches the value of the register selected by the
address.
• To store multiple bits of data at each address, we use a register for each bit.
(We only need one decoder, however.) The diagram below supports 2 bits of
data per address. The dashed rectangles indicate the circuitry being repeated
for each “column” of output. Note the registers for each address share the
same select line.
Memory
address
k
/
Out
1-bit Reg
k-bit
Decoder
...
Select
1-bit Reg
1-bit Reg
...
...
1-bit Reg
...
1-bit Reg
...
OR
Output₁
Out
1-bit Reg
OR
Output₀
F. Writing To Memory
• With read-write memory, the 1-bit registers gain two inputs: a write enable
line and an input data line. The latch state is set to the input if the write
enable line is on, otherwise the input is ignored.
• As before, the output of the latch is only sent out if the select line is on,
otherwise a 0 is output.
CS 350: Comp Org & Asm Pgm’g
–4 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
Select
D
D-latch
AND
WE
Out
A 1-bit Read/Write Register
• If we concentrate on all the bits stored at one address, we only write data to
these bits if this address is the one selected and the memory bank is supposed
to write its input data into the bank.
Bank
WE
In₁
In₀
AND
Select
D
WE
1-bit
R/W
Register
Out₁
D
WE
1-bit
R/W
Register
Out₀
The 2 bits At an Address
CS 350: Comp Org & Asm Pgm’g
–5 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
• For a fuller example, the textbook's Figure 3.21 shows a memory bank with 2bit address size and 3-bit addressability.
CS 350: Comp Org & Asm Pgm’g
–6 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
G. Sequential Logic Circuits
• A Sequential Logic Circuit combines combinatorial circuits and storage
elements. The combinatorial circuit calculations take input values and
memory values and produce output values and updated memory values.
• It turns out that we also need a way to control when the calculations occur
relative to when memory gets updated. Consider the following block diagram
for a sequential logic circuit; ignore the clock for now. There are two storage
elements, with inputs D[0:1] and outputs S [0:1].
Output
Input
Combinatorial Logic Circuit
D[0:1]
S[0:1]
Storage Elements
Clock
• If we update D₀, this will change S₀ ← D₀. But changing S₀ can change what
the combinatorial circuit produces as D₁; if this change occurs before we set
S₁ ← D₁, then we may set S₁ to the wrong value.
• As a concrete example, say we have input X and we calculate D₁ = S̅ ₁̅ S ₀ and
D₀ = S ₁ + X S ₀. If X = 0 and S = 10 (i.e., S₁ = 1 and S₀ = 0), then D = 01. If
we update S₁ ← 0 before updating S₀ ← 1, then we’ll change S from 10 to S = 00, which will change D₀ = 1 to D₀ = 0.
H. Clocks and Flip-Flops
• To the solve the problem caused by allowing calculations and memory updates
to intermingle, we need to synchronize them. To do this, we’ll use a Clock, a
device that cycles its output (the Clock Signal) from 0 to 1 and back, at a
regular speed.
• During one half of the cycle, we’ll simultaneously read memory, get the input
values, and do calculations, but we won’t allow memory to be updated.
Memory updates are only allowed during the other half cycle, and while
memory is being updated, we’ll ignore the inputs and calculation results.
CS 350: Comp Org & Asm Pgm’g
–7 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
Do computation
Change state
1 Voltage = 0 One Clock cycle
• To store a memory bit, we can use a Master-Slave Flip-Flop. It uses the clock
signal to alternate between two modes. In the first mode, it reads and stores
one bit of input without changing its output. In the second mode, it changes
its output to match its internal state while ignoring its input.
• A master-slave flip-flop has two D-latches and a clock connection. The righthand D-latch output is the left-hand D-latch input.
• When the clock signal is 0
• The combinatorial circuit does its calculation based on the value in the
left-hand latch and sends its output to the right-hand latch
• The right-hand latch sets its state to the value of the combinatorial
circuit.
• The left-hand latch sends its value as the flip-flop output but ignores the
value of the right-hand latch (as it possibly changes).
• When the clock signal is 1
• The left-hand latch reads the value in the right-hand latch.
• The right-hand latch ignores the value being produced by the
combinatorial circuit.
• The combinatorial circuit does its calculation based on the changing value
of the left-hand latch.
CS 350: Comp Org & Asm Pgm’g
–8 –
© James Sasaki, 2015
Illinois Institute of Technology
Lecture 22
• For an m-bit register, we have m flip-flops all connected to the same clock.
Either m bits of data are being read into the register (without changing
the register’s output). Or, m bits of data are being output from the
register (while ignoring the data entering the register).
• In the textbook’s Figure 3.43, we have two flip-flops connected to the
clock, so D ₀ and D₁ get calculated, then S ₀ and S ₁ get set, then D₀ and
D₁ get calculated, and so on.
CS 350: Comp Org & Asm Pgm’g
–9 –
© James Sasaki, 2015
Illinois Institute of Technology
Activity 22
Memory; Sequential Logic Circuits
CS 350: Computer Organization & Assembler Language Programming
A. Why?
• Memory lets us access and update state values.
• Sequential logic circuits combine combinatorial circuits, memory, and a clock
to perform calculations that take inputs, use and update the state, and
produce outputs.
B. Outcomes
After this activity, you should be able to:
• Show how memory combines address decoders, multiplexers, and data storage/
update.
C. Questions
1.
In a memory bank, what kind of circuit is used to map a memory address to
the enable line for that memory address?
2.
In a memory bank, how are enable lines shared? Write enable lines?
3.
What is the difference between byte addressability and word addressability?
4.
What is the relationship between address size and addressability for computer
memory banks? For memory banks in general?
5.
Say we have a machine with k-bit addresses and m-byte addressability. (a)
What is the address space and how large is it? (b) How many bytes of memory
can we have in total? (c) What, if any, is the relationship between k and m ?
6.
Say a byte-addressable machine has 32-bit memory addresses. How many
gigabytes of memory can we access? What if memory addresses are 64-bits?
Hint: The standard prefixes are kilo-, mega-, giga-, tera-, peta-, exa-, zetta-,
and yotta-.
7.
How are combinatorial and sequential logic circuits different? Which uses
state information?
CS 350: Comp Org & Asm Pgm’g
– 10 –
© James Sasaki, 2015
Illinois Institute of Technology
Activity 22
8.
Why do sequential logic circuits synchronize calculations and memory
updates? How are clocks used to do synchronization? How fast can the clock
be relative to the calculation part of a sequential logic circuit?
9.
What comprises a master-slave flip-flop and how does it work?
CS 350: Comp Org & Asm Pgm’g
– 11 –
© James Sasaki, 2015
Illinois Institute of Technology
Activity 22
Solution
1.
A decoder takes the k bits of address and turns on the corresponding output
wire. (There are 2k output wires.)
2.
All the 1-bit registers at the same address share the enable line for that
address. The write enable line to the memory bank splits into write enable
lines for each address, shared again by the 1-bit registers at that address.
3.
Byte- and word-addressability differ in how much data is stored at an
address (8 bits versus a word length).
4.
For computers with word addressability, the addressability is typically ≥ the
address size. For memory banks in general, addressability and address size
are unrelated.
5.
The address space is the set of legal addresses. Ours has size 2k. The total
amount of memory is m 2k bytes. In theory, there's no relationship between
k and m. A typical computer, however, can fit an address within a word, so
in practice, if we have word addressability (i.e., if m > 1), then we probably
have k ≤ m.
6.
A gigabyte (GB) = 2 30 bytes, so with 32-bit addresses, we can access 2³²
bytes of memory = 4 gigabytes (4 GB). With 64-bit addresses we can
address 2⁴ * 2⁶⁰ bytes = 16 exabytes (16 EB).
7.
A combinatorial logic circuit has no loops; it corresponds to a boolean
expression for each of its outputs. A sequential logic circuit combines a
combinatorial logic circuit and memory into a loop (in addition to having
inputs and outputs). A sequential logic circuit has a state; a combinatorial
circuit simply performs operations.
8.
We separate the calculation of the new state from the update of the state
because if the two are intermingled, some of the calculations may be
incorrect. (The calculations that use already-updated parts of the state
might produce values that differ from the values that would have been
produced if the state hadn’t been partially updated.) A clock is used to
CS 350: Comp Org & Asm Pgm’g
– 12 –
© James Sasaki, 2015
Illinois Institute of Technology
Activity 22
signal whether we’re doing calculations or state update. Calculation is done
during half the clock cycle, so the the length of the clock cycle must be ≥
twice the time for the slowest calculation.
9.
A master-slave flip-flop contains two D-latches, say D₀ and D₁ with the
output of D₀ connected to the input of D₁. If D₀ has (state) value x and D₁
has value y, then the flip-flop’s output is y. Say D₀ has input value z. When
the clock signal is low, D₀ changes its state and output to z but D₁ ignores
its input value z and continues to output y as the flip-flop’s output. When
the clock signal is high, D₁ changes its state and output to z. Since z goes to
the combinatorial circuit, the circuit may change the value it sends to D₀
from x to some value w. But D₀ ignores its input when the clock signal is
high, so it ignores w and continues to send y to D₁.
CS 350: Comp Org & Asm Pgm’g
– 13 –
© James Sasaki, 2015