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Using XILINX ISE DESIGN SUITE 14.7 WebPack create the following PlanAhead projects
targeting a specific FPGA device located on the Nexys2 board.
1. Modeling Latches and Flip-Flops
Task1: An SR latch (Set/Reset) is an asynchronous device: it works independently of control
signals and relies only on the state of the S and R inputs. The symbol, the circuit using NOR
gates, and the truth table are shown below [1].
Simulate the design.
Assign S input to K1 and R input to K2. Assign Q to LED1 and Qbar to LED2. Implement the
design and verify the functionality in hardware.
Task2: The gated SR latch is a simple extension of the SR latch which provides an Enable
line [1].
Make the truth table of the circuit.
Simulate the design.
Implement the design and verify the functionality in hardware.
Task3: The D latch (D for "data") or transparent latch is a simple extension of the gated SR
latch that removes the possibility of invalid input states (metastability) [1].
Design a D latch. Simulate the design. Assign D input to K1, and Enable input to K2. Assign
Q to LED1 and Qbar to LED2.
Implement the design and verify the functionality in hardware.
Task4: Model the D Flip-Flop with Asynchronous Preset and Clear (FDCP)
Simulate the design.
2. Modeling Registers and Counters
Task5: Study the behavior of a 16-Bit Cascadable Binary Counter with Clock Enable and
Asynchronous Clear (CB16CE) and write it’s logic table.
Task 6: An N-bit shift register contains N flip-flops. At each clock pulse data are shifted from
one flip-flop to the next.
a) To build a shift register, it is necessary to divide the FPGA internal frequency
(50 MHz). Using two 16-bit binary counters, the final frequency will be around 1.5 Hz
that is quite good to see the leds blinking.
Name the design Divider and assign the clock input to port B8, and the output to LED1.
Implement the design and verify the functionality in hardware.
b) Create the Divider symbol, following the steps listed in
http://uni-obuda.hu/users/lovassyr/Digital_technics_II_lab/Digital_technics_II_lab.pdf
c) Design a 4-bit shift register from D flip-flops. The clock pulse is given by the Divider.
Implement the design and verify the functionality in hardware.
Task 7: Design a 4-bit ring counter from D flip-flops. The clock pulse is given by the
Divider.
Implement the design and verify the functionality in hardware.
References:
[1] www.xilinx.com; Lab Workbook; Modeling Latches and Flip-flops