NVRAM for the computer scientist Kevin Marquet INSA Lyon / CITI Lab / INRIA Socrate March 20th, 2015 1 / 20 A computer CPU DRAM Disk 2 / 20 A computer CPU DRAM Access time : 50ns Loose data when not powered Disk 2 / 20 A computer CPU DRAM Disk Access time : 50ns Loose data when not powered Access time : 100000 ns Retains data when not powered 2 / 20 NVRAMs Read/Write times, scalability, density, energy consumption 3 / 20 NVRAMs Read/Write times, scalability, density, energy consumption PCM I Read time : 100ns I Write time : 200ns 3 / 20 NVRAMs Read/Write times, scalability, density, energy consumption MRAM I Read time : 10ns I Write time : 20ns 3 / 20 NVRAM for mass storage CPU DRAM Disk 4 / 20 NVRAM for mass storage CPU DRAM NVRAM Disk 4 / 20 NVRAM for mass storage CPU DRAM NVRAM Disk I Dedicated file systems I Database in NVRAM 4 / 20 DRAM + NVRAM CPU DRAM Disk 5 / 20 DRAM + NVRAM CPU NVRAM DRAM Disk 5 / 20 DRAM + NVRAM CPU NVRAM DRAM Disk I DRAM + PCM : More RAM I DRAM + PCM : wear-Leveling I ... 5 / 20 Architecture CPU DRAM Disk 6 / 20 Architecture L1 Cache CPU L2 Cache DRAM Disk 6 / 20 Architecture L1 Cache CPU L2 Cache DRAM Disk I 4x more, 2x slower ? I L1 ? L2 ? L3 ? I Several technologies ? 6 / 20 NVRAM as working memory CPU DRAM Disk 7 / 20 NVRAM as working memory CPU NVRAM DRAM Disk 7 / 20 NVRAM as working memory CPU NVRAM DRAM Disk Existing works with PCM : I Endurance problem I Performance w.r.t. DRAM I Energy consumption increases 7 / 20 NVRAM as the only memory CPU DRAM Disk 8 / 20 NVRAM as the only memory CPU DRAM NVRAM Disk 8 / 20 NVRAM as the only memory CPU DRAM NVRAM Disk I Impact on the implementation (Harvard/Von Neumann architecture) 8 / 20 Operating system I Paging... Frame n Page table (in RAM) Virtual address CPU ... Physical address Frame 5 Frame 4 MMU Frame 3 Frame 2 Frame 1 TLB Frame 0 DRAM 9 / 20 Operating system I Paging... I ...vs. file system 9 / 20 Operating system : boot and reboot ? I Installation and launch CPU DRAM Disk 10 / 20 Operating system : boot and reboot ? I Installation and launch CPU DRAM Disk 10 / 20 Operating system : boot and reboot ? I Installation and launch CPU DRAM Disk 10 / 20 Operating system : boot and reboot ? I Installation and launch CPU DRAM NVRAM Disk 10 / 20 Operating system : boot and reboot ? I Installation and launch CPU DRAM NVRAM Disk I No reboot... I I I bug ? reset ? Checkpoint ? Compilation I I produce new executable files decides when to checkpoint ? 10 / 20 Programming model I With DRAM + Disk : decide what is persistent I With NVRAM : decide what is non-persistent 11 / 20 Peripherals 12 / 20 Glory ? Test my ideas, publish, be famous 13 / 20 Glory ? ? Test my ideas, publish, be famous Buy a computer that includes MRAM 13 / 20 Glory ? ? Test my ideas, publish, be famous Buy a computer that includes MRAM 13 / 20 Simulation ;-( 14 / 20 Simulation ;-( I Not so bad 14 / 20 Simulation ;-( I Not so bad I I Explore memory hierarchies Feedback to architects I Extrapolate from dram accesses : No ! I Emulate : yes (but not so easy) 14 / 20 Which technology ? I Which technology is realistic ? I Understand the technology 15 / 20 Which technology ? I Which technology is realistic ? I Understand the technology 15 / 20 What about us ? I Internet of Things I Energy harvesting Capacitor voltage (V) 3.5 3.0 2.5 2.0 Init 5000 5200 No chkpt 5400 5600 Chkpt success 5800 Time (ms) 6000 Restore 6200 6400 16 / 20 Why now ? I Because architects will (again) design CPUs impossible to program I ...or we can help design these CPUs I Lots of recent works I Real platform appeared recently 17 / 20 Conclusion I Can lead to huge changes in computer science I Simulation necessary, for now I Feedback to architects I Memory hierarchy depends on the use case Which technology is viable ? I I Always in motion the future is... 18 / 20 Credits I I Bibliography : kevinmarquet.net/research/nvram Pictures : I Small bib: andrebourgeois.fr/ImageBibliotheque.JPG I Big bib : www.10escadron.com/bibliotheque/ I Mram: ndl.hanyang.ac.kr/xe/files/attach/images/79/790/001/10.png I Javacard: javacard.vetilles.com/wp-content/uploads/2008/09/gemalto-jc3.jpg I Rolex: blog.titanblack.co.uk/wp-content/uploads/2013/04/ Platinum-Rolex-Daytona-Basel-2013.jpg I Files : nixlinux.com/wp-content/uploads/2014/04/61tdpgruLeL._SL1500_.jpg I Elf: www.johnloomis.org/microchip/pic32/elf/Elf-layout.png I Key: http://www.businesshi-lite.co.za/wp-content/uploads/2012/06/ key-small-1024x768.jpg I Sensor: www.libelium.com/libelium-images/generico/waspmote_ radiation_sensor_board-1000.png I Wislab: wislab.cz/media/content-images/WislabNode-S-description.png I Simulation: www.mpg.de/698541/standard.jpeg 19 / 20 Backup : fetch-decode-execute Decode Fetch Execute 20 / 20
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