1. No category

Objectives: Memory Organization and Access
Comparison of the DRAM & SRAM; ROM Memory
● ([O’H&Bryant, fig 6.2])
Ref: [O’H&Bryant, sect 6.1–6.4] or [Tanembaum, sect 3.3]
SRAM
DRAM
● know what are the basic types of (main) memory and their characteristics
● to understand how physical addresses are structured according to DRAM
transistors / bit
6
1
rel. access time
1×
10×
persistent
yes
no
sensitive
no
yes
rel. cost
100×
1×
use
?
?
Both of these are ‘volatile’: data is lost if power is off.
organization, and the mechanism of DRAM access
● Read Only Memory (ROM) – non-volatile (state persists if power is off)
● know how DRAM chips are organized within a memory controller
■ programs (e.g. the BIOS) stored in ROM are termed firmware
Memory Organization and Access
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Memory Types
Memory Organization and Access
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Organization of Physical Addresses
● SRAM (Static Random Access Memory)
■ basis is the D-latch [Tanembaum, fig
● physical addresses are structured into 3 components: DRAM chip number, and row
and column addresses within the chip
3.23]
■ can hold 1 bit
■ requires 11 transistors (can be done in 6)
■ state persists providing power is on
● DRAM (Dynamic RAM)
■ requires 1 capacitor and 1 transistor!
■ capacitor stores just 40,000 electrons!
■ has a time constant of 10−3 sec
■ hence requires refresh (typically
10-100ms)
Memory Organization and Access
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❛ ✁✂✄✄
❧☎✆✂
❞✁❛✆✄☎✄❞✞✁
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(courtesy of Dowd, High Performance Computing, O’Reilly Press)
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Memory Organization and Access
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Accessing Memory
Organization and Access of (DRAM) Memory Chip
([O’H&Bryant, fig 6.4])
([O’H&Bryant, fig 6.6])
● processor/memory communicate over a shared bus (transactions)
● read transaction:
■ CPU places address on system bus; I/O bridge forwards to memory bus
■ main memory reads address and places content on memory bus
■ CPU reads word from system bus and copies to register
1. select row address (RAS = 2)
2. select column address (CAS = 1)
● write transaction:
3. access the bits of the selected supercell
■ as above, but main memory waits to receive data
● why is the address bus 2 bits wide?
● why not a single index (0–15) per bit?
Memory Organization and Access
● n.b. memory is byte-addressable, i.e. address X + 1 refers to 1 byte after address X
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The Memory Module and Controller
Dual Inline Memory Module (DIMM, 168 pins; [O’H&Bryant, fig 6.5])
Memory Organization and Access
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Memory Organization and Access
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