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KING FAHD UNIVERSITY OF PETROLEUM & MINERALS
Electrical Engineering Department
EE 200 Digital Logic Circuit Design
Syllabus - Term 143
Catalog Description
Number systems & codes. Logic gates. Boolean Algebra. Karnaugh maps. Analysis and
synthesis of combinational systems, decoders, multiplexers, adders and subtractors,
PLA's. Types of flip-flops. Memory concept. Registers. Introduction to sequential circuit
design.
Prerequisite: Calculus I (MATH 101), General Physics I (PHYS 101)
Instructor Dr. Aiman H. El-Maleh.
Room: 22/407-5
Email: [email protected]
Phone: 2811
Office Hours UT 12:15-1:00 PM, and by appointment
Course Objectives
1. Introduce the students to the digital principles with emphasis on logic design.
2. Familiarize the students with the necessary mathematical tools such as number
systems, codes, and Boolean algebra.
3. Learn the principles of analysis and design of combinational logic circuits
4. Learn the principles of analysis and design of sequential logic circuits.
Course Learning Outcomes
After successfully completing the course, the students will be able to
Outcome1:
apply knowledge of number systems, codes and Boolean algebra to the
analysis and design of digital logic circuits.
Outcome 2: identify, formulate, and solve engineering problems in the area of
digital logic circuit design.
Outcome 3: use the techniques, skills, and modern engineering tools such as logic
works, necessary for engineering practice.
Outcome 4: to function on multi-disciplinary teams through digital circuit
experiments and projects.
Outcome 5: to design a digital system, components or process to meet desired
needs within realistic constraints.
Textbook
M. Morris Mano and Michael D. Celleti , Digital Design with an introduction to the
Verilog HDL, Fifth Edition, Pearson, 2013.
Grading Policy
Discussions
Assignments
Quizzes
Lab
Exam I
Exam II
Final





4%
8%
8%
20%
15% (Sat., June 27, 1:00 PM)
20% (Sat., August 1, 1:00 PM)
25%
Attendance will be taken regularly. For each missed 2 classes, a penalty of 0.5 will be
deducted.
Excuses for officially authorized absences must be presented no later than one week
following resumption of class attendance.
Late assignments will be accepted but you will be penalized 10% per each late day.
A student caught cheating in any of the assignments will get 0 out of 8%.
No makeup will be made for missing Quizzes or Exams.
Tentative Course Outline and Schedule
Week
1
Date
June 7-8
June 9-10
Topics
Binary Numbers, Number Base Conversions,
Octal & Hexadecimal Numbers, Complements,
Signed Binary Numbers, Binary Codes
Binary Logic, Boolean Algebra: Axioms, Theorems
& Properties. Boolean functions, Digital Logic
Gates
Canonical & Standard Forms, More Logical
June 16-17
Operations, Simplification of Boolean functions
Using K-Maps, Product of Sums Simplification.
Don’t-care Conditions, NAND, NOR, and Other
June 21-22
Two Level Implementations, Exclusive-OR
Function.
Combinational Logic: Analysis and Design
June 23-24
Procedures, Code Conversion, Adder circuits.
June 14-15
2
3
Sections
Labs/Prob. Sessions
1.1-1.3
No Lab.
Introduction to Lab.
Equipment, Exp#1: Binary
& Decimal Numbers
1.4-1.7
1.9,
2.1-2.4
2.7-2.8
No Lab.
2.5-2.6
3.1-3.5
Exp#2: Digital Logic Gates
3.6-3.9,310
4.1-4.4
Exp#3: Introduction to
LogicWorks
Exp#4: Boolean Algebra
First Major Exam. Saturday June 27, 2015, Time 1:00-3:00 PM
4
June 28-29
June 30July 1
July 5-6
5
July 7-8
Subtractors, Decimal Adder, binary multiplier,
Magnitude Comparator, Decoders.
Encoders and Multiplexers, Random Access
Memory
Programmable Logic, PLD’S, ROM, Programmable
Logic Array, Programmable Array Logic.
Sequential Circuits, Latches, Flip-flops,
Characteristic Tables
4.5-4.8
4.9-4.11,
7.2, 7.3
7.5-7.7
5.1-5.4
Exp#5: Simplification
Exp#6: Code Conversion
Exp#7: Adders/Subtractors
Exp#8: Multiplexers
Ramadhan Break July 12-23
6
July 25-26
Analysis of Clocked Sequential Circuits, State
Reduction and Assignment.
5.5, 5.7
Exp#9: Design with ROM's
July 27-28
Flip-flop Excitation Tables, Design Procedure,
Synthesis using different flip flops.
5.8
Exp#10: Flip-flops
Second Major Exam, Saturday August 1, Time 1:00-3:00 PM
7
8
August 2-3
Registers and Shift Registers
6.1, 6.2
Exp#11: Counters &
Sequential Logic
August 4-5
Ripple Counters, Synchronous Counters and other
counters.
6.3-6.5
No Lab
August 910
Revision
Lab Final