April/14/2015 Errata_c17w22-23_20 S1C17 Family Technical Manual Errata ITEM The operation when “Display Off” is selected Object manual Document code Object item Page S1C17M01 Technical Manual 412361701 17.5.2 Display On/Off 17-6 S1C17W22/W23 Technical Manual 412690402 18.5.2 Display On/Off 18-7 S1C17W15 Technical Manual 412645702 17.5.2 Display On/Off 17-6 S1C17W14/W16 Technical Manual 412910300 18.5.2 Display On/Off 18-6 (Error) When “Display off” is selected, the drive voltage supply stops and the LCD driver pin outputs are all set to VSS level. Since “All on” and “All off” directly control the driving waveform output by the LCD driver, data in the display data RAM is not altered. The common pins are set to dynamic drive for “All on” and to static drive for “All off.” This function can be used to make the display flash on and off without altering the display memory. (Correct) When “Display off” is selected, the drive voltage supply stops and the LCD driver pin outputs are all set to VSS level. Since “All on” and “All off” directly control the driving waveform output by the LCD driver, data in the display data RAM is not altered. The common pins are set to dynamic drive for “All on” and to static drive for “All off.” This function can be used to make the display flash on and off without altering the display memory. Note: When “Display off” is selected, VC4 ( or VC3)’s electric charge must be discharged with the procedure shown below. <Using Internal Generation Mode> 1. Set the LCD8PWR.VCEN bit to 0. (Disable LCD voltage regulator) 2. Set the LCD8PWR.HVLD bit to 1. (Enable heavy load protection mode) 3. When CLK_LCDxx is stopped, it must be stopped after VC4 ( or VC3 )’s electric potential became less than VDD – 1V. <Using External Voltage Application Mode> 1. Disable the external voltage. 2. Set the LCD8PWR.HVLD bit to 1. (Enable heavy load protection mode) 3. When CLK_LCDxx is stopped, it must be stopped after VC4 ( or VC3 )’s electric potential became less April/14/2015 Errata_c17w22-23_20 than VDD – 1V. When “Display on” is selected again, it should be in a reverse procedure of the above description. Nov/14/2014 Errata_c17w22-23_19 S1C17 Family Technical Manual Errata ITEM Slave Operation in 10-bit Address Mode Object manual Document code Object item Page S1C17M01 Technical Manual 412361700 Slave Operations in 10-bit Address 13-14 Mode S1C17F13 Technical Manual 412486300 Slave Operations in 10-bit Address 12-14 Mode S1C17W22/W23 Technical Manual 412690401 Slave Operations in 10-bit Address 14-14 Mode S1C17W15 Technical Manual 412645701 Slave Operations in 10-bit Address 14-14 Mode (Error) Figure:Example of Data Transfer Starting Operations in 10-bit Address Mode(Slave Mode) (Correct) Figure: Example of Data Transfer Starting Operations in 10-bit Address Mode(Slave Mode) Nov/14/2014 Errata_c17w22-23_18 S1C17 Family Technical Manual Errata ITEM CLG OSC3A Control Register Object manual Document code Object item Page S1C17M01 Technical Manual 412361700 Overview, Input Pin 10-1 S1C17F13 Technical Manual 412486300 Overview, Input Pin 9-1 S1C17W22/W23 Technical Manual 412690401 Overview, Input Pin 11-1 S1C17W15 Technical Manual 412645701 Overview, Input Pin 11-1 (Error) Overview Figure:Configuration of a T16 Channel (Correct) Overview Figure:Configuration of a T16 Channel Nov/14/2014 Errata_c17w22-23_18 (Error) Input Pin (Correct) Nov/14/2014 Errata_c17w22-23_17 S1C17 Family Technical Manual Errata ITEM 16-bit Timers (T16) Object manual Document code Object item Page S1C17M01 Technical Manual 412361700 Control Registers 10-5 S1C17F13 Technical Manual 412486300 Control Registers 9-5 S1C17W22/W23 Technical Manual 412690401 Control Registers 11-5 S1C17W15 Technical Manual 412645701 Control Registers 11-5 (Error) T16 Ch.n Mode Register : Bit0 TRMD This bit selects the T16 operation mode. 1 (R/W): One-shot mode 0 (R/W): Repeat mode For detailed information on the operation mode, refer to “Operations in One-shot Mode” and “Operations in Repeat Mode.” (Correct) T16 Ch.n Mode Register : Bit0 TRMD This bit selects the T16 operation mode. 1 (R/W): One-shot mode 0 (R/W): Repeat mode For detailed information on the operation mode, refer to “Operations in One-shot Mode” and “Operations in Repeat Mode.” Note: When one-shot mode is set, the T16_nTR.TR[15:0] bits should be set to a value equal to or greater than 0x0001. Nov/14/2014 Errata_c17w22-23_16 S1C17 Family Technical Manual Errata ITEM 16-bit Timers (T16) Object manual Document code Object item Page S1C17M01 Technical Manual 412361700 Overview, Input Pin 10-1 S1C17F13 Technical Manual 412486300 Overview, Input Pin 9-1 S1C17W22/W23 Technical Manual 412690401 Overview, Input Pin 11-1 S1C17W15 Technical Manual 412645701 Overview, Input Pin 11-1 (Error) Overview Figure:Configuration of a T16 Channel (Correct) Overview (Error) Input Pin Figure:Configuration of a T16 Channel Nov/14/2014 Errata_c17w22-23_16 If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function. The EXCLm signal can be input through the chattering filter. For more information, refer to the “I/O Ports” chapter. (Correct) Input Pin If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function. For more information, refer to the “I/O Ports” chapter. Nov/14/2014 errata_c17w22-23_15 S1C17 Family Technical Manual Errata ITEM Electrical Characteristics EXOSC external clock input characteristics Object manual Document Object item Page code S1C17W22/W23 Technical Manual 412690401 23.5 Clock Generator (CLG) 23-6 Generator (CLG) 20-6 Characteristics S1C17W15 Technical Manual 412645701 20.5 Clock Characteristics (Error) (Correct) Nov/14/2014 errata_c17w22-23_15 ITEM Electrical Characteristics R/F Converter (RFC) Characteristics Object manual Document Object item Page code S1C17W22/W23 Technical Manual 412690401 23.13 R/F Converter (RFC) 23-16 Converter (RFC) 20-16 Characteristics S1C17W15 Technical Manual 412645701 20.13 R/F Characteristics (Error) (Correct) Nov/14/2014 errata_c17w22-23_15 ITEM Electrical Characteristics Object manual Input/Output Port (PPORT) Characteristics Document Object item Page 23.7 Input/Output Port (PPORT) 23-7 code S1C17W22/W23 Technical Manual 412690401 Characteristics S1C17W15 Technical Manual 412645701 20.7 Input/Output Port (PPORT) 20-7 Characteristics Page 23-7 S1C17W22/W23 Technical Manual 23.7 Input/Output Port (PPORT) Characteristics (Error) (Correct) Page 20-7 S1C17W15 Technical Manual 20.7 Input/Output Port (PPORT) Characteristics Nov/14/2014 errata_c17w22-23_15 (Error) (Correct) Nov/7/2014 errata_c17w22-23_14 S1C17 Family Technical Manual Errata ITEM Mounting Precautions Object manual Document code Object item Page S1C17M01 Technical Manual 412361700 Mounting Precautions AP-C-1 S1C17F13 Technical Manual 412486300 Mounting Precautions AP-C-1 S1C17W22/W23 Technical Manual 412690401 Mounting Precautions AP-C-1 S1C17W15 Technical Manual 412645701 Mounting Precautions AP-C-1 (Error) VPP pin Connect CVPP to this pin if the VPP voltage is not stable. (Correct) VPP pin If fluctuations in the Flash programming voltage VPP is large, connect a capacitor CVPP between the VSS and VPP pins to suppress fluctuations within VPP ± 1 V. The CVPP should be placed as close to the VPP pin as possible and use a sufficiently thick wiring pattern that allows current of several tens of mA to flow. V PP pin connection example Pin V PP CVPP V SS Pin V PP CVPP V SS Nov/7/2014 errata_c17w22-23_13 S1C17 Family Technical Manual Errata ITEM Basic External Connection Diagram Object manual Document code Object item Page S1C17W22/W23 Technical Manual 412690401 Basic External Connection Diagram 24-3 S1C17W15 Technical Manual 412645701 Basic External Connection Diagram 21-2 (Error) Symbol Name Recommended components … … … X’tal3 Crystal resonator CA-301 (1 MHz) manufactured by Seiko Epson Corporation … … … (Correct) Symbol Name Recommended components … … … X’tal3 Crystal resonator CA-301 (4 MHz) manufactured by Seiko Epson Corporation … … … Nov/7/2014 errata_c17w22-23_12 S1C17 Family Technical Manual Errata ITEM Supply Voltage Detector (SVD) Object manual Document code Object item Page S1C17M01 Technical Manual 412361700 Operations, Control Registers 9-3, 9-7 S1C17F13 Technical Manual 412486300 Operations, Control Registers 8-3, 8-7 S1C17W22/W23 Technical Manual 412690401 Operations, Control Registers 10-3, 10-7 S1C17W15 Technical Manual 412645701 Operations, Control Registers 10-3, 10-7 (Error) Reading detection results The following two detection results can be obtained by reading the SVDINTF.SVDDT bit: • Power supply voltage (VDD or EXSVD) ≥ Comparison voltage when SVDINTF.SVDDT bit = 0 • Power supply voltage (VDD or EXSVD) < Comparison voltage when SVDINTF.SVDDT bit = 1 Before reading the SVDINTF.SVDDT bit, wait for at least SVD circuit enable response time after 1 is written to the SVDCTL.MODEN bit (refer to “Supply Voltage Detector Characteristics, SVD circuit enable response time tSVDEN” in the “Electrical Characteristics” chapter). After the SVDCTL.SVDC[4:0] bits setting value is altered to change the comparison voltage when the SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time tSVD” in the “Electrical Characteristics”chapter). (Correct) Reading detection results The following two detection results can be obtained by reading the SVDINTF.SVDDT bit: • Power supply voltage (VDD or EXSVD) ≥ SVD detection voltage VSVD when SVDINTF.SVDDT bit = 0 • Power supply voltage (VDD or EXSVD) < SVD detection voltage VSVD when SVDINTF.SVDDT bit = 1 Before reading the SVDINTF.SVDDT bit, wait for at least SVD circuit enable response time after 1 is written to the SVDCTL.MODEN bit (refer to “Supply Voltage Detector Characteristics, SVD circuit enable response time tSVDEN” in the “Electrical Characteristics” chapter). After the SVDCTL.SVDC[4:0] bits setting value is altered to change the SVD detection voltage VSVD when the SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time tSVD” in the “Electrical Characteristics”chapter). (Error) Bit 8 SVDDT The power supply voltage detection results can be read out from this bit. Nov/7/2014 errata_c17w22-23_12 1 (R): Power supply voltage (VDD or EXSVD) < comparison voltage 0 (R): Power supply voltage (VDD or EXSVD) ≥ comparison voltage (Correct) Bit 8 SVDDT The power supply voltage detection results can be read out from this bit. 1 (R): Power supply voltage (VDD or EXSVD) < SVD detection voltage VSVD 0 (R): Power supply voltage (VDD or EXSVD) ≥ SVD detection voltage VSVD Sep/11/2014 errata_c17w22-23_11 S1C17 Family Technical Manual Errata ITEM OSC3 oscillator circuit characteristics Object manual Document Object item Page code S1C17W22/W23 Technical Manual 412690401 23 Electrical Characteristics 23-6 S1C17W15 Technical Manual 412645701 20 Electrical Characteristics 20-6 (Error) (Correct) 0x3 0x3 0x2 0x2 0x1 0x1 0x0 0x0 Sep/11/2014 errata_c17w22-23_10 S1C17 Family Technical Manual Errata ITEM Supply Voltage Detector (SVD) Characteristics Object manual Document Object item Page code S1C17W22/W23 Technical Manual 412690401 23 Electrical Characteristics 23-9 S1C17W15 Technical Manual 412645701 20 Electrical Characteristics 20-9 (Error) (Correct) SVDCTL.SVDC[4:0] 0x1e Aug/28/2014 errata_c17w22-23_9 S1C17 Family Technical Manual errata ITEM: Port Input / Output Control Object manuals Document codes Items Pages S1C17M01 Technical Manual 412361700 6.4.2 Port Input / Output Control P.6-5 S1C17F13 Technical Manual 412486300 6.4.2 Port Input / Output Control P.6-5 S1C17W22/W23 412690401 6.4.2 Port Input / Output Control P.6-5 412645701 6.4.2 Port Input / Output Control P.6-5 Technical Manual S1C17W15 Technical Manual (Error) Reading input data from a GPIO port The data (1 = high input, 0 = low input) input from the Pxy pin can be read out from the PxDAT.PxINy bit. (Correct) Reading input data from a GPIO port The data (1 = high input, 0 = low input) input from the Pxy pin can be read out from the PxDAT.PxINy bit. Note: PxDAT.PxINy bits retain the input port state before 1 CLK that CPU reads (Error) Chattering filter function (Skip) 2 Input sampling time = ———————————————— [second] (Eq.6.2) CLK_PPORT frequency [Hz] (Correct) Chattering filter function (Skip) 2~3 Input sampling time = ———————————————— [second] (Eq.6.2) CLK_PPORT frequency [Hz] Aug/28/2014 errata_c17w22-23_8 S1C17 Family Technical Manual errata ITEM: 12-bit A/D Converter(ADC12A) Control Registers Object manuals Document codes Items Pages S1C17W22/W23 412690401 20.6 Control Registers P.20-7, 20-8 Technical Manual (Error) Bit 1 ADST This bit starts A/D conversion or enables to accept triggers. 1 (R/W): Start sampling and conversion (software trigger)/Enable trigger acceptance (external trigger, 16-bit timer underflow trigger) 0 (R/W): Terminate conversion This bit does not revert to 0 automatically after A/D conversion has completed. Write 0 to this bit onceand write 1 again to start another A/D conversion. After 0 is written to this bit to forcefully terminateconversion, the ADC12A stops after the A/D conversion being executed is completed. Therefore, this bit cannot be used to determine whether the ADC12A is executing A/D conversion or not. (Correct) Bit 1 ADST This bit starts A/D conversion or enables to accept triggers. 1 (R/W): Start sampling and conversion (software trigger)/Enable trigger acceptance (external trigger, 16-bit timer underflow trigger) 0 (R/W): Terminate conversion This bit does not revert to 0 automatically after A/D conversion has completed. Write 0 to this bit onceand write 1 again to start another A/D conversion. After 0 is written to this bit to forcefully terminateconversion, the ADC12A stops after the A/D conversion being executed is completed. Therefore, this bit cannot be used to determine whether the ADC12A is executing A/D conversion or not. Note: retain the 1 during CLK_T16_k ≥ 1 CLK and the 0 during CLK_T16_k ≥ 2 CLK. Aug/28/2014 errata_c17w22-23_8 (Error) Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. (Slip Table 20.6.4) Note: A/D conversion will not be performed if the ADC_nCFG.VRANGE[1:0] bits = 0x0. Set these bits to 0x3 to perform A/D conversion. (Correct) Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. (Slip Table 20.6.4) Note: A/D conversion will not be performed if the ADC_nCFG.VRANGE[1:0] bits = 0x0. Set these bits to 0x3 to perform A/D conversion. Note: When ADC12_nCTL.BSYSTAT bit = 1, the ADC circuit current IADC current flows if the ADC_nCFG.VRANGE[1:0] bits = 0x3 is set. Aug/28/2014 errata_c17w22-23_7 S1C17 Family Technical Manual errata ITEM: Appendix A List of Peripheral Circuit Control Registers Object manuals S1C17W22/W23 Manual (Error) (Correct) Technical Document codes Items 412690401 List Pages of Registers Peripheral Circuit Control AP-A-3, AP-A-22 Aug/28/2014 errata_c17w22-23_6 S1C17 Family Technical Manual errata ITEM: 12-bit A/D Converter(ADC12A) Control Registers Object manuals S1C17W22/W23 Technical Document codes Items Pages 412690401 20.6 Control Registers 20-6, 20-7 Manual (Error) Bits 14–12 A DSTAT[2:0] These bits indicate the analog input pin number m being A/D converted. (skip Table 19.6.1) These bits indicate the pin number that follows the last converted analog input pin after A/D conversionis forcefully terminated by writing 0 to the ADC12_nCTL.ADST bit or automatically terminated in onetime conversion mode (ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. (Correct) Bits 14–12 A DSTAT[2:0] These bits indicate the analog input pin number m being A/D converted. (skip Table 19.6.1) These bits indicate the pin number that is the last converted analog input pin after A/D conversionis forcefully terminated by writing 0 to the ADC12_nCTL.ADST bit or automatically terminated in onetime conversion mode (ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. (Error) Bit 10 BSYSTAT This bit indicates whether the ADC12A is executing A/D conversion or not. 1 (R/W): A/D converting 0 (R/W): Idle (Correct) Aug/28/2014 errata_c17w22-23_6 Bit 10 BSYSTAT This bit indicates whether the ADC12A is executing A/D conversion or not. 1 (R/W): A/D converting 0 (R/W): Idle Note: The ADC12_nCTL.BSYSTAT bit is cleared to 0 when the clock is supplied to ADC12A by setting the ADC12_nCTL.MODEN bit to 1. Jul/30/2014 errata_c17w22-23_5 S1C17 Family Technical Manual errata ITEM: PWG2 Auto mode operations Object manuals S1C17W22/W23 Technical Document codes Items Pages 412690401 2.1.3 Operations 2-3 412645701 2.1.3 Operations 2-3 Manual S1C17W15 Technical Manual (Error) 4. When the slp instruction is executed in normal mode (only OSC1 operates during SLEEP) After a lapse of 1 ms from transition to SLEEP mode, the hardware switches from normal mode to economy mode and sets the PWGINTF.MODCMPIF bit to 1. (Correct) 4. When the slp instruction is executed in normal mode (only OSC1 operates during SLEEP) After a lapse of 1 ms from transition to SLEEP mode, the hardware switches from normal mode to economy mode and sets the PWGINTF.MODCMPIF bit to 1. Note: The IC does not enter economy mode if a clock source other than OSC1 is active when the slp instruction is executed. Therefore, stop clock sources other than OSC1 before executing the slp instruction. July/30/2014 errata_c17w22-23_4 S1C17 Family Technical Manual Errata ITEM 16-bit PWM Timers(T16B) Object manual T16B Ch.n Compare/Capture m Data Register Document Object item Page 15 16-bit PWM Timers(T16B) 15-30 Appendix A List of Peripheral AP-A-16 Circuit Control Registers AP-A-17 code S1C17W22/W23 Technical Manual 412690401 AP-A-18 AP-A-19 S1C17W15 Technical Manual 412645701 15 16-bit PWM Timers(T16B) 15-30 Appendix A List of Peripheral AP-A-15 Circuit Control Registers AP-A-16 AP-A-17 (Error) 15.6 Control Register (Correct) 15.6 Control Register (Error) Appendix A (Common) July/30/2014 errata_c17w22-23_4 (S1C17W23 only) (Correct) Appendix A (Common) (S1C17W23 only) July/30/2014 errata_c17w22-23_3 S1C17 Family Technical Manual Errata ITEM OSC3 oscillator circuit characteristics Object manual Document Object item Page code S1C17W22/W23 Technical Manual 412690401 23 Electrical Characteristics 23-5 S1C17W15 Technical Manual 412645701 20 Electrical Characteristics 20-5 (Error) OSC3 oscillator circuit characteristics (Correct) OSC3 oscillator circuit characteristics July/30/2014 errata_c17w22-23_2 S1C17 Family Technical Manual Errata Item Watchdog Timer (WDT) NMI function Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 8.1 Overview 8-1 S1C17W22/W23 Technical Manual 412690401 8.1 Overview 8-1 S1C17M01 Technical Manual 412361700 7.1 Overview 7-1 S1C17F13 Technical Manual 412486300 7.1 Overview 7-1 (Error) WDT restarts the system if a problem occurs, such as when the program cannot be executed normally. The features of WDT are listed below. • Includes a 10-bit up counter to count NMI/reset generation cycle. • A counter clock source and clock division ratio are selectable. • Counter overflow generates a reset or NMI. Figure 8.1.1 shows the configuration of WDT. (Correct) WDT restarts the system if a problem occurs, such as when the program cannot be executed normally. The features of WDT are listed below. • Includes a 10-bit up counter to count NMI/reset generation cycle. • A counter clock source and clock division ratio are selectable. • Counter overflow generates a reset or NMI. Internal data bus Figure 8.1.1 shows the configuration of WDT. Clock Generator WDT WDTRUN[3:0] WDTCNTRST CLK_WDT CLKSRC[1:0] CLKDIV[1:0] DBRUN 10-bit counter Reset request July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 8.3.1 WDT Control 8-2 S1C17W22/W23 Technical Manual 412690401 8.3.1 WDT Control 8-2 S1C17M01 Technical Manual 412361700 7.3.1 WDT Control 7-2 S1C17F13 Technical Manual 412486300 7.3.1 WDT Control 7-2 (Error) WDT should be initialized and started up with the procedure listed below. 1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Configure the WDT operating clock. 3. Configure the WDTCTL.NMIXRST bit. (Select NMI or reset mode) 4. Write 1 to the WDTCTL.WDTCNTRST bit. (Reset WDT counter) 5. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits. (Start up WDT) 6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) (Correct) WDT should be initialized and started up with the procedure listed below. 1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Configure the WDT operating clock. 3. Configure the WDTCTL.NMIXRST bit. 3. Write 1 to the WDTCTL.WDTCNTRST bit. (Select NMI or reset mode) (Reset WDT counter) 4. Write a value other than 0xa to the WDTCTL.WDTRUN[3:0] bits. (Start up WDT) 5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 8.3.1 WDT Control 8-2 S1C17W22/W23 Technical Manual 412690401 8.3.1 WDT Control 8-2 S1C17M01 Technical Manual 412361700 7.3.1 WDT Control 7-2 S1C17F13 Technical Manual 412486300 7.3.1 WDT Control 7-2 (Error) WDT generates a system reset (WDTCTL.NMIXRST bit = 0) or NMI (WDTCTL.NMIXRST bit = 1) when the counter overflows. To avert system restart by WDT, its embedded counter must be reset periodically via software while WDT is running. (Correct) WDT generates a system reset (WDTCTL.NMIXRST bit = 0) or NMI (WDTCTL.NMIXRST bit = 1) when the counter overflows. To avert system restart by WDT, its embedded counter must be reset periodically via software while WDT is running. July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 8.3.1 WDT Control 8-2 S1C17W22/W23 Technical Manual 412690401 8.3.1 WDT Control 8-2 S1C17M01 Technical Manual 412361700 7.3.1 WDT Control 7-2 S1C17F13 Technical Manual 412486300 7.3.1 WDT Control 7-2 (Error) A location should be provided for periodically processing this routine. Process this routine within the tWDT cycle. After resetting, WDT starts counting with a new NMI/reset generation cycle. If WDT is not reset within the tWDT cycle for any reason, the CPU is switched to interrupt processing by NMI or reset, the interrupt vector is read out, and the interrupt handler routine is executed. If the counter overflows and generates an NMI without WDT being reset, the WDTCTL.STATNMI bit is set to 1. (Correct) A location should be provided for periodically processing this routine. Process this routine within the tWDT cycle. After resetting, WDT starts counting with a new NMI/reset generation cycle. If WDT is not reset within the tWDT cycle for any reason, the CPU is switched to interrupt processing by NMI or reset, the interrupt vector is read out, and the interrupt handler routine system reset is executed. If the counter overflows and generates an NMI without WDT being reset, the WDTCTL.STATNMI bit is set to 1. July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 8.3.2 Operations in HALT and SLEEP Modes 8-2 S1C17W22/W23 Technical Manual 412690401 8.3.2 Operations in HALT and SLEEP Modes 8-2 S1C17M01 Technical Manual 412361700 7.3.2 Operations in HALT and SLEEP Modes 7-2 S1C17F13 Technical Manual 412486300 7.3.2 Operations in HALT and SLEEP Modes 7-2 (Error) During HALT mode WDT operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed. To disable WDT in HALT mode, stop WDT by writing 0xa to the WDTCTL.WDTRUN[3:0] bits before executing the halt instruction. Reset WDT before resuming operations after HALT mode is cleared. During SLEEP mode WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed. Therefore, stop WDT by setting the WDTCTL.WDTRUN[3:0] bits before executing the slp instruction. If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the WDTCTL.WDTRUN[3:0] bits. (Correct) During HALT mode WDT operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed. To disable WDT in HALT mode, stop WDT by writing 0xa to the WDTCTL.WDTRUN[3:0] bits before executing the halt instruction. Reset WDT before resuming operations after HALT mode is cleared. During SLEEP mode WDT operates in SLEEP mode if the selected clock source is running. In this case SLEEP mode is cleared by an NMI or reset if it continues for more than the NMI/reset generation cycle and the NMI or reset handler is executed. Therefore, stop WDT by setting the WDTCTL.WDTRUN[3:0] bits before executing the slp instruction. If the clock source stops in SLEEP mode, WDT stops. To prevent generation of an unnecessary NMI or reset after clearing SLEEP mode, reset WDT before executing the slp instruction. WDT should also be stopped as required using the WDTCTL.WDTRUN[3:0] bits. July/30/2014 errata_c17w22-23_2 Object Manual Document Object Item Page Code S1C17W15 Technical Manual S1C17W22/W23 Technical 412645701 412690401 Manual S1C17M01 Technical Manual S1C17F13 Technical Manual 412361700 412486300 8.4 Control Registers 8-3, 8-4, Appendix A P-AP-4 List of Peripheral Circuit Control Registers 8.4 Control Registers 8-3, 8-4 Appendix A P-AP-4 List of Peripheral Circuit Control Registers 7.4 Control Registers 7-2 Appendix A P-AP-4 List of Peripheral Circuit Control Registers 7.4 Control Registers 7-3, 7-4 Appendix A P-AP-3 List of Peripheral Circuit Control Registers (Error) Bits 15–10 Reserved Bit 9 NMIXRST This bit sets the WDT operating mode. 1 (R/WP): NMI mode 0 (R/WP): Reset mode This bit is used to select whether an NMI signal or a reset signal is output when WDT has not been reset within the NMI/reset generation cycle. Bit 8 STATNMI This bit indicates that a counter overflow and NMI have occurred. 1 (R): NMI (counter overflow) occurred 0 (R): NMI not occurred When the NMI generation function of WDT is used, read this bit in the NMI handler routine to confirm that WDT was the source of the NMI. The STATNMI set to 1 is cleared to 0 by resetting WDT. Bits 7–5 (Correct) Register name WDTCTL Bits 15-5 Reserved Bit Bit name Initial Reset R/W 15-5 4 3-0 WDTCNTRST WDTRUN[3:0] 0x000 0 0xa H0 H0 R WP R/WP Reserved Remarks Always set to 0 Always read as 0 - July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 1.1 Features 1-1 S1C17W22/W23 Technical Manual 412690401 1.1 Features 1-1 S1C17M01 Technical Manual 412361700 1.1 Features 1-1 S1C17F13 Technical Manual 412486300 1.1 Features 1-2 (誤) (正) Timers Watchdog Timer (WDT) Generates NMI or watchdog timer reset. July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 2.4.2 Transition between Operating Modes 2-15 S1C17W22/W23 Technical Manual 412690401 2.4.2 Transition between Operating Modes 2-15 S1C17M01 Technical Manual 412361700 2.4.2 Transition between Operating Modes 2-11 S1C17F13 Technical Manual 412486300 2.4.2 Transition between Operating Modes 2-12 (Error) Canceling HALT or SLEEP mode The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Debug interrupt • Reset request (Correct) Canceling HALT or SLEEP mode The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Debug interrupt • Reset request July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 5.1 Overview 5-1 S1C17W22/W23 Technical Manual 412690401 5.1 Overview 5-1 S1C17M01 Technical Manual 412361700 5.1 Overview 5-1 S1C17F13 Technical Manual 412486300 5.1 Overview 5-1 (Error) (Correct) July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 5.2 Vector Table 5-1 S1C17W22/W23 Technical Manual 412690401 5.2 Vector Table 5-1 S1C17M01 Technical Manual 412361700 5.2 Vector Table 5-1 S1C17F13 Technical Manual 412486300 5.2 Vector Table 5-1 (Error) (Correct) 2 (0x02) TTBR + 0x08 NMI - 4 July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 5.2 Vector Table 5-3 S1C17W22/W23 Technical Manual 412690401 5.2 Vector Table 5-3 S1C17M01 Technical Manual 412361700 5.2 Vector Table 5-3 S1C17F13 Technical Manual 412486300 5.2 Vector Table 5-3 (Error) *2 Either reset or NMI can be selected as the watchdog timer interrupt with software. (Correct) *2 Either reset or NMI can be selected as the watchdog timer interrupt with software. July/30/2014 errata_c17w22-23_2 Object Manual Document Code Object Item Page S1C17W15 Technical Manual 412645701 5.5 NMI 5-4 S1C17W22/W23 Technical Manual 412690401 5.5 NMI 5-4 S1C17M01 Technical Manual 412361700 5.5 NMI 5-4 S1C17F13 Technical Manual 412486300 5.5 NMI 5-4 (Error) The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes precedence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. (Correct) This IC cannot generate non-maskable interrupt (NMI). Jul/4/2014 errata_c17w22-23_1 S1C17 Family Technical Manual Errata ITEM Unused pins Object manual Document Object item Page Appendix C Mounting Precautions AP-C-2 code S1C17W22/W23 Technical Manual 412690401 (Error) Unused pins (4) CV1–2 pins If super economy mode is not used, these pins should be left open. (Correct) Unused pins (4) CV1–2 and VD2 pins If super economy mode is not used, the CV1 and CV2 pins should be left open. In this case, CPW3 can be omitted by connecting between the VDD and VD2 pins directly. When these pins are not short-circuited, CPW3 is required even if super economy mode is not used.
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